summaryrefslogtreecommitdiffstats
path: root/tools/perf/pmu-events/arch/x86/icelake/cache.json
blob: d26c4efe35f0b386b9e4bd7c9793282eb4d6e9c5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
[
    {
        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "EventCode": "0xF1",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "UMask": "0x1f"
    },
    {
        "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
        "EventCode": "0xF2",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
        "EventCode": "0xF2",
        "EventName": "L2_LINES_OUT.SILENT",
        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
        "EventCode": "0xf2",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "L2 code requests",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "PublicDescription": "Counts the total number of L2 code requests.",
        "SampleAfterValue": "200003",
        "UMask": "0xe4"
    },
    {
        "BriefDescription": "Demand Data Read requests",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
        "SampleAfterValue": "200003",
        "UMask": "0xe1"
    },
    {
        "BriefDescription": "Demand requests that miss L2 cache",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
        "PublicDescription": "Counts demand requests that miss L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x27"
    },
    {
        "BriefDescription": "Demand requests to L2 cache",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
        "PublicDescription": "Counts demand requests to L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0xe7"
    },
    {
        "BriefDescription": "RFO requests to L2 cache",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_RFO",
        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
        "SampleAfterValue": "200003",
        "UMask": "0xe2"
    },
    {
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
        "SampleAfterValue": "200003",
        "UMask": "0xc4"
    },
    {
        "BriefDescription": "L2 cache misses when fetching instructions",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "PublicDescription": "Counts L2 cache misses when fetching instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x24"
    },
    {
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0xc1"
    },
    {
        "BriefDescription": "Demand Data Read miss L2, no rejects",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
        "SampleAfterValue": "200003",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "This event is deprecated.",
        "Deprecated": "1",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x3f"
    },
    {
        "BriefDescription": "This event is deprecated.",
        "Deprecated": "1",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.REFERENCES",
        "SampleAfterValue": "200003",
        "UMask": "0xff"
    },
    {
        "BriefDescription": "RFO requests that hit L2 cache",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_HIT",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0xc2"
    },
    {
        "BriefDescription": "RFO requests that miss L2 cache",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_MISS",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x22"
    },
    {
        "BriefDescription": "SW prefetch requests that hit L2 cache.",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_HIT",
        "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
        "SampleAfterValue": "200003",
        "UMask": "0xc8"
    },
    {
        "BriefDescription": "SW prefetch requests that miss L2 cache.",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_MISS",
        "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
        "SampleAfterValue": "200003",
        "UMask": "0x28"
    },
    {
        "BriefDescription": "L2 writebacks that access L2 cache",
        "EventCode": "0xF0",
        "EventName": "L2_TRANS.L2_WB",
        "PublicDescription": "Counts L2 writebacks that access L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
        "SampleAfterValue": "100003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Retired load instructions.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
        "PEBS": "1",
        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
        "SampleAfterValue": "1000003",
        "UMask": "0x81"
    },
    {
        "BriefDescription": "Retired store instructions.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_STORES",
        "PEBS": "1",
        "PublicDescription": "Counts all retired store instructions.",
        "SampleAfterValue": "1000003",
        "UMask": "0x82"
    },
    {
        "BriefDescription": "All retired memory instructions.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ANY",
        "PEBS": "1",
        "PublicDescription": "Counts all retired memory instructions - loads and stores.",
        "SampleAfterValue": "1000003",
        "UMask": "0x83"
    },
    {
        "BriefDescription": "Retired load instructions with locked access.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with locked access.",
        "SampleAfterValue": "100007",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
        "SampleAfterValue": "100003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
        "PEBS": "1",
        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
        "SampleAfterValue": "100003",
        "UMask": "0x42"
    },
    {
        "BriefDescription": "Retired load instructions that miss the STLB.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
        "PEBS": "1",
        "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x11"
    },
    {
        "BriefDescription": "Retired store instructions that miss the STLB.",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
        "PEBS": "1",
        "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x12"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
        "SampleAfterValue": "20011",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
        "SampleAfterValue": "20011",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
        "PEBS": "1",
        "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "SampleAfterValue": "20011",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
        "Data_LA": "1",
        "EventCode": "0xd4",
        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
        "PEBS": "1",
        "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
        "SampleAfterValue": "100007",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
        "SampleAfterValue": "100007",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
        "SampleAfterValue": "100021",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
        "SampleAfterValue": "100021",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
        "SampleAfterValue": "50021",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C0004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C0004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1E003C0004",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1E003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1E003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C0400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C0400",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0010",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0010",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0010",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C0010",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C0010",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2)  that hit a cacheline in the L3 where a snoop was sent.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1E003C0010",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0020",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0020",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C0020",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C0020",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C0020",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1E003C0020",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.HWPF_L3.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C2380",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x4003C8000",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2003C8000",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1003C8000",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1E003C8000",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3FC03C0800",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Demand and prefetch data reads",
        "EventCode": "0xB0",
        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Counts memory transactions sent to the uncore.",
        "EventCode": "0xB0",
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
        "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "PublicDescription": "Cycles where at least 1 outstanding data read request is pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
        "EventCode": "0xF4",
        "EventName": "SQ_MISC.BUS_LOCK",
        "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles the queue waiting for offcore responses is full.",
        "EventCode": "0xf4",
        "EventName": "SQ_MISC.SQ_FULL",
        "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    }
]