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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-15 19:40:15 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-15 19:40:15 +0000 |
commit | 399644e47874bff147afb19c89228901ac39340e (patch) | |
tree | 1c4c0b733f4c16b5783b41bebb19194a9ef62ad1 /man4/msr.4 | |
parent | Initial commit. (diff) | |
download | manpages-399644e47874bff147afb19c89228901ac39340e.tar.xz manpages-399644e47874bff147afb19c89228901ac39340e.zip |
Adding upstream version 6.05.01.upstream/6.05.01
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'man4/msr.4')
-rw-r--r-- | man4/msr.4 | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/man4/msr.4 b/man4/msr.4 new file mode 100644 index 0000000..c499a6e --- /dev/null +++ b/man4/msr.4 @@ -0,0 +1,42 @@ +.\" Copyright (c) 2009 Intel Corporation, Author Andi Kleen +.\" Some sentences copied from comments in arch/x86/kernel/msr.c +.\" +.\" SPDX-License-Identifier: Linux-man-pages-copyleft +.\" +.TH msr 4 2022-10-30 "Linux man-pages 6.05.01" +.SH NAME +msr \- x86 CPU MSR access device +.SH DESCRIPTION +.I /dev/cpu/CPUNUM/msr +provides an interface to read and write the model-specific +registers (MSRs) of an x86 CPU. +.I CPUNUM +is the number of the CPU to access as listed in +.IR /proc/cpuinfo . +.PP +The register access is done by opening the file and seeking +to the MSR number as offset in the file, and then +reading or writing in chunks of 8 bytes. +An I/O transfer of more than 8 bytes means multiple reads or writes +of the same register. +.PP +This file is protected so that it can be read and written only by the user +.IR root , +or members of the group +.IR root . +.SH NOTES +The +.I msr +driver is not auto-loaded. +On modular kernels you might need to use the following command +to load it explicitly before use: +.PP +.in +4n +.EX +$ modprobe msr +.EE +.in +.SH SEE ALSO +Intel Corporation Intel 64 and IA-32 Architectures +Software Developer's Manual Volume 3B Appendix B, +for an overview of the Intel CPU MSRs. |