diff options
Diffstat (limited to '')
-rw-r--r-- | tests/cap-ide | 346 |
1 files changed, 346 insertions, 0 deletions
diff --git a/tests/cap-ide b/tests/cap-ide new file mode 100644 index 0000000..01a9e09 --- /dev/null +++ b/tests/cap-ide @@ -0,0 +1,346 @@ +e1:00.0 Class 0800: Device aaaa:bbbb + Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- + Interrupt: pin ? routed to IRQ 255 + Region 0: Memory at 20014000000 (64-bit, prefetchable) [disabled] + Region 1: Memory at <unassigned> (32-bit, non-prefetchable) [disabled] + Region 2: Memory at 20018013000 (64-bit, prefetchable) [disabled] + Region 3: Memory at <unassigned> (32-bit, non-prefetchable) [disabled] + Expansion ROM at dc2c0000 [disabled] + Capabilities: [40] Power Management version 3 + Flags: PMEClk- DSI- D1+ D2- AuxCurrent=0mA PME(D0+,D1+,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [70] Express (v2) Endpoint, IntMsgNum 0 + DevCap: MaxPayload 1024 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us + ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 75W TEE-IO+ + DevCtl: CorrErr+ NonFatalErr+ FatalErr+ UnsupReq- + RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+ FLReset- + MaxPayload 512 bytes, MaxReadReq 512 bytes + DevSta: CorrErr+ NonFatalErr- FatalErr- UnsupReq+ AuxPwr- TransPend- + LnkCap: Port #0, Speed 32GT/s, Width x16, ASPM not supported + ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+ + LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 32GT/s, Width x16 + TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + DevCap2: Completion Timeout: Not Supported, TimeoutDis+ NROPrPrP- LTR+ + 10BitTagComp+ 10BitTagReq+ OBFF Not Supported, ExtFmt+ EETLPPrefix+, MaxEETLPPrefixes 1 + EmergencyPowerReduction Not Supported, EmergencyPowerReductionInit- + FRS- TPHComp- ExtTPHComp- + AtomicOpsCap: 32bit+ 64bit+ 128bitCAS+ + DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis- + AtomicOpsCtl: ReqEn- + IDOReq- IDOCompl- LTR+ EmergencyPowerReductionReq- + 10BitTagReq+ OBFF Disabled, EETLPPrefixBlk- + LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS- + LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis- + Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS- + Compliance Preset/De-emphasis: -6dB de-emphasis, 0dB preshoot + LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete+ EqualizationPhase1+ + EqualizationPhase2+ EqualizationPhase3+ LinkEqualizationRequest- + Retimer- 2Retimers- CrosslinkRes: unsupported + Capabilities: [100 v2] Advanced Error Reporting + UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol- + UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO+ CmpltAbrt- UnxCmplt+ RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol- + CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- AdvNonFatalErr+ + AERCap: First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- ECRCChkEn- + MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap- + HeaderLog: 00000000 00000000 00000000 00000000 + Capabilities: [148 v1] Single Root I/O Virtualization (SR-IOV) + IOVCap: Migration- 10BitTagReq+ IntMsgNum 0 + IOVCtl: Enable- Migration- Interrupt- MSE- ARIHierarchy+ 10BitTagReq- + IOVSta: Migration- + Initial VFs: 4, Total VFs: 4, Number of VFs: 0, Function Dependency Link: 00 + VF offset: 32, stride: 1, Device ID: 50a5 + Supported Page Size: 00000553, System Page Size: 00000001 + Region 0: Memory at 000001fff8000000 (64-bit, prefetchable) + Region 2: Memory at 000002001800c000 (64-bit, prefetchable) + VF Migration: offset: 00000000, BIR: 0 + Capabilities: [188 v1] Alternative Routing-ID Interpretation (ARI) + ARICap: MFVC- ACS-, Next Function: 1 + ARICtl: MFVC- ACS-, Function Group: 0 + Capabilities: [1c0 v1] Secondary PCI Express + LnkCtl3: LnkEquIntrruptEn- PerformEqu- + LaneErrStat: 0 + Capabilities: [3b0 v1] Physical Layer 16.0 GT/s <?> + Capabilities: [400 v1] Lane Margining at the Receiver + PortCap: Uses Driver- + PortSta: MargReady+ MargSoftReady- + Capabilities: [450 v1] Access Control Services + ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd- EgressCtrl- DirectTrans- + Capabilities: [460 v1] Physical Layer 32.0 GT/s <?> + Capabilities: [5f0 v1] Process Address Space ID (PASID) + PASIDCap: Exec+ Priv+, Max PASID Width: 10 + PASIDCtl: Enable+ Exec- Priv- + Capabilities: [830 v1] Integrity & Data Encryption + IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+ + IDECtl: FTEn- + SelectiveIDE#0 Cap: RID#=1 + SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0 + SelectiveIDE#0 Sta: insecure RecvChkFail- + SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0 + SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0 + Capabilities: [e00 v2] Data Object Exchange + DOECap: IntSup- + DOECtl: IntEn- + DOESta: Busy- IntSta- Error- ObjectReady- +00: aa aa bb bb 00 00 10 00 00 00 00 08 10 00 80 00 +10: 0c 00 00 14 00 02 00 00 0c 30 01 18 00 02 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +30: 00 00 2c dc 40 00 00 00 00 00 00 00 ff 00 00 00 +40: 01 70 03 da 08 00 00 00 05 70 80 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 11 70 00 00 40 00 00 00 50 00 00 00 00 00 00 00 +70: 10 00 02 00 23 80 2c 51 57 29 09 00 05 f1 43 00 +80: 40 00 05 11 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 90 0b 73 00 00 14 00 00 3e 00 80 01 +a0: 05 00 1e 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 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