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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-06-07 05:48:42 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-06-07 05:48:42 +0000
commitcec1877e180393eba0f6ddb0cf97bf3a791631c7 (patch)
tree47b4dac2a9dd9a40c30c251b4d4a72d7ccf77e9f /compiler/rustc_codegen_cranelift
parentAdding debian version 1.74.1+dfsg1-1. (diff)
downloadrustc-cec1877e180393eba0f6ddb0cf97bf3a791631c7.tar.xz
rustc-cec1877e180393eba0f6ddb0cf97bf3a791631c7.zip
Merging upstream version 1.75.0+dfsg1.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'compiler/rustc_codegen_cranelift')
-rw-r--r--compiler/rustc_codegen_cranelift/.cirrus.yml2
-rw-r--r--compiler/rustc_codegen_cranelift/.github/workflows/main.yml10
-rw-r--r--compiler/rustc_codegen_cranelift/.vscode/settings.json2
-rw-r--r--compiler/rustc_codegen_cranelift/Cargo.lock170
-rw-r--r--compiler/rustc_codegen_cranelift/Cargo.toml20
-rw-r--r--compiler/rustc_codegen_cranelift/Readme.md22
-rw-r--r--compiler/rustc_codegen_cranelift/build_system/build_backend.rs2
-rw-r--r--compiler/rustc_codegen_cranelift/build_system/build_sysroot.rs9
-rw-r--r--compiler/rustc_codegen_cranelift/build_system/main.rs2
-rw-r--r--compiler/rustc_codegen_cranelift/build_system/prepare.rs7
-rw-r--r--compiler/rustc_codegen_cranelift/build_system/tests.rs68
-rw-r--r--compiler/rustc_codegen_cranelift/build_system/utils.rs45
-rw-r--r--compiler/rustc_codegen_cranelift/config.txt2
-rw-r--r--compiler/rustc_codegen_cranelift/example/mini_core.rs6
-rw-r--r--compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs11
-rw-r--r--compiler/rustc_codegen_cranelift/example/neon.rs234
-rw-r--r--compiler/rustc_codegen_cranelift/example/std_example.rs6
-rw-r--r--compiler/rustc_codegen_cranelift/patches/0001-portable-simd-Allow-internal-features.patch24
-rw-r--r--compiler/rustc_codegen_cranelift/patches/0002-rand-Disable-failing-test.patch24
-rw-r--r--compiler/rustc_codegen_cranelift/patches/0003-rand-Disable-rand-tests-on-mingw.patch47
-rw-r--r--compiler/rustc_codegen_cranelift/patches/0027-coretests-128bit-atomic-operations.patch2
-rw-r--r--compiler/rustc_codegen_cranelift/patches/portable-simd-lock.toml304
-rw-r--r--compiler/rustc_codegen_cranelift/patches/rand-lock.toml563
-rw-r--r--compiler/rustc_codegen_cranelift/patches/regex-lock.toml422
-rw-r--r--compiler/rustc_codegen_cranelift/patches/stdlib-lock.toml49
-rw-r--r--compiler/rustc_codegen_cranelift/rust-toolchain2
-rw-r--r--compiler/rustc_codegen_cranelift/scripts/setup_rust_fork.sh31
-rwxr-xr-xcompiler/rustc_codegen_cranelift/scripts/test_bootstrap.sh4
-rwxr-xr-xcompiler/rustc_codegen_cranelift/scripts/test_rustc_tests.sh43
-rw-r--r--compiler/rustc_codegen_cranelift/src/abi/mod.rs43
-rw-r--r--compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs17
-rw-r--r--compiler/rustc_codegen_cranelift/src/abi/returning.rs4
-rw-r--r--compiler/rustc_codegen_cranelift/src/allocator.rs4
-rw-r--r--compiler/rustc_codegen_cranelift/src/analyze.rs4
-rw-r--r--compiler/rustc_codegen_cranelift/src/base.rs22
-rw-r--r--compiler/rustc_codegen_cranelift/src/cast.rs10
-rw-r--r--compiler/rustc_codegen_cranelift/src/common.rs77
-rw-r--r--compiler/rustc_codegen_cranelift/src/concurrency_limiter.rs3
-rw-r--r--compiler/rustc_codegen_cranelift/src/constant.rs10
-rw-r--r--compiler/rustc_codegen_cranelift/src/debuginfo/emit.rs3
-rw-r--r--compiler/rustc_codegen_cranelift/src/debuginfo/line_info.rs31
-rw-r--r--compiler/rustc_codegen_cranelift/src/debuginfo/mod.rs27
-rw-r--r--compiler/rustc_codegen_cranelift/src/debuginfo/object.rs7
-rw-r--r--compiler/rustc_codegen_cranelift/src/debuginfo/unwind.rs4
-rw-r--r--compiler/rustc_codegen_cranelift/src/driver/aot.rs85
-rw-r--r--compiler/rustc_codegen_cranelift/src/driver/jit.rs3
-rw-r--r--compiler/rustc_codegen_cranelift/src/global_asm.rs134
-rw-r--r--compiler/rustc_codegen_cranelift/src/inline_asm.rs438
-rw-r--r--compiler/rustc_codegen_cranelift/src/intrinsics/cpuid.rs74
-rw-r--r--compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs19
-rw-r--r--compiler/rustc_codegen_cranelift/src/intrinsics/llvm_aarch64.rs112
-rw-r--r--compiler/rustc_codegen_cranelift/src/intrinsics/llvm_x86.rs606
-rw-r--r--compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs66
-rw-r--r--compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs39
-rw-r--r--compiler/rustc_codegen_cranelift/src/lib.rs44
-rw-r--r--compiler/rustc_codegen_cranelift/src/pointer.rs5
-rw-r--r--compiler/rustc_codegen_cranelift/src/pretty_clif.rs22
-rw-r--r--compiler/rustc_codegen_cranelift/src/value_and_place.rs103
58 files changed, 2509 insertions, 1640 deletions
diff --git a/compiler/rustc_codegen_cranelift/.cirrus.yml b/compiler/rustc_codegen_cranelift/.cirrus.yml
index 8b4efd4e3..aa1a2bad2 100644
--- a/compiler/rustc_codegen_cranelift/.cirrus.yml
+++ b/compiler/rustc_codegen_cranelift/.cirrus.yml
@@ -3,7 +3,7 @@ task:
freebsd_instance:
image: freebsd-13-2-release-amd64
setup_rust_script:
- - pkg install -y git bash
+ - pkg install -y git bash binutils
- curl https://sh.rustup.rs -sSf --output rustup.sh
- sh rustup.sh --default-toolchain none -y --profile=minimal
target_cache:
diff --git a/compiler/rustc_codegen_cranelift/.github/workflows/main.yml b/compiler/rustc_codegen_cranelift/.github/workflows/main.yml
index 652d6eca3..47d9a3b93 100644
--- a/compiler/rustc_codegen_cranelift/.github/workflows/main.yml
+++ b/compiler/rustc_codegen_cranelift/.github/workflows/main.yml
@@ -50,10 +50,12 @@ jobs:
- os: ubuntu-latest
env:
TARGET_TRIPLE: aarch64-unknown-linux-gnu
- # s390x requires QEMU 6.1 or greater, we could build it from source, but ubuntu 22.04 comes with 6.2 by default
- os: ubuntu-latest
env:
TARGET_TRIPLE: s390x-unknown-linux-gnu
+ - os: ubuntu-latest
+ env:
+ TARGET_TRIPLE: riscv64gc-unknown-linux-gnu
- os: windows-latest
env:
TARGET_TRIPLE: x86_64-pc-windows-msvc
@@ -92,6 +94,12 @@ jobs:
sudo apt-get update
sudo apt-get install -y gcc-s390x-linux-gnu qemu-user
+ - name: Install riscv64gc toolchain and qemu
+ if: matrix.env.TARGET_TRIPLE == 'riscv64gc-unknown-linux-gnu'
+ run: |
+ sudo apt-get update
+ sudo apt-get install -y gcc-riscv64-linux-gnu qemu-user
+
- name: Prepare dependencies
run: ./y.sh prepare
diff --git a/compiler/rustc_codegen_cranelift/.vscode/settings.json b/compiler/rustc_codegen_cranelift/.vscode/settings.json
index 60cb51d56..834a1362c 100644
--- a/compiler/rustc_codegen_cranelift/.vscode/settings.json
+++ b/compiler/rustc_codegen_cranelift/.vscode/settings.json
@@ -33,7 +33,7 @@
]
},
{
- "sysroot_src": "./download/sysroot/sysroot_src/library",
+ "sysroot_src": "./build/stdlib/library",
"crates": [
{
"root_module": "./example/std_example.rs",
diff --git a/compiler/rustc_codegen_cranelift/Cargo.lock b/compiler/rustc_codegen_cranelift/Cargo.lock
index af8e43da4..dcb6cc575 100644
--- a/compiler/rustc_codegen_cranelift/Cargo.lock
+++ b/compiler/rustc_codegen_cranelift/Cargo.lock
@@ -15,9 +15,9 @@ dependencies = [
[[package]]
name = "anyhow"
-version = "1.0.66"
+version = "1.0.75"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "216261ddc8289130e551ddcd5ce8a064710c0d064a4d2895c67151c92b5443f6"
+checksum = "a4668cab20f66d8d020e1fbc0ebe47217433c1b6c8f2040faf858554e394ace6"
[[package]]
name = "arbitrary"
@@ -26,12 +26,6 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e2d098ff73c1ca148721f37baad5ea6a465a13f9573aba8641fbbbae8164a54e"
[[package]]
-name = "autocfg"
-version = "1.1.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
-
-[[package]]
name = "bitflags"
version = "1.3.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
@@ -39,9 +33,9 @@ checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
[[package]]
name = "bumpalo"
-version = "3.11.1"
+version = "3.14.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "572f695136211188308f16ad2ca5c851a712c464060ae6974944458eb83880ba"
+checksum = "7f30e7476521f6f8af1a1c4c0b8cc94f0bee37d91763d0ca2665f299b6cd8aec"
[[package]]
name = "cfg-if"
@@ -51,18 +45,18 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
[[package]]
name = "cranelift-bforest"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ec27af72e56235eb326b5bf2de4e70ab7c5ac1fb683a1829595badaf821607fd"
+checksum = "f773437307980ac0f424bf9b9a5d0cd21a0f17248c6860c9a65bec8b5975f3fe"
dependencies = [
"cranelift-entity",
]
[[package]]
name = "cranelift-codegen"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2231e12925e6c5f4bc9c95b62a798eea6ed669a95bc3e00f8b2adb3b7b9b7a80"
+checksum = "443c2ac50e97fb7de1a0f862753fce3f27215558811a6fcee508eb0c3747fa79"
dependencies = [
"bumpalo",
"cranelift-bforest",
@@ -72,7 +66,7 @@ dependencies = [
"cranelift-entity",
"cranelift-isle",
"gimli",
- "hashbrown 0.13.2",
+ "hashbrown 0.14.0",
"log",
"regalloc2",
"smallvec",
@@ -81,39 +75,39 @@ dependencies = [
[[package]]
name = "cranelift-codegen-meta"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "413b00b8dfb3aab85674a534677e7ca08854b503f164a70ec0634fce80996e2c"
+checksum = "c5b174c411480c79ce0793c55042fa51bec27e486381d103a53cab3b480cb2db"
dependencies = [
"cranelift-codegen-shared",
]
[[package]]
name = "cranelift-codegen-shared"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cd0feb9ecc8193ef5cb04f494c5bd835e5bfec4bde726e7ac0444fc9dd76229e"
+checksum = "73fa0151a528066a369de6debeea4d4b23a32aba68b5add8c46d3dc8091ff434"
[[package]]
name = "cranelift-control"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "72eedd2afcf5fee1e042eaaf18d3750e48ad0eca364a9f5971ecfdd5ef85bf71"
+checksum = "b8adf1e6398493c9bea1190e37d28a0eb0eca5fddbc80e01e506cda34db92b1f"
dependencies = [
"arbitrary",
]
[[package]]
name = "cranelift-entity"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7af19157be42671073cf8c2a52d6a4ae1e7b11f1dcb4131fede356d9f91c29dd"
+checksum = "4917e2ed3bb5fe87d0ed88395ca6d644018d119a034faedd1f3e1f2c33cd52b2"
[[package]]
name = "cranelift-frontend"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c2dc7636c5fad156be7d9ae691cd1aaecd97326caf2ab534ba168056d56aa76c"
+checksum = "9aaadf1e7cf28886bbf046eaf7ef538997bc8a7e020e578ea4957b39da87d5a1"
dependencies = [
"cranelift-codegen",
"log",
@@ -123,15 +117,15 @@ dependencies = [
[[package]]
name = "cranelift-isle"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c1111aea4fb6fade5779903f184249a3fc685a799fe4ec59126f9af59c7c2a74"
+checksum = "a67fda31b9d69eaa1c49a2081939454c45857596a9d45af6744680541c628b4c"
[[package]]
name = "cranelift-jit"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "dadf88076317f6286ec77ebbe65978734fb43b6befdc96f52ff4c4c511841644"
+checksum = "d6bf32710628e7ff298739f1ed80a0bfdafc0c6a3e284c4540b23f18e8889d4b"
dependencies = [
"anyhow",
"cranelift-codegen",
@@ -149,9 +143,9 @@ dependencies = [
[[package]]
name = "cranelift-module"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c6bae8a82dbf82241b1083e57e06870d2c2bdc9852727be99d58477513816953"
+checksum = "4d693e93a0fbf56b4bc93cffe6b107c2e52f070e1111950505fc8c83ac440b9d"
dependencies = [
"anyhow",
"cranelift-codegen",
@@ -160,9 +154,9 @@ dependencies = [
[[package]]
name = "cranelift-native"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1ecfc01a634448468a698beac433d98040033046678a0eed3ca39a3a9f63ae86"
+checksum = "76fb52ba71be98312f35e798d9e98e45ab2586f27584231bf7c644fa9501e8af"
dependencies = [
"cranelift-codegen",
"libc",
@@ -171,9 +165,9 @@ dependencies = [
[[package]]
name = "cranelift-object"
-version = "0.98.0"
+version = "0.101.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0ee14a7276999f0dcaae2de84043e2c2de50820fb89b3db56fab586a4ad26734"
+checksum = "2551b2e185022b89e9efa5e04c0f17f679b86ef73d9f7feabc48b608ff23120d"
dependencies = [
"anyhow",
"cranelift-codegen",
@@ -195,35 +189,29 @@ dependencies = [
[[package]]
name = "equivalent"
-version = "1.0.0"
+version = "1.0.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "88bffebc5d80432c9b140ee17875ff173a8ab62faad5b257da912bd2f6c1c0a1"
+checksum = "5443807d6dff69373d433ab9ef5378ad8df50ca6298caf15de6e52e24aaf54d5"
[[package]]
name = "fallible-iterator"
-version = "0.2.0"
+version = "0.3.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4443176a9f2c162692bd3d352d745ef9413eec5782a80d8fd6f8a1ac692a07f7"
+checksum = "2acce4a10f12dc2fb14a218589d4f1f62ef011b2d0cc4b3cb1bba8e94da14649"
[[package]]
name = "gimli"
-version = "0.27.2"
+version = "0.28.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ad0a93d233ebf96623465aad4046a8d3aa4da22d4f4beba5388838c8a434bbb4"
+checksum = "6fb8d784f27acf97159b40fc4db5ecd8aa23b9ad5ef69cdd136d3bc80665f0c0"
dependencies = [
"fallible-iterator",
- "indexmap 1.9.3",
+ "indexmap",
"stable_deref_trait",
]
[[package]]
name = "hashbrown"
-version = "0.12.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8a9ee70c43aaf417c914396645a0fa852624801b24ebb7ae78fe8272889ac888"
-
-[[package]]
-name = "hashbrown"
version = "0.13.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "43a3c133739dddd0d2990f9a4bdf8eb4b21ef50e4851ca85ab661199821d510e"
@@ -236,15 +224,8 @@ name = "hashbrown"
version = "0.14.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "2c6201b9ff9fd90a5a3bac2e56a830d0caa509576f0e503818ee82c181b3437a"
-
-[[package]]
-name = "indexmap"
-version = "1.9.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bd070e393353796e801d209ad339e89596eb4c8d430d18ede6a1cced8fafbd99"
dependencies = [
- "autocfg",
- "hashbrown 0.12.3",
+ "ahash",
]
[[package]]
@@ -259,9 +240,9 @@ dependencies = [
[[package]]
name = "libc"
-version = "0.2.138"
+version = "0.2.148"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "db6d7e329c562c5dfab7a46a2afabc8b987ab9a4834c9d1ca04dc54c1546cef8"
+checksum = "9cdc71e17332e86d2e1d38c1f99edcb6288ee11b815fb1a4b049eaa2114d369b"
[[package]]
name = "libloading"
@@ -275,12 +256,9 @@ dependencies = [
[[package]]
name = "log"
-version = "0.4.17"
+version = "0.4.20"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
-dependencies = [
- "cfg-if",
-]
+checksum = "b5e6163cb8c49088c2c36f57875e58ccd8c87c7427f7fbd50ea6710b2f3f2e8f"
[[package]]
name = "mach"
@@ -293,27 +271,27 @@ dependencies = [
[[package]]
name = "memchr"
-version = "2.5.0"
+version = "2.6.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "2dffe52ecf27772e601905b7522cb4ef790d2cc203488bbd0e2fe85fcb74566d"
+checksum = "8f232d6ef707e1956a43342693d2a31e72989554d58299d7a88738cc95b0d35c"
[[package]]
name = "object"
-version = "0.30.4"
+version = "0.32.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "03b4680b86d9cfafba8fc491dc9b6df26b68cf40e9e6cd73909194759a63c385"
+checksum = "77ac5bbd07aea88c60a577a1ce218075ffd59208b2d7ca97adf9bfc5aeb21ebe"
dependencies = [
"crc32fast",
- "hashbrown 0.13.2",
- "indexmap 1.9.3",
+ "hashbrown 0.14.0",
+ "indexmap",
"memchr",
]
[[package]]
name = "once_cell"
-version = "1.16.0"
+version = "1.18.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "86f0b0d4bf799edbc74508c1e8bf170ff5f41238e5f8225603ca7caaae2b7860"
+checksum = "dd8b5dd2ae5ed71462c540258bedcb51965123ad7e7ccf4b9a8cafaa4a63576d"
[[package]]
name = "regalloc2"
@@ -357,7 +335,7 @@ dependencies = [
"cranelift-native",
"cranelift-object",
"gimli",
- "indexmap 2.0.0",
+ "indexmap",
"libloading",
"object",
"smallvec",
@@ -366,15 +344,15 @@ dependencies = [
[[package]]
name = "slice-group-by"
-version = "0.3.0"
+version = "0.3.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "03b634d87b960ab1a38c4fe143b508576f075e7c978bfad18217645ebfdfa2ec"
+checksum = "826167069c09b99d56f31e9ae5c99049e932a98c9dc2dac47645b08dbbf76ba7"
[[package]]
name = "smallvec"
-version = "1.10.0"
+version = "1.11.0"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a507befe795404456341dfab10cef66ead4c041f62b8b11bbb92bffe5d0953e0"
+checksum = "62bb4feee49fdd9f707ef802e22365a35de4b7b299de4763d44bfea899442ff9"
[[package]]
name = "stable_deref_trait"
@@ -384,9 +362,9 @@ checksum = "a8f112729512f8e442d81f95a8a7ddf2b7c6b8a1a6f509a95864142b30cab2d3"
[[package]]
name = "target-lexicon"
-version = "0.12.5"
+version = "0.12.12"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "9410d0f6853b1d94f0e519fb95df60f29d2c1eff2d921ffdf01a4c8a3b54f12d"
+checksum = "14c39fd04924ca3a864207c66fc2cd7d22d7c016007f9ce846cbb9326331930a"
[[package]]
name = "version_check"
@@ -396,9 +374,9 @@ checksum = "49874b5167b65d7193b8aba1567f5c7d93d001cafc34600cee003eda787e483f"
[[package]]
name = "wasmtime-jit-icache-coherence"
-version = "11.0.0"
+version = "14.0.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e34eb67f0829a5614ec54716c8e0c9fe68fab7b9df3686c85f719c9d247f7169"
+checksum = "0980a96b16abbdaf829858d2389697b1d6cfc6a903873fd74b7e47a6b1045584"
dependencies = [
"cfg-if",
"libc",
@@ -438,9 +416,9 @@ dependencies = [
[[package]]
name = "windows-targets"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7b1eb6f0cd7c80c79759c929114ef071b87354ce476d9d94271031c0497adfd5"
+checksum = "9a2fa6e2155d7247be68c096456083145c183cbbbc2764150dda45a87197940c"
dependencies = [
"windows_aarch64_gnullvm",
"windows_aarch64_msvc",
@@ -453,42 +431,42 @@ dependencies = [
[[package]]
name = "windows_aarch64_gnullvm"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "91ae572e1b79dba883e0d315474df7305d12f569b400fcf90581b06062f7e1bc"
+checksum = "2b38e32f0abccf9987a4e3079dfb67dcd799fb61361e53e2882c3cbaf0d905d8"
[[package]]
name = "windows_aarch64_msvc"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b2ef27e0d7bdfcfc7b868b317c1d32c641a6fe4629c171b8928c7b08d98d7cf3"
+checksum = "dc35310971f3b2dbbf3f0690a219f40e2d9afcf64f9ab7cc1be722937c26b4bc"
[[package]]
name = "windows_i686_gnu"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "622a1962a7db830d6fd0a69683c80a18fda201879f0f447f065a3b7467daa241"
+checksum = "a75915e7def60c94dcef72200b9a8e58e5091744960da64ec734a6c6e9b3743e"
[[package]]
name = "windows_i686_msvc"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "4542c6e364ce21bf45d69fdd2a8e455fa38d316158cfd43b3ac1c5b1b19f8e00"
+checksum = "8f55c233f70c4b27f66c523580f78f1004e8b5a8b659e05a4eb49d4166cca406"
[[package]]
name = "windows_x86_64_gnu"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ca2b8a661f7628cbd23440e50b05d705db3686f894fc9580820623656af974b1"
+checksum = "53d40abd2583d23e4718fddf1ebec84dbff8381c07cae67ff7768bbf19c6718e"
[[package]]
name = "windows_x86_64_gnullvm"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7896dbc1f41e08872e9d5e8f8baa8fdd2677f29468c4e156210174edc7f7b953"
+checksum = "0b7b52767868a23d5bab768e390dc5f5c55825b6d30b86c844ff2dc7414044cc"
[[package]]
name = "windows_x86_64_msvc"
-version = "0.48.0"
+version = "0.48.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1a515f5799fe4961cb532f983ce2b23082366b898e52ffbce459c86f67c8378a"
+checksum = "ed94fce61571a4006852b7389a063ab983c02eb1bb37b47f8272ce92d06d9538"
diff --git a/compiler/rustc_codegen_cranelift/Cargo.toml b/compiler/rustc_codegen_cranelift/Cargo.toml
index 8ded81d73..30db10f74 100644
--- a/compiler/rustc_codegen_cranelift/Cargo.toml
+++ b/compiler/rustc_codegen_cranelift/Cargo.toml
@@ -8,15 +8,15 @@ crate-type = ["dylib"]
[dependencies]
# These have to be in sync with each other
-cranelift-codegen = { version = "0.98", features = ["unwind", "all-arch"] }
-cranelift-frontend = { version = "0.98" }
-cranelift-module = { version = "0.98" }
-cranelift-native = { version = "0.98" }
-cranelift-jit = { version = "0.98", optional = true }
-cranelift-object = { version = "0.98" }
+cranelift-codegen = { version = "0.101.2", default-features = false, features = ["std", "unwind", "all-arch"] }
+cranelift-frontend = { version = "0.101.2" }
+cranelift-module = { version = "0.101.2" }
+cranelift-native = { version = "0.101.2" }
+cranelift-jit = { version = "0.101.2", optional = true }
+cranelift-object = { version = "0.101.2" }
target-lexicon = "0.12.0"
-gimli = { version = "0.27.2", default-features = false, features = ["write"]}
-object = { version = "0.30.3", default-features = false, features = ["std", "read_core", "write", "archive", "coff", "elf", "macho", "pe"] }
+gimli = { version = "0.28", default-features = false, features = ["write"]}
+object = { version = "0.32", default-features = false, features = ["std", "read_core", "write", "archive", "coff", "elf", "macho", "pe"] }
indexmap = "2.0.0"
libloading = { version = "0.7.3", optional = true }
@@ -35,9 +35,9 @@ smallvec = "1.8.1"
[features]
# Enable features not ready to be enabled when compiling as part of rustc
-unstable-features = ["jit", "inline_asm"]
+unstable-features = ["jit", "inline_asm_sym"]
jit = ["cranelift-jit", "libloading"]
-inline_asm = []
+inline_asm_sym = []
[package.metadata.rust-analyzer]
rustc_private = true
diff --git a/compiler/rustc_codegen_cranelift/Readme.md b/compiler/rustc_codegen_cranelift/Readme.md
index 62eaef359..1a2b2bbc5 100644
--- a/compiler/rustc_codegen_cranelift/Readme.md
+++ b/compiler/rustc_codegen_cranelift/Readme.md
@@ -8,7 +8,7 @@ If not please open an issue.
## Building and testing
```bash
-$ git clone https://github.com/bjorn3/rustc_codegen_cranelift
+$ git clone https://github.com/rust-lang/rustc_codegen_cranelift
$ cd rustc_codegen_cranelift
$ ./y.sh prepare
$ ./y.sh build
@@ -29,7 +29,7 @@ Extract the `dist` directory in the archive anywhere you want.
If you want to use `cargo clif build` instead of having to specify the full path to the `cargo-clif` executable, you can add the `bin` subdirectory of the extracted `dist` directory to your `PATH`.
(tutorial [for Windows](https://stackoverflow.com/a/44272417), and [for Linux/MacOS](https://unix.stackexchange.com/questions/26047/how-to-correctly-add-a-path-to-path/26059#26059)).
-[releases]: https://github.com/bjorn3/rustc_codegen_cranelift/releases/tag/dev
+[releases]: https://github.com/rust-lang/rustc_codegen_cranelift/releases/tag/dev
## Usage
@@ -60,18 +60,14 @@ You need to do this steps to successfully compile and use the cranelift backend
2. Run `python x.py setup` and choose option for compiler (`b`).
3. Build compiler and necessary tools: `python x.py build --stage=2 compiler library/std src/tools/rustdoc src/tools/rustfmt`
* (Optional) You can also build cargo by adding `src/tools/cargo` to previous command.
-4. Copy exectutable files from `./build/host/stage2-tools/<your hostname triple>/release`
-to `./build/host/stage2/bin/`. Note that you would need to do this every time you rebuilt `rust` repository.
-5. Copy cargo from another toolchain: `cp $(rustup which cargo) .build/<your hostname triple>/stage2/bin/cargo`
- * Another option is to build it at step 3 and copy with other executables at step 4.
-6. Link your new `rustc` to toolchain: `rustup toolchain link stage2 ./build/host/stage2/`.
-7. (Windows only) compile the build system: `rustc +stage2 -O build_system/main.rs -o y.exe`.
-8. You need to prefix every `./y.sh` (or `y` if you built `build_system/main.rs` as `y`) command by `rustup run stage2` to make cg_clif use your local changes in rustc.
-
+4. Copy cargo from a nightly toolchain: `cp $(rustup +nightly which cargo) ./build/host/stage2/bin/cargo`. Note that you would need to do this every time you rebuilt `rust` repository.
+5. Link your new `rustc` to toolchain: `rustup toolchain link stage2 ./build/host/stage2/`.
+6. (Windows only) compile the build system: `rustc +stage2 -O build_system/main.rs -o y.exe`.
+7. You need to prefix every `./y.sh` (or `y` if you built `build_system/main.rs` as `y`) command by `rustup run stage2` to make cg_clif use your local changes in rustc.
* `rustup run stage2 ./y.sh prepare`
* `rustup run stage2 ./y.sh build`
* (Optional) run tests: `rustup run stage2 ./y.sh test`
-9. Now you can use your cg_clif build to compile other Rust programs, e.g. you can open any Rust crate and run commands like `$RustCheckoutDir/compiler/rustc_codegen_cranelift/dist/cargo-clif build --release`.
+8. Now you can use your cg_clif build to compile other Rust programs, e.g. you can open any Rust crate and run commands like `$RustCheckoutDir/compiler/rustc_codegen_cranelift/dist/cargo-clif build --release`.
## Configuration
@@ -80,9 +76,7 @@ configuration options.
## Not yet supported
-* Inline assembly ([no cranelift support](https://github.com/bytecodealliance/wasmtime/issues/1041))
- * On UNIX there is support for invoking an external assembler for `global_asm!` and `asm!`.
-* SIMD ([tracked here](https://github.com/bjorn3/rustc_codegen_cranelift/issues/171), `std::simd` fully works, `std::arch` is partially supported)
+* SIMD ([tracked here](https://github.com/rust-lang/rustc_codegen_cranelift/issues/171), `std::simd` fully works, `std::arch` is partially supported)
* Unwinding on panics ([no cranelift support](https://github.com/bytecodealliance/wasmtime/issues/1677), `-Cpanic=abort` is enabled by default)
## License
diff --git a/compiler/rustc_codegen_cranelift/build_system/build_backend.rs b/compiler/rustc_codegen_cranelift/build_system/build_backend.rs
index e434c36f9..d90111adf 100644
--- a/compiler/rustc_codegen_cranelift/build_system/build_backend.rs
+++ b/compiler/rustc_codegen_cranelift/build_system/build_backend.rs
@@ -20,6 +20,8 @@ pub(crate) fn build_backend(
let mut rustflags = rustflags_from_env("RUSTFLAGS");
+ rustflags.push("-Zallow-features=rustc_private".to_owned());
+
if is_ci() {
// Deny warnings on CI
rustflags.push("-Dwarnings".to_owned());
diff --git a/compiler/rustc_codegen_cranelift/build_system/build_sysroot.rs b/compiler/rustc_codegen_cranelift/build_system/build_sysroot.rs
index 31a4b2098..1ed896c6b 100644
--- a/compiler/rustc_codegen_cranelift/build_system/build_sysroot.rs
+++ b/compiler/rustc_codegen_cranelift/build_system/build_sysroot.rs
@@ -1,3 +1,4 @@
+use std::env;
use std::fs;
use std::path::{Path, PathBuf};
use std::process::Command;
@@ -259,6 +260,14 @@ fn build_clif_sysroot_for_triple(
// inlining.
rustflags.push("-Zinline-mir".to_owned());
}
+ if let Some(prefix) = env::var_os("CG_CLIF_STDLIB_REMAP_PATH_PREFIX") {
+ rustflags.push("--remap-path-prefix".to_owned());
+ rustflags.push(format!(
+ "{}={}",
+ STDLIB_SRC.to_path(dirs).to_str().unwrap(),
+ prefix.to_str().unwrap()
+ ));
+ }
compiler.rustflags.extend(rustflags);
let mut build_cmd = STANDARD_LIBRARY.build(&compiler, dirs);
maybe_incremental(&mut build_cmd);
diff --git a/compiler/rustc_codegen_cranelift/build_system/main.rs b/compiler/rustc_codegen_cranelift/build_system/main.rs
index 798ae9dbd..e8cf486e9 100644
--- a/compiler/rustc_codegen_cranelift/build_system/main.rs
+++ b/compiler/rustc_codegen_cranelift/build_system/main.rs
@@ -55,7 +55,7 @@ enum CodegenBackend {
}
fn main() {
- if env::var("RUST_BACKTRACE").is_err() {
+ if env::var_os("RUST_BACKTRACE").is_none() {
env::set_var("RUST_BACKTRACE", "1");
}
env::set_var("CG_CLIF_DISABLE_INCR_CACHE", "1");
diff --git a/compiler/rustc_codegen_cranelift/build_system/prepare.rs b/compiler/rustc_codegen_cranelift/build_system/prepare.rs
index 165296cb4..c68968b4f 100644
--- a/compiler/rustc_codegen_cranelift/build_system/prepare.rs
+++ b/compiler/rustc_codegen_cranelift/build_system/prepare.rs
@@ -122,10 +122,10 @@ impl GitRepo {
if download_dir.exists() {
let actual_hash = format!("{:016x}", hash_dir(&download_dir));
if actual_hash == self.content_hash {
- println!("[FRESH] {}", download_dir.display());
+ eprintln!("[FRESH] {}", download_dir.display());
return;
} else {
- println!(
+ eprintln!(
"Mismatched content hash for {download_dir}: {actual_hash} != {content_hash}. Downloading again.",
download_dir = download_dir.display(),
content_hash = self.content_hash,
@@ -143,6 +143,7 @@ impl GitRepo {
RelPath::PATCHES.to_path(dirs).join(format!("{}-lock.toml", self.patch_name));
let target_lockfile = download_dir.join("Cargo.lock");
if source_lockfile.exists() {
+ assert!(!target_lockfile.exists());
fs::copy(source_lockfile, target_lockfile).unwrap();
} else {
assert!(target_lockfile.exists());
@@ -150,7 +151,7 @@ impl GitRepo {
let actual_hash = format!("{:016x}", hash_dir(&download_dir));
if actual_hash != self.content_hash {
- println!(
+ eprintln!(
"Download of {download_dir} failed with mismatched content hash: {actual_hash} != {content_hash}",
download_dir = download_dir.display(),
content_hash = self.content_hash,
diff --git a/compiler/rustc_codegen_cranelift/build_system/tests.rs b/compiler/rustc_codegen_cranelift/build_system/tests.rs
index e7bd8b127..10736ff9a 100644
--- a/compiler/rustc_codegen_cranelift/build_system/tests.rs
+++ b/compiler/rustc_codegen_cranelift/build_system/tests.rs
@@ -9,7 +9,7 @@ use crate::path::{Dirs, RelPath};
use crate::prepare::{apply_patches, GitRepo};
use crate::rustc_info::get_default_sysroot;
use crate::shared_utils::rustflags_from_env;
-use crate::utils::{spawn_and_wait, spawn_and_wait_with_input, CargoProject, Compiler, LogGroup};
+use crate::utils::{spawn_and_wait, CargoProject, Compiler, LogGroup};
use crate::{CodegenBackend, SysrootKind};
static BUILD_EXAMPLE_OUT_DIR: RelPath = RelPath::BUILD.join("example");
@@ -99,15 +99,14 @@ const BASE_SYSROOT_SUITE: &[TestCase] = &[
TestCase::build_bin_and_run("aot.mod_bench", "example/mod_bench.rs", &[]),
TestCase::build_bin_and_run("aot.issue-72793", "example/issue-72793.rs", &[]),
TestCase::build_bin("aot.issue-59326", "example/issue-59326.rs"),
+ TestCase::build_bin_and_run("aot.neon", "example/neon.rs", &[]),
];
-// FIXME(rust-random/rand#1293): Newer rand versions fail to test on Windows. Update once this is
-// fixed.
pub(crate) static RAND_REPO: GitRepo = GitRepo::github(
"rust-random",
"rand",
- "50b9a447410860af8d6db9a208c3576886955874",
- "446203b96054891e",
+ "9a02c819cc1e4ec6959ae25eafbb5cf6acb68234",
+ "4934f0afb1d1c2ca",
"rand",
);
@@ -116,8 +115,8 @@ pub(crate) static RAND: CargoProject = CargoProject::new(&RAND_REPO.source_dir()
pub(crate) static REGEX_REPO: GitRepo = GitRepo::github(
"rust-lang",
"regex",
- "32fed9429eafba0ae92a64b01796a0c5a75b88c8",
- "fcc4df7c5b902633",
+ "061ee815ef2c44101dba7b0b124600fcb03c1912",
+ "dc26aefbeeac03ca",
"regex",
);
@@ -126,8 +125,8 @@ pub(crate) static REGEX: CargoProject = CargoProject::new(&REGEX_REPO.source_dir
pub(crate) static PORTABLE_SIMD_REPO: GitRepo = GitRepo::github(
"rust-lang",
"portable-simd",
- "7c7dbe0c505ccbc02ff30c1e37381ab1d47bf46f",
- "5bcc9c544f6fa7bd",
+ "4825b2a64d765317066948867e8714674419359b",
+ "9e67d07c00f5fb0b",
"portable-simd",
);
@@ -180,40 +179,6 @@ const EXTENDED_SYSROOT_SUITE: &[TestCase] = &[
spawn_and_wait(build_cmd);
}
}),
- TestCase::custom("test.regex-shootout-regex-dna", &|runner| {
- REGEX_REPO.patch(&runner.dirs);
-
- REGEX.clean(&runner.dirs);
-
- let mut build_cmd = REGEX.build(&runner.target_compiler, &runner.dirs);
- build_cmd.arg("--example").arg("shootout-regex-dna");
- spawn_and_wait(build_cmd);
-
- if runner.is_native {
- let mut run_cmd = REGEX.run(&runner.target_compiler, &runner.dirs);
- run_cmd.arg("--example").arg("shootout-regex-dna");
-
- let input = fs::read_to_string(
- REGEX.source_dir(&runner.dirs).join("examples").join("regexdna-input.txt"),
- )
- .unwrap();
- let expected = fs::read_to_string(
- REGEX.source_dir(&runner.dirs).join("examples").join("regexdna-output.txt"),
- )
- .unwrap();
-
- let output = spawn_and_wait_with_input(run_cmd, input);
-
- let output_matches = expected.lines().eq(output.lines());
- if !output_matches {
- println!("Output files don't match!");
- println!("Expected Output:\n{}", expected);
- println!("Actual Output:\n{}", output);
-
- std::process::exit(1);
- }
- }
- }),
TestCase::custom("test.regex", &|runner| {
REGEX_REPO.patch(&runner.dirs);
@@ -223,7 +188,22 @@ const EXTENDED_SYSROOT_SUITE: &[TestCase] = &[
let mut run_cmd = REGEX.test(&runner.target_compiler, &runner.dirs);
// regex-capi and regex-debug don't have any tests. Nor do they contain any code
// that is useful to test with cg_clif. Skip building them to reduce test time.
- run_cmd.args(["-p", "regex", "-p", "regex-syntax", "--", "-q"]);
+ run_cmd.args([
+ "-p",
+ "regex",
+ "-p",
+ "regex-syntax",
+ "--release",
+ "--all-targets",
+ "--",
+ "-q",
+ ]);
+ spawn_and_wait(run_cmd);
+
+ let mut run_cmd = REGEX.test(&runner.target_compiler, &runner.dirs);
+ // don't run integration tests for regex-autonata. they take like 2min each without
+ // much extra coverage of simd usage.
+ run_cmd.args(["-p", "regex-automata", "--release", "--lib", "--", "-q"]);
spawn_and_wait(run_cmd);
} else {
eprintln!("Cross-Compiling: Not running tests");
diff --git a/compiler/rustc_codegen_cranelift/build_system/utils.rs b/compiler/rustc_codegen_cranelift/build_system/utils.rs
index 24624cdea..149f1618f 100644
--- a/compiler/rustc_codegen_cranelift/build_system/utils.rs
+++ b/compiler/rustc_codegen_cranelift/build_system/utils.rs
@@ -1,8 +1,8 @@
use std::env;
use std::fs;
-use std::io::{self, Write};
+use std::io;
use std::path::{Path, PathBuf};
-use std::process::{self, Command, Stdio};
+use std::process::{self, Command};
use std::sync::atomic::{AtomicBool, Ordering};
use crate::path::{Dirs, RelPath};
@@ -42,12 +42,22 @@ impl Compiler {
"/usr/s390x-linux-gnu".to_owned(),
];
}
+ "riscv64gc-unknown-linux-gnu" => {
+ // We are cross-compiling for riscv64. Use the correct linker and run tests in qemu.
+ self.rustflags.push("-Clinker=riscv64-linux-gnu-gcc".to_owned());
+ self.rustdocflags.push("-Clinker=riscv64-linux-gnu-gcc".to_owned());
+ self.runner = vec![
+ "qemu-riscv64".to_owned(),
+ "-L".to_owned(),
+ "/usr/riscv64-linux-gnu".to_owned(),
+ ];
+ }
"x86_64-pc-windows-gnu" => {
// We are cross-compiling for Windows. Run tests in wine.
self.runner = vec!["wine".to_owned()];
}
_ => {
- println!("Unknown non-native platform");
+ eprintln!("Unknown non-native platform");
}
}
}
@@ -197,7 +207,9 @@ pub(crate) fn try_hard_link(src: impl AsRef<Path>, dst: impl AsRef<Path>) {
#[track_caller]
pub(crate) fn spawn_and_wait(mut cmd: Command) {
- if !cmd.spawn().unwrap().wait().unwrap().success() {
+ let status = cmd.spawn().unwrap().wait().unwrap();
+ if !status.success() {
+ eprintln!("{cmd:?} exited with status {:?}", status);
process::exit(1);
}
}
@@ -207,38 +219,17 @@ pub(crate) fn spawn_and_wait(mut cmd: Command) {
pub(crate) fn retry_spawn_and_wait(tries: u64, mut cmd: Command) {
for i in 1..tries + 1 {
if i != 1 {
- println!("Command failed. Attempt {i}/{tries}:");
+ eprintln!("Command failed. Attempt {i}/{tries}:");
}
if cmd.spawn().unwrap().wait().unwrap().success() {
return;
}
std::thread::sleep(std::time::Duration::from_secs(i * 5));
}
- println!("The command has failed after {tries} attempts.");
+ eprintln!("The command has failed after {tries} attempts.");
process::exit(1);
}
-#[track_caller]
-pub(crate) fn spawn_and_wait_with_input(mut cmd: Command, input: String) -> String {
- let mut child = cmd
- .stdin(Stdio::piped())
- .stdout(Stdio::piped())
- .spawn()
- .expect("Failed to spawn child process");
-
- let mut stdin = child.stdin.take().expect("Failed to open stdin");
- std::thread::spawn(move || {
- stdin.write_all(input.as_bytes()).expect("Failed to write to stdin");
- });
-
- let output = child.wait_with_output().expect("Failed to read stdout");
- if !output.status.success() {
- process::exit(1);
- }
-
- String::from_utf8(output.stdout).unwrap()
-}
-
pub(crate) fn remove_dir_if_exists(path: &Path) {
match fs::remove_dir_all(&path) {
Ok(()) => {}
diff --git a/compiler/rustc_codegen_cranelift/config.txt b/compiler/rustc_codegen_cranelift/config.txt
index fa1c9f425..2ccdc7d78 100644
--- a/compiler/rustc_codegen_cranelift/config.txt
+++ b/compiler/rustc_codegen_cranelift/config.txt
@@ -42,10 +42,10 @@ aot.float-minmax-pass
aot.mod_bench
aot.issue-72793
aot.issue-59326
+aot.neon
testsuite.extended_sysroot
test.rust-random/rand
test.libcore
-test.regex-shootout-regex-dna
test.regex
test.portable-simd
diff --git a/compiler/rustc_codegen_cranelift/example/mini_core.rs b/compiler/rustc_codegen_cranelift/example/mini_core.rs
index 34c7e44b2..934e4b178 100644
--- a/compiler/rustc_codegen_cranelift/example/mini_core.rs
+++ b/compiler/rustc_codegen_cranelift/example/mini_core.rs
@@ -685,6 +685,12 @@ pub macro cfg() {
#[rustc_builtin_macro]
#[rustc_macro_transparency = "semitransparent"]
+pub macro asm() {
+ /* compiler built-in */
+}
+
+#[rustc_builtin_macro]
+#[rustc_macro_transparency = "semitransparent"]
pub macro global_asm() {
/* compiler built-in */
}
diff --git a/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs b/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs
index 91de04d97..afc51a47f 100644
--- a/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs
+++ b/compiler/rustc_codegen_cranelift/example/mini_core_hello_world.rs
@@ -353,6 +353,17 @@ fn main() {
let f = V([0.0, 1.0]);
let _a = f.0[0];
+
+ stack_val_align();
+}
+
+#[inline(never)]
+fn stack_val_align() {
+ #[repr(align(8192))]
+ struct Foo(u8);
+
+ let a = Foo(0);
+ assert_eq!(&a as *const Foo as usize % 8192, 0);
}
#[cfg(all(
diff --git a/compiler/rustc_codegen_cranelift/example/neon.rs b/compiler/rustc_codegen_cranelift/example/neon.rs
new file mode 100644
index 000000000..bad269479
--- /dev/null
+++ b/compiler/rustc_codegen_cranelift/example/neon.rs
@@ -0,0 +1,234 @@
+// Most of these tests are copied from https://github.com/japaric/stdsimd/blob/0f4413d01c4f0c3ffbc5a69e9a37fbc7235b31a9/coresimd/arm/neon.rs
+
+#![feature(portable_simd)]
+
+#[cfg(target_arch = "aarch64")]
+use std::arch::aarch64::*;
+use std::mem::transmute;
+use std::simd::*;
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_s8() {
+ let a = i8x8::from([1, -2, 3, -4, 5, 6, 7, 8]);
+ let b = i8x8::from([0, 3, 2, 5, 4, 7, 6, 9]);
+ let e = i8x8::from([-2, -4, 5, 7, 0, 2, 4, 6]);
+ let r: i8x8 = transmute(vpmin_s8(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_s16() {
+ let a = i16x4::from([1, 2, 3, -4]);
+ let b = i16x4::from([0, 3, 2, 5]);
+ let e = i16x4::from([1, -4, 0, 2]);
+ let r: i16x4 = transmute(vpmin_s16(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_s32() {
+ let a = i32x2::from([1, -2]);
+ let b = i32x2::from([0, 3]);
+ let e = i32x2::from([-2, 0]);
+ let r: i32x2 = transmute(vpmin_s32(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_u8() {
+ let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 8]);
+ let b = u8x8::from([0, 3, 2, 5, 4, 7, 6, 9]);
+ let e = u8x8::from([1, 3, 5, 7, 0, 2, 4, 6]);
+ let r: u8x8 = transmute(vpmin_u8(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_u16() {
+ let a = u16x4::from([1, 2, 3, 4]);
+ let b = u16x4::from([0, 3, 2, 5]);
+ let e = u16x4::from([1, 3, 0, 2]);
+ let r: u16x4 = transmute(vpmin_u16(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_u32() {
+ let a = u32x2::from([1, 2]);
+ let b = u32x2::from([0, 3]);
+ let e = u32x2::from([1, 0]);
+ let r: u32x2 = transmute(vpmin_u32(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmin_f32() {
+ let a = f32x2::from([1., -2.]);
+ let b = f32x2::from([0., 3.]);
+ let e = f32x2::from([-2., 0.]);
+ let r: f32x2 = transmute(vpmin_f32(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_s8() {
+ let a = i8x8::from([1, -2, 3, -4, 5, 6, 7, 8]);
+ let b = i8x8::from([0, 3, 2, 5, 4, 7, 6, 9]);
+ let e = i8x8::from([1, 3, 6, 8, 3, 5, 7, 9]);
+ let r: i8x8 = transmute(vpmax_s8(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_s16() {
+ let a = i16x4::from([1, 2, 3, -4]);
+ let b = i16x4::from([0, 3, 2, 5]);
+ let e = i16x4::from([2, 3, 3, 5]);
+ let r: i16x4 = transmute(vpmax_s16(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_s32() {
+ let a = i32x2::from([1, -2]);
+ let b = i32x2::from([0, 3]);
+ let e = i32x2::from([1, 3]);
+ let r: i32x2 = transmute(vpmax_s32(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_u8() {
+ let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 8]);
+ let b = u8x8::from([0, 3, 2, 5, 4, 7, 6, 9]);
+ let e = u8x8::from([2, 4, 6, 8, 3, 5, 7, 9]);
+ let r: u8x8 = transmute(vpmax_u8(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_u16() {
+ let a = u16x4::from([1, 2, 3, 4]);
+ let b = u16x4::from([0, 3, 2, 5]);
+ let e = u16x4::from([2, 4, 3, 5]);
+ let r: u16x4 = transmute(vpmax_u16(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_u32() {
+ let a = u32x2::from([1, 2]);
+ let b = u32x2::from([0, 3]);
+ let e = u32x2::from([2, 3]);
+ let r: u32x2 = transmute(vpmax_u32(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpmax_f32() {
+ let a = f32x2::from([1., -2.]);
+ let b = f32x2::from([0., 3.]);
+ let e = f32x2::from([1., 3.]);
+ let r: f32x2 = transmute(vpmax_f32(transmute(a), transmute(b)));
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpadd_s16() {
+ let a = i16x4::from([1, 2, 3, 4]);
+ let b = i16x4::from([0, -1, -2, -3]);
+ let r: i16x4 = transmute(vpadd_s16(transmute(a), transmute(b)));
+ let e = i16x4::from([3, 7, -1, -5]);
+ assert_eq!(r, e);
+}
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpadd_s32() {
+ let a = i32x2::from([1, 2]);
+ let b = i32x2::from([0, -1]);
+ let r: i32x2 = transmute(vpadd_s32(transmute(a), transmute(b)));
+ let e = i32x2::from([3, -1]);
+ assert_eq!(r, e);
+}
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpadd_s8() {
+ let a = i8x8::from([1, 2, 3, 4, 5, 6, 7, 8]);
+ let b = i8x8::from([0, -1, -2, -3, -4, -5, -6, -7]);
+ let r: i8x8 = transmute(vpadd_s8(transmute(a), transmute(b)));
+ let e = i8x8::from([3, 7, 11, 15, -1, -5, -9, -13]);
+ assert_eq!(r, e);
+}
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpadd_u16() {
+ let a = u16x4::from([1, 2, 3, 4]);
+ let b = u16x4::from([30, 31, 32, 33]);
+ let r: u16x4 = transmute(vpadd_u16(transmute(a), transmute(b)));
+ let e = u16x4::from([3, 7, 61, 65]);
+ assert_eq!(r, e);
+}
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpadd_u32() {
+ let a = u32x2::from([1, 2]);
+ let b = u32x2::from([30, 31]);
+ let r: u32x2 = transmute(vpadd_u32(transmute(a), transmute(b)));
+ let e = u32x2::from([3, 61]);
+ assert_eq!(r, e);
+}
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vpadd_u8() {
+ let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 8]);
+ let b = u8x8::from([30, 31, 32, 33, 34, 35, 36, 37]);
+ let r: u8x8 = transmute(vpadd_u8(transmute(a), transmute(b)));
+ let e = u8x8::from([3, 7, 11, 15, 61, 65, 69, 73]);
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vqsub_u8() {
+ let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 0xff]);
+ let b = u8x8::from([30, 1, 1, 1, 34, 0xff, 36, 37]);
+ let r: u8x8 = transmute(vqsub_u8(transmute(a), transmute(b)));
+ let e = u8x8::from([0, 1, 2, 3, 0, 0, 0, 218]);
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+unsafe fn test_vqadd_u8() {
+ let a = u8x8::from([1, 2, 3, 4, 5, 6, 7, 0xff]);
+ let b = u8x8::from([30, 1, 1, 1, 34, 0xff, 36, 37]);
+ let r: u8x8 = transmute(vqadd_u8(transmute(a), transmute(b)));
+ let e = u8x8::from([31, 3, 4, 5, 39, 0xff, 43, 0xff]);
+ assert_eq!(r, e);
+}
+
+#[cfg(target_arch = "aarch64")]
+fn main() {
+ unsafe {
+ test_vpmin_s8();
+ test_vpmin_s16();
+ test_vpmin_s32();
+ test_vpmin_u8();
+ test_vpmin_u16();
+ test_vpmin_u32();
+ test_vpmin_f32();
+ test_vpmax_s8();
+ test_vpmax_s16();
+ test_vpmax_s32();
+ test_vpmax_u8();
+ test_vpmax_u16();
+ test_vpmax_u32();
+ test_vpmax_f32();
+
+ test_vpadd_s16();
+ test_vpadd_s32();
+ test_vpadd_s8();
+ test_vpadd_u16();
+ test_vpadd_u32();
+ test_vpadd_u8();
+
+ test_vqsub_u8();
+ test_vqadd_u8();
+ }
+}
+
+#[cfg(not(target_arch = "aarch64"))]
+fn main() {}
diff --git a/compiler/rustc_codegen_cranelift/example/std_example.rs b/compiler/rustc_codegen_cranelift/example/std_example.rs
index 490cc2404..9bd2ab5c6 100644
--- a/compiler/rustc_codegen_cranelift/example/std_example.rs
+++ b/compiler/rustc_codegen_cranelift/example/std_example.rs
@@ -1,7 +1,7 @@
#![feature(
core_intrinsics,
- generators,
- generator_trait,
+ coroutines,
+ coroutine_trait,
is_sorted,
repr_simd,
tuple_trait,
@@ -12,7 +12,7 @@
use std::arch::x86_64::*;
use std::hint::black_box;
use std::io::Write;
-use std::ops::Generator;
+use std::ops::Coroutine;
fn main() {
println!("{:?}", std::env::args().collect::<Vec<_>>());
diff --git a/compiler/rustc_codegen_cranelift/patches/0001-portable-simd-Allow-internal-features.patch b/compiler/rustc_codegen_cranelift/patches/0001-portable-simd-Allow-internal-features.patch
deleted file mode 100644
index 87252df1e..000000000
--- a/compiler/rustc_codegen_cranelift/patches/0001-portable-simd-Allow-internal-features.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From fcf75306d88e533b83eaff3f8d0ab9f307e8a84d Mon Sep 17 00:00:00 2001
-From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
-Date: Wed, 9 Aug 2023 10:01:17 +0000
-Subject: [PATCH] Allow internal features
-
----
- crates/core_simd/src/lib.rs | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/crates/core_simd/src/lib.rs b/crates/core_simd/src/lib.rs
-index fde406b..b386116 100644
---- a/crates/core_simd/src/lib.rs
-+++ b/crates/core_simd/src/lib.rs
-@@ -19,6 +19,7 @@
- #![warn(missing_docs, clippy::missing_inline_in_public_items)] // basically all items, really
- #![deny(unsafe_op_in_unsafe_fn, clippy::undocumented_unsafe_blocks)]
- #![unstable(feature = "portable_simd", issue = "86656")]
-+#![allow(internal_features)]
- //! Portable SIMD module.
-
- #[path = "mod.rs"]
---
-2.34.1
-
diff --git a/compiler/rustc_codegen_cranelift/patches/0002-rand-Disable-failing-test.patch b/compiler/rustc_codegen_cranelift/patches/0002-rand-Disable-failing-test.patch
deleted file mode 100644
index ae13ab3b0..000000000
--- a/compiler/rustc_codegen_cranelift/patches/0002-rand-Disable-failing-test.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From a8fb97120d71252538b6b026695df40d02696bdb Mon Sep 17 00:00:00 2001
-From: bjorn3 <bjorn3@users.noreply.github.com>
-Date: Sat, 15 Aug 2020 20:04:38 +0200
-Subject: [PATCH] [rand] Disable failing test
-
----
- src/distributions/uniform.rs | 1 +
- 1 file changed, 1 insertion(+), 0 deletions(-)
-
-diff --git a/src/distributions/uniform.rs b/src/distributions/uniform.rs
-index 480b859..c80bb6f 100644
---- a/src/distributions/uniform.rs
-+++ b/src/distributions/uniform.rs
-@@ -1314,6 +1314,7 @@ mod tests {
- not(target_arch = "wasm32"),
- not(target_arch = "asmjs")
- ))]
-+ #[ignore] // Requires unwinding
- fn test_float_assertions() {
- use super::SampleUniform;
- use std::panic::catch_unwind;
---
-2.20.1
-
diff --git a/compiler/rustc_codegen_cranelift/patches/0003-rand-Disable-rand-tests-on-mingw.patch b/compiler/rustc_codegen_cranelift/patches/0003-rand-Disable-rand-tests-on-mingw.patch
deleted file mode 100644
index eb452c5cd..000000000
--- a/compiler/rustc_codegen_cranelift/patches/0003-rand-Disable-rand-tests-on-mingw.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From eec874c889b8d24e5ad50faded24288150f057b1 Mon Sep 17 00:00:00 2001
-From: Afonso Bordado <afonsobordado@az8.co>
-Date: Tue, 27 Sep 2022 08:13:58 +0100
-Subject: [PATCH] Disable rand tests on mingw
-
----
- rand_distr/src/pareto.rs | 2 ++
- rand_distr/tests/value_stability.rs | 4 ++++
- 2 files changed, 6 insertions(+)
-
-diff --git a/rand_distr/src/pareto.rs b/rand_distr/src/pareto.rs
-index 217899e..9cedeb7 100644
---- a/rand_distr/src/pareto.rs
-+++ b/rand_distr/src/pareto.rs
-@@ -107,6 +107,8 @@ mod tests {
- }
-
- #[test]
-+ // This is broken on x86_64-pc-windows-gnu presumably due to a broken powf implementation
-+ #[cfg_attr(all(target_os = "windows", target_env = "gnu"), ignore)]
- fn value_stability() {
- fn test_samples<F: Float + Debug + Display + LowerExp, D: Distribution<F>>(
- distr: D, thresh: F, expected: &[F],
-diff --git a/rand_distr/tests/value_stability.rs b/rand_distr/tests/value_stability.rs
-index 192ba74..0101ace 100644
---- a/rand_distr/tests/value_stability.rs
-+++ b/rand_distr/tests/value_stability.rs
-@@ -72,6 +72,8 @@ fn unit_disc_stability() {
- }
-
- #[test]
-+// This is broken on x86_64-pc-windows-gnu
-+#[cfg_attr(all(target_os = "windows", target_env = "gnu"), ignore)]
- fn pareto_stability() {
- test_samples(213, Pareto::new(1.0, 1.0).unwrap(), &[
- 1.0423688f32, 2.1235929, 4.132709, 1.4679428,
-@@ -143,6 +145,8 @@ fn inverse_gaussian_stability() {
- }
-
- #[test]
-+// This is broken on x86_64-pc-windows-gnu
-+#[cfg_attr(all(target_os = "windows", target_env = "gnu"), ignore)]
- fn gamma_stability() {
- // Gamma has 3 cases: shape == 1, shape < 1, shape > 1
- test_samples(223, Gamma::new(1.0, 5.0).unwrap(), &[
---
-2.25.1
diff --git a/compiler/rustc_codegen_cranelift/patches/0027-coretests-128bit-atomic-operations.patch b/compiler/rustc_codegen_cranelift/patches/0027-coretests-128bit-atomic-operations.patch
index a650e1011..be29ae09b 100644
--- a/compiler/rustc_codegen_cranelift/patches/0027-coretests-128bit-atomic-operations.patch
+++ b/compiler/rustc_codegen_cranelift/patches/0027-coretests-128bit-atomic-operations.patch
@@ -19,9 +19,9 @@ index 897a5e9..331f66f 100644
#![feature(const_option_ext)]
#![feature(const_result)]
-#![cfg_attr(target_has_atomic = "128", feature(integer_atomics))]
+ #![cfg_attr(test, feature(cfg_match))]
#![feature(int_roundings)]
#![feature(slice_group_by)]
- #![feature(split_array)]
diff --git a/atomic.rs b/atomic.rs
index b735957..ea728b6 100644
--- a/atomic.rs
diff --git a/compiler/rustc_codegen_cranelift/patches/portable-simd-lock.toml b/compiler/rustc_codegen_cranelift/patches/portable-simd-lock.toml
deleted file mode 100644
index e7db1fd2c..000000000
--- a/compiler/rustc_codegen_cranelift/patches/portable-simd-lock.toml
+++ /dev/null
@@ -1,304 +0,0 @@
-# This file is automatically @generated by Cargo.
-# It is not intended for manual editing.
-version = 3
-
-[[package]]
-name = "autocfg"
-version = "1.1.0"
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-
-[[package]]
-name = "bitflags"
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-source = "registry+https://github.com/rust-lang/crates.io-index"
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-
-[[package]]
-name = "bumpalo"
-version = "3.13.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
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-
-[[package]]
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-version = "1.4.3"
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-checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
-
-[[package]]
-name = "cfg-if"
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diff --git a/compiler/rustc_codegen_cranelift/patches/rand-lock.toml b/compiler/rustc_codegen_cranelift/patches/rand-lock.toml
index 66c515731..aacf3653c 100644
--- a/compiler/rustc_codegen_cranelift/patches/rand-lock.toml
+++ b/compiler/rustc_codegen_cranelift/patches/rand-lock.toml
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[[package]]
name = "libc"
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+checksum = "9cdc71e17332e86d2e1d38c1f99edcb6288ee11b815fb1a4b049eaa2114d369b"
[[package]]
name = "libm"
@@ -138,24 +365,30 @@ checksum = "f7012b1bbb0719e1097c47611d3898568c546d597c2e74d66f6087edd5233ff4"
[[package]]
name = "log"
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+
+[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "8f232d6ef707e1956a43342693d2a31e72989554d58299d7a88738cc95b0d35c"
[[package]]
name = "memoffset"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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]
[[package]]
name = "num-traits"
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+checksum = "f30b0abd723be7e2ffca1272140fac1a2f084c77ec3e123c192b66af1ee9e6c2"
dependencies = [
"autocfg",
"libm",
@@ -163,15 +396,61 @@ dependencies = [
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name = "num_cpus"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "4161fcb6d602d4d2081af7c3a45852d875a03dd337a6bfdd6e06407b61342a43"
dependencies = [
- "hermit-abi",
+ "hermit-abi 0.3.2",
"libc",
]
[[package]]
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+
+[[package]]
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+
+[[package]]
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+
+[[package]]
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+dependencies = [
+ "num-traits",
+ "plotters-backend",
+ "plotters-svg",
+ "wasm-bindgen",
+ "web-sys",
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+
+[[package]]
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+checksum = "9e76628b4d3a7581389a35d5b6e2139607ad7c75b17aed325f210aa91f4a9609"
+
+[[package]]
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+checksum = "38f6d39893cca0701371e3c27294f09797214b86f1fb951b89ade8ec04e2abab"
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+ "plotters-backend",
+]
+
+[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
@@ -179,18 +458,18 @@ checksum = "5b40af805b3121feab8a3c29f04d8ad262fa8e0561883e7653e024ae4479e6de"
[[package]]
name = "proc-macro2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "3d433d9f1a3e8c1263d9456598b16fec66f4acc9a74dacffd35c7bb09b3a1328"
dependencies = [
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]
[[package]]
name = "quote"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "5267fca4496028628a95160fc423a33e8b2e6af8a5302579e322e4b520293cae"
dependencies = [
"proc-macro2",
]
@@ -200,6 +479,7 @@ name = "rand"
version = "0.9.0"
dependencies = [
"bincode",
+ "criterion",
"libc",
"log",
"rand_chacha",
@@ -236,6 +516,7 @@ dependencies = [
"rand",
"rand_pcg",
"serde",
+ "serde_with",
"special",
]
@@ -271,42 +552,80 @@ dependencies = [
]
[[package]]
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+dependencies = [
+ "aho-corasick",
+ "memchr",
+ "regex-automata",
+ "regex-syntax",
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+
+[[package]]
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+checksum = "c2f401f4955220693b56f8ec66ee9c78abffd8d1c4f23dc41a23839eb88f0795"
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+ "aho-corasick",
+ "memchr",
+ "regex-syntax",
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+
+[[package]]
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+
+[[package]]
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+
+[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "93fc1dc3aaa9bfed95e02e6eadabb4baf7e3078b0bd1b4d7b6b0b68378900502"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
name = "serde"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "cf9e0fcba69a370eed61bcf2b728575f726b50b55cba78064753d708ddc7549e"
dependencies = [
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]
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name = "serde_derive"
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dependencies = [
"proc-macro2",
"quote",
- "syn",
+ "syn 2.0.37",
]
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name = "serde_json"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"ryu",
@@ -314,6 +633,28 @@ dependencies = [
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[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "678b5a069e50bf00ecd22d0cd8ddf7c236f68581b03db652061ed5eb13a312ff"
+dependencies = [
+ "serde",
+ "serde_with_macros",
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+[[package]]
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+ "proc-macro2",
+ "quote",
+ "syn 1.0.109",
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+
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version = "0.8.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
@@ -323,10 +664,27 @@ dependencies = [
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[[package]]
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+
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+ "quote",
+ "unicode-ident",
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+[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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"quote",
@@ -334,13 +692,134 @@ dependencies = [
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[[package]]
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+
+[[package]]
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+ "serde_json",
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "3354b9ac3fae1ff6755cb6db53683adb661634f67557942dea4facebec0fee4b"
+
+[[package]]
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+ "winapi-util",
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name = "wasi"
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source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "9c8d87e72b64a3b4db28d11ce29237c246188f4f51057d65a7eab63b7987e423"
+
+[[package]]
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+checksum = "7706a72ab36d8cb1f80ffbf0e071533974a60d0a308d01a5d0375bf60499a342"
+dependencies = [
+ "cfg-if",
+ "wasm-bindgen-macro",
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+ "log",
+ "once_cell",
+ "proc-macro2",
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+[[package]]
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+dependencies = [
+ "winapi",
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diff --git a/compiler/rustc_codegen_cranelift/patches/regex-lock.toml b/compiler/rustc_codegen_cranelift/patches/regex-lock.toml
index 0e4a33b90..e0df6f9ae 100644
--- a/compiler/rustc_codegen_cranelift/patches/regex-lock.toml
+++ b/compiler/rustc_codegen_cranelift/patches/regex-lock.toml
@@ -4,51 +4,49 @@ version = 3
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "0f2135563fb5c609d2b2b87c1e8ce7bc41b0b45430fa9661f457981503dd5bf0"
dependencies = [
+ "log",
"memchr",
]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
- "bzip2-sys",
- "libc",
+ "derive_arbitrary",
]
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+checksum = "d9b39be18770d11421cdb1b9947a45dd3f37e93092cbf377614828a319d5fee8"
dependencies = [
- "cc",
+ "hermit-abi",
"libc",
- "pkg-config",
+ "winapi",
]
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-
-[[package]]
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source = "registry+https://github.com/rust-lang/crates.io-index"
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+checksum = "4c2f7349907b712260e64b0afe2f84692af14a454be26187d9df565c7f69266a"
+dependencies = [
+ "memchr",
+ "serde",
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[[package]]
name = "cfg-if"
@@ -57,114 +55,129 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
- "lazy_static",
- "regex 1.8.3",
- "serde",
- "strsim",
+ "proc-macro2",
+ "quote",
+ "syn",
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@@ -180,9 +193,9 @@ dependencies = [
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+ "memchr",
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diff --git a/compiler/rustc_codegen_cranelift/patches/stdlib-lock.toml b/compiler/rustc_codegen_cranelift/patches/stdlib-lock.toml
index 5b79d6569..8a690bada 100644
--- a/compiler/rustc_codegen_cranelift/patches/stdlib-lock.toml
+++ b/compiler/rustc_codegen_cranelift/patches/stdlib-lock.toml
@@ -41,22 +41,6 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
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@@ -74,9 +58,9 @@ dependencies = [
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source = "registry+https://github.com/rust-lang/crates.io-index"
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dependencies = [
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@@ -174,9 +158,9 @@ dependencies = [
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source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f92be4933c13fd498862a9e02a3055f8a8d9c039ce33db97306fd5a6caa7f29b"
+checksum = "89d92a4743f9a61002fae18374ed11e7973f530cb3a3255fb354818118b2203c"
dependencies = [
"rustc-std-workspace-core",
]
@@ -256,6 +240,27 @@ dependencies = [
]
[[package]]
+name = "r-efi"
+version = "4.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "575fc2d9b3da54adbdfaddf6eca48fec256d977c8630a1750b8991347d1ac911"
+dependencies = [
+ "compiler_builtins",
+ "rustc-std-workspace-core",
+]
+
+[[package]]
+name = "r-efi-alloc"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "31d6f09fe2b6ad044bc3d2c34ce4979796581afd2f1ebc185837e02421e02fd7"
+dependencies = [
+ "compiler_builtins",
+ "r-efi",
+ "rustc-std-workspace-core",
+]
+
+[[package]]
name = "rand"
version = "0.8.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
@@ -353,6 +358,8 @@ dependencies = [
"panic_abort",
"panic_unwind",
"profiler_builtins",
+ "r-efi",
+ "r-efi-alloc",
"rand",
"rand_xorshift",
"rustc-demangle",
@@ -365,7 +372,6 @@ dependencies = [
name = "std_detect"
version = "0.1.5"
dependencies = [
- "auxv",
"cfg-if",
"compiler_builtins",
"cupid",
@@ -409,7 +415,6 @@ dependencies = [
name = "unwind"
version = "0.0.0"
dependencies = [
- "cc",
"cfg-if",
"compiler_builtins",
"core",
diff --git a/compiler/rustc_codegen_cranelift/rust-toolchain b/compiler/rustc_codegen_cranelift/rust-toolchain
index 2cc5d7777..b832b06e0 100644
--- a/compiler/rustc_codegen_cranelift/rust-toolchain
+++ b/compiler/rustc_codegen_cranelift/rust-toolchain
@@ -1,3 +1,3 @@
[toolchain]
-channel = "nightly-2023-09-06"
+channel = "nightly-2023-11-10"
components = ["rust-src", "rustc-dev", "llvm-tools"]
diff --git a/compiler/rustc_codegen_cranelift/scripts/setup_rust_fork.sh b/compiler/rustc_codegen_cranelift/scripts/setup_rust_fork.sh
index e6bbac647..bbb8a010d 100644
--- a/compiler/rustc_codegen_cranelift/scripts/setup_rust_fork.sh
+++ b/compiler/rustc_codegen_cranelift/scripts/setup_rust_fork.sh
@@ -1,7 +1,12 @@
#!/usr/bin/env bash
set -e
-./y.sh build --no-unstable-features
+# Compiletest expects all standard library paths to start with /rustc/FAKE_PREFIX.
+# CG_CLIF_STDLIB_REMAP_PATH_PREFIX will cause cg_clif's build system to pass
+# --remap-path-prefix to handle this.
+# CG_CLIF_FORCE_GNU_AS will force usage of as instead of the LLVM backend of rustc as we
+# the LLVM backend isn't compiled in here.
+CG_CLIF_FORCE_GNU_AS=1 CG_CLIF_STDLIB_REMAP_PATH_PREFIX=/rustc/FAKE_PREFIX ./y.sh build
echo "[SETUP] Rust fork"
git clone https://github.com/rust-lang/rust.git || true
@@ -13,25 +18,8 @@ git checkout "$(rustc -V | cut -d' ' -f3 | tr -d '(')"
git -c user.name=Dummy -c user.email=dummy@example.com -c commit.gpgSign=false \
am ../patches/*-stdlib-*.patch
-git apply - <<EOF
-diff --git a/library/alloc/Cargo.toml b/library/alloc/Cargo.toml
-index d95b5b7f17f..00b6f0e3635 100644
---- a/library/alloc/Cargo.toml
-+++ b/library/alloc/Cargo.toml
-@@ -8,7 +8,7 @@ edition = "2018"
-
- [dependencies]
- core = { path = "../core" }
--compiler_builtins = { version = "0.1.40", features = ['rustc-dep-of-std'] }
-+compiler_builtins = { version = "0.1.66", features = ['rustc-dep-of-std', 'no-asm'] }
-
- [dev-dependencies]
- rand = { version = "0.8.5", default-features = false, features = ["alloc"] }
- rand_xorshift = "0.3.0"
-EOF
-
cat > config.toml <<EOF
-changelog-seen = 2
+change-id = 115898
[llvm]
ninja = false
@@ -49,11 +37,6 @@ verbose-tests = false
EOF
popd
-# FIXME remove once inline asm is fully supported
-export RUSTFLAGS="$RUSTFLAGS --cfg=rustix_use_libc"
-
-export CFG_VIRTUAL_RUST_SOURCE_BASE_DIR="$(cd build/stdlib; pwd)"
-
# Allow the testsuite to use llvm tools
host_triple=$(rustc -vV | grep host | cut -d: -f2 | tr -d " ")
export LLVM_BIN_DIR="$(rustc --print sysroot)/lib/rustlib/$host_triple/bin"
diff --git a/compiler/rustc_codegen_cranelift/scripts/test_bootstrap.sh b/compiler/rustc_codegen_cranelift/scripts/test_bootstrap.sh
index 791d45799..a8f6d7a20 100755
--- a/compiler/rustc_codegen_cranelift/scripts/test_bootstrap.sh
+++ b/compiler/rustc_codegen_cranelift/scripts/test_bootstrap.sh
@@ -11,5 +11,7 @@ rm -r compiler/rustc_codegen_cranelift/{Cargo.*,src}
cp ../Cargo.* compiler/rustc_codegen_cranelift/
cp -r ../src compiler/rustc_codegen_cranelift/src
-./x.py build --stage 1 library/std
+# CG_CLIF_FORCE_GNU_AS will force usage of as instead of the LLVM backend of rustc as we
+# the LLVM backend isn't compiled in here.
+CG_CLIF_FORCE_GNU_AS=1 ./x.py build --stage 1 library/std
popd
diff --git a/compiler/rustc_codegen_cranelift/scripts/test_rustc_tests.sh b/compiler/rustc_codegen_cranelift/scripts/test_rustc_tests.sh
index 3fc462a39..cdc78adcf 100755
--- a/compiler/rustc_codegen_cranelift/scripts/test_rustc_tests.sh
+++ b/compiler/rustc_codegen_cranelift/scripts/test_rustc_tests.sh
@@ -11,32 +11,26 @@ pushd rust
command -v rg >/dev/null 2>&1 || cargo install ripgrep
rm -r tests/ui/{unsized-locals/,lto/,linkage*} || true
-for test in $(rg --files-with-matches "lto|// needs-asm-support" tests/{codegen-units,ui,incremental}); do
+for test in $(rg --files-with-matches "lto" tests/{codegen-units,ui,incremental}); do
rm $test
done
-for test in tests/run-make/**/Makefile; do
- if rg "# needs-asm-support" $test >/dev/null; then
- rm -r $(dirname $test)
- fi
-done
-
for test in $(rg -i --files-with-matches "//(\[\w+\])?~[^\|]*\s*ERR|// error-pattern:|// build-fail|// run-fail|-Cllvm-args" tests/ui); do
rm $test
done
git checkout -- tests/ui/issues/auxiliary/issue-3136-a.rs # contains //~ERROR, but shouldn't be removed
git checkout -- tests/ui/proc-macro/pretty-print-hack/
+git checkout -- tests/ui/entry-point/auxiliary/bad_main_functions.rs
rm tests/ui/parser/unclosed-delimiter-in-dep.rs # submodule contains //~ERROR
# missing features
# ================
-rm -r tests/run-make/comment-section # cg_clif doesn't yet write the .comment section
-
# requires stack unwinding
-# FIXME add needs-unwind to this test
+# FIXME add needs-unwind to these tests
rm -r tests/run-make/libtest-junit
+rm tests/ui/asm/may_unwind.rs
# extra warning about -Cpanic=abort for proc macros
rm tests/ui/proc-macro/crt-static.rs
@@ -48,10 +42,8 @@ rm tests/ui/proc-macro/allowed-signatures.rs
rm tests/ui/proc-macro/no-mangle-in-proc-macro-issue-111888.rs
# vendor intrinsics
-rm tests/ui/sse2.rs # cpuid not supported, so sse2 not detected
+rm tests/ui/sse2.rs # CodegenBackend::target_features not yet implemented
rm tests/ui/simd/array-type.rs # "Index argument for `simd_insert` is not a constant"
-rm tests/ui/simd/intrinsic/generic-bswap-byte.rs # simd_bswap not yet implemented
-rm tests/ui/simd/intrinsic/generic-arithmetic-pass.rs # many missing simd intrinsics
# exotic linkages
rm tests/ui/issues/issue-33992.rs # unsupported linkages
@@ -76,7 +68,8 @@ rm -r tests/run-make/split-debuginfo # same
rm -r tests/run-make/symbols-include-type-name # --emit=asm not supported
rm -r tests/run-make/target-specs # i686 not supported by Cranelift
rm -r tests/run-make/mismatching-target-triples # same
-rm -r tests/run-make/use-extern-for-plugins # same
+rm tests/ui/asm/x86_64/issue-82869.rs # vector regs in inline asm not yet supported
+rm tests/ui/asm/x86_64/issue-96797.rs # const and sym inline asm operands don't work entirely correctly
# requires LTO
rm -r tests/run-make/cdylib
@@ -117,20 +110,6 @@ rm tests/ui/consts/issue-33537.rs # same
rm tests/ui/layout/valid_range_oob.rs # different ICE message
rm tests/ui/const-generics/generic_const_exprs/issue-80742.rs # gives error instead of ICE with cg_clif
-rm tests/ui/consts/issue-miri-1910.rs # different error message
-rm tests/ui/consts/offset_ub.rs # same
-rm tests/ui/consts/const-eval/ub-slice-get-unchecked.rs # same
-rm tests/ui/intrinsics/panic-uninitialized-zeroed.rs # same
-rm tests/ui/lint/lint-const-item-mutation.rs # same
-rm tests/ui/pattern/usefulness/doc-hidden-non-exhaustive.rs # same
-rm tests/ui/suggestions/derive-trait-for-method-call.rs # same
-rm tests/ui/typeck/issue-46112.rs # same
-rm tests/ui/consts/const_cmp_type_id.rs # same
-rm tests/ui/consts/issue-73976-monomorphic.rs # same
-rm tests/ui/rfcs/rfc-3348-c-string-literals/non-ascii.rs # same
-rm tests/ui/consts/const-eval/nonnull_as_ref_ub.rs # same
-rm tests/ui/consts/issue-94675.rs # same
-
# rustdoc-clif passes extra args, suppressing the help message when no args are passed
rm -r tests/run-make/issue-88756-default-output
@@ -154,9 +133,12 @@ rm -r tests/run-make/output-type-permutations # same
rm -r tests/run-make/used # same
rm -r tests/run-make/no-alloc-shim
rm -r tests/run-make/emit-to-stdout
+rm -r tests/run-make/compressed-debuginfo
rm -r tests/run-make/extern-fn-explicit-align # argument alignment not yet supported
+rm tests/ui/codegen/subtyping-enforces-type-equality.rs # assert_assignable bug with Coroutine's
+
# bugs in the test suite
# ======================
rm tests/ui/backtrace.rs # TODO warning
@@ -164,6 +146,11 @@ rm tests/ui/process/nofile-limit.rs # TODO some AArch64 linking issue
rm tests/ui/stdio-is-blocking.rs # really slow with unoptimized libstd
+# rustc bugs
+# ==========
+# https://github.com/rust-lang/rust/pull/116447#issuecomment-1790451463
+rm tests/ui/coroutine/gen_block_*.rs
+
cp ../dist/bin/rustdoc-clif ../dist/bin/rustdoc # some tests expect bin/rustdoc to exist
# prevent $(RUSTDOC) from picking up the sysroot built by x.py. It conflicts with the one used by
diff --git a/compiler/rustc_codegen_cranelift/src/abi/mod.rs b/compiler/rustc_codegen_cranelift/src/abi/mod.rs
index 5d775b9b5..c4572e035 100644
--- a/compiler/rustc_codegen_cranelift/src/abi/mod.rs
+++ b/compiler/rustc_codegen_cranelift/src/abi/mod.rs
@@ -6,6 +6,7 @@ mod returning;
use std::borrow::Cow;
+use cranelift_codegen::ir::{AbiParam, SigRef};
use cranelift_module::ModuleError;
use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags;
use rustc_middle::ty::layout::FnAbiOf;
@@ -13,12 +14,9 @@ use rustc_session::Session;
use rustc_target::abi::call::{Conv, FnAbi};
use rustc_target::spec::abi::Abi;
-use cranelift_codegen::ir::{AbiParam, SigRef};
-
use self::pass_mode::*;
-use crate::prelude::*;
-
pub(crate) use self::returning::codegen_return;
+use crate::prelude::*;
fn clif_sig_from_fn_abi<'tcx>(
tcx: TyCtxt<'tcx>,
@@ -30,7 +28,7 @@ fn clif_sig_from_fn_abi<'tcx>(
let inputs = fn_abi.args.iter().flat_map(|arg_abi| arg_abi.get_abi_param(tcx).into_iter());
let (return_ptr, returns) = fn_abi.ret.get_abi_return(tcx);
- // Sometimes the first param is an pointer to the place where the return value needs to be stored.
+ // Sometimes the first param is a pointer to the place where the return value needs to be stored.
let params: Vec<_> = return_ptr.into_iter().chain(inputs).collect();
Signature { params, returns, call_conv }
@@ -122,32 +120,25 @@ impl<'tcx> FunctionCx<'_, '_, 'tcx> {
args: &[Value],
) -> Cow<'_, [Value]> {
if self.tcx.sess.target.is_like_windows {
- let (mut params, mut args): (Vec<_>, Vec<_>) =
- params
- .into_iter()
- .zip(args)
- .map(|(param, &arg)| {
- if param.value_type == types::I128 {
- let arg_ptr = Pointer::stack_slot(self.bcx.create_sized_stack_slot(
- StackSlotData { kind: StackSlotKind::ExplicitSlot, size: 16 },
- ));
- arg_ptr.store(self, arg, MemFlags::trusted());
- (AbiParam::new(self.pointer_type), arg_ptr.get_addr(self))
- } else {
- (param, arg)
- }
- })
- .unzip();
+ let (mut params, mut args): (Vec<_>, Vec<_>) = params
+ .into_iter()
+ .zip(args)
+ .map(|(param, &arg)| {
+ if param.value_type == types::I128 {
+ let arg_ptr = self.create_stack_slot(16, 16);
+ arg_ptr.store(self, arg, MemFlags::trusted());
+ (AbiParam::new(self.pointer_type), arg_ptr.get_addr(self))
+ } else {
+ (param, arg)
+ }
+ })
+ .unzip();
let indirect_ret_val = returns.len() == 1 && returns[0].value_type == types::I128;
if indirect_ret_val {
params.insert(0, AbiParam::new(self.pointer_type));
- let ret_ptr =
- Pointer::stack_slot(self.bcx.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- size: 16,
- }));
+ let ret_ptr = self.create_stack_slot(16, 16);
args.insert(0, ret_ptr.get_addr(self));
self.lib_call_unadjusted(name, params, vec![], &args);
return Cow::Owned(vec![ret_ptr.load(self, types::I128, MemFlags::trusted())]);
diff --git a/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs b/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs
index 0d16da480..065226700 100644
--- a/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs
+++ b/compiler/rustc_codegen_cranelift/src/abi/pass_mode.rs
@@ -1,14 +1,14 @@
//! Argument passing
-use crate::prelude::*;
-use crate::value_and_place::assert_assignable;
-
use cranelift_codegen::ir::{ArgumentExtension, ArgumentPurpose};
use rustc_target::abi::call::{
ArgAbi, ArgAttributes, ArgExtension as RustcArgExtension, CastTarget, PassMode, Reg, RegKind,
};
use smallvec::{smallvec, SmallVec};
+use crate::prelude::*;
+use crate::value_and_place::assert_assignable;
+
pub(super) trait ArgAbiExt<'tcx> {
fn get_abi_param(&self, tcx: TyCtxt<'tcx>) -> SmallVec<[AbiParam; 2]>;
fn get_abi_return(&self, tcx: TyCtxt<'tcx>) -> (Option<AbiParam>, Vec<AbiParam>);
@@ -189,16 +189,13 @@ pub(super) fn from_casted_value<'tcx>(
let abi_params = cast_target_to_abi_params(cast);
let abi_param_size: u32 = abi_params.iter().map(|param| param.value_type.bytes()).sum();
let layout_size = u32::try_from(layout.size.bytes()).unwrap();
- let stack_slot = fx.bcx.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- // FIXME Don't force the size to a multiple of 16 bytes once Cranelift gets a way to
- // specify stack slot alignment.
+ let ptr = fx.create_stack_slot(
// Stack slot size may be bigger for example `[u8; 3]` which is packed into an `i32`.
// It may also be smaller for example when the type is a wrapper around an integer with a
// larger alignment than the integer.
- size: (std::cmp::max(abi_param_size, layout_size) + 15) / 16 * 16,
- });
- let ptr = Pointer::stack_slot(stack_slot);
+ std::cmp::max(abi_param_size, layout_size),
+ u32::try_from(layout.align.pref.bytes()).unwrap(),
+ );
let mut offset = 0;
let mut block_params_iter = block_params.iter().copied();
for param in abi_params {
diff --git a/compiler/rustc_codegen_cranelift/src/abi/returning.rs b/compiler/rustc_codegen_cranelift/src/abi/returning.rs
index 646fb4a3c..0799a22c6 100644
--- a/compiler/rustc_codegen_cranelift/src/abi/returning.rs
+++ b/compiler/rustc_codegen_cranelift/src/abi/returning.rs
@@ -1,10 +1,10 @@
//! Return value handling
-use crate::prelude::*;
-
use rustc_target::abi::call::{ArgAbi, PassMode};
use smallvec::{smallvec, SmallVec};
+use crate::prelude::*;
+
/// Return a place where the return value of the current function can be written to. If necessary
/// this adds an extra parameter pointing to where the return value needs to be stored.
pub(super) fn codegen_return_param<'tcx>(
diff --git a/compiler/rustc_codegen_cranelift/src/allocator.rs b/compiler/rustc_codegen_cranelift/src/allocator.rs
index 4e4c595de..e8af3e8c2 100644
--- a/compiler/rustc_codegen_cranelift/src/allocator.rs
+++ b/compiler/rustc_codegen_cranelift/src/allocator.rs
@@ -1,8 +1,6 @@
//! Allocator shim
// Adapted from rustc
-use crate::prelude::*;
-
use rustc_ast::expand::allocator::{
alloc_error_handler_name, default_fn_name, global_fn_name, AllocatorKind, AllocatorTy,
ALLOCATOR_METHODS, NO_ALLOC_SHIM_IS_UNSTABLE,
@@ -10,6 +8,8 @@ use rustc_ast::expand::allocator::{
use rustc_codegen_ssa::base::allocator_kind_for_codegen;
use rustc_session::config::OomStrategy;
+use crate::prelude::*;
+
/// Returns whether an allocator shim was created
pub(crate) fn codegen(
tcx: TyCtxt<'_>,
diff --git a/compiler/rustc_codegen_cranelift/src/analyze.rs b/compiler/rustc_codegen_cranelift/src/analyze.rs
index 359d581c1..321612238 100644
--- a/compiler/rustc_codegen_cranelift/src/analyze.rs
+++ b/compiler/rustc_codegen_cranelift/src/analyze.rs
@@ -1,11 +1,11 @@
//! SSA analysis
-use crate::prelude::*;
-
use rustc_index::IndexVec;
use rustc_middle::mir::StatementKind::*;
use rustc_middle::ty::Ty;
+use crate::prelude::*;
+
#[derive(Copy, Clone, Debug, PartialEq, Eq, Hash)]
pub(crate) enum SsaKind {
NotSsa,
diff --git a/compiler/rustc_codegen_cranelift/src/base.rs b/compiler/rustc_codegen_cranelift/src/base.rs
index 0a451dad9..91b1547cb 100644
--- a/compiler/rustc_codegen_cranelift/src/base.rs
+++ b/compiler/rustc_codegen_cranelift/src/base.rs
@@ -1,15 +1,14 @@
//! Codegen of a single function
+use cranelift_codegen::ir::UserFuncName;
+use cranelift_codegen::CodegenError;
+use cranelift_module::ModuleError;
use rustc_ast::InlineAsmOptions;
use rustc_index::IndexVec;
use rustc_middle::ty::adjustment::PointerCoercion;
use rustc_middle::ty::layout::FnAbiOf;
use rustc_middle::ty::print::with_no_trimmed_paths;
-use cranelift_codegen::ir::UserFuncName;
-use cranelift_codegen::CodegenError;
-use cranelift_module::ModuleError;
-
use crate::constant::ConstantCx;
use crate::debuginfo::FunctionDebugContext;
use crate::prelude::*;
@@ -250,17 +249,6 @@ pub(crate) fn verify_func(
}
fn codegen_fn_body(fx: &mut FunctionCx<'_, '_, '_>, start_block: Block) {
- if let Err(err) =
- fx.mir.post_mono_checks(fx.tcx, ty::ParamEnv::reveal_all(), |c| Ok(fx.monomorphize(c)))
- {
- err.emit_err(fx.tcx);
- fx.bcx.append_block_params_for_function_params(fx.block_map[START_BLOCK]);
- fx.bcx.switch_to_block(fx.block_map[START_BLOCK]);
- // compilation should have been aborted
- fx.bcx.ins().trap(TrapCode::UnreachableCodeReached);
- return;
- }
-
let arg_uninhabited = fx
.mir
.args_iter()
@@ -490,7 +478,7 @@ fn codegen_fn_body(fx: &mut FunctionCx<'_, '_, '_>, start_block: Block) {
TerminatorKind::Yield { .. }
| TerminatorKind::FalseEdge { .. }
| TerminatorKind::FalseUnwind { .. }
- | TerminatorKind::GeneratorDrop => {
+ | TerminatorKind::CoroutineDrop => {
bug!("shouldn't exist at codegen {:?}", bb_data.terminator());
}
TerminatorKind::Drop { place, target, unwind: _, replace: _ } => {
@@ -778,7 +766,7 @@ fn codegen_stmt<'tcx>(
NullOp::SizeOf => layout.size.bytes(),
NullOp::AlignOf => layout.align.abi.bytes(),
NullOp::OffsetOf(fields) => {
- layout.offset_of_subfield(fx, fields.iter().map(|f| f.index())).bytes()
+ layout.offset_of_subfield(fx, fields.iter()).bytes()
}
};
let val = CValue::by_val(
diff --git a/compiler/rustc_codegen_cranelift/src/cast.rs b/compiler/rustc_codegen_cranelift/src/cast.rs
index 6bf3a866b..0b5cb1547 100644
--- a/compiler/rustc_codegen_cranelift/src/cast.rs
+++ b/compiler/rustc_codegen_cranelift/src/cast.rs
@@ -104,11 +104,7 @@ pub(crate) fn clif_int_or_float_cast(
&[from],
)[0];
// FIXME(bytecodealliance/wasmtime#6104) use bitcast instead of store to get from i64x2 to i128
- let stack_slot = fx.bcx.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- size: 16,
- });
- let ret_ptr = Pointer::stack_slot(stack_slot);
+ let ret_ptr = fx.create_stack_slot(16, 16);
ret_ptr.store(fx, ret, MemFlags::trusted());
ret_ptr.load(fx, types::I128, MemFlags::trusted())
} else {
@@ -129,8 +125,8 @@ pub(crate) fn clif_int_or_float_cast(
let (min, max) = match (to_ty, to_signed) {
(types::I8, false) => (0, i64::from(u8::MAX)),
(types::I16, false) => (0, i64::from(u16::MAX)),
- (types::I8, true) => (i64::from(i8::MIN), i64::from(i8::MAX)),
- (types::I16, true) => (i64::from(i16::MIN), i64::from(i16::MAX)),
+ (types::I8, true) => (i64::from(i8::MIN as u32), i64::from(i8::MAX as u32)),
+ (types::I16, true) => (i64::from(i16::MIN as u32), i64::from(i16::MAX as u32)),
_ => unreachable!(),
};
let min_val = fx.bcx.ins().iconst(types::I32, min);
diff --git a/compiler/rustc_codegen_cranelift/src/common.rs b/compiler/rustc_codegen_cranelift/src/common.rs
index 359b430b4..63562d335 100644
--- a/compiler/rustc_codegen_cranelift/src/common.rs
+++ b/compiler/rustc_codegen_cranelift/src/common.rs
@@ -1,6 +1,5 @@
use cranelift_codegen::isa::TargetFrontendConfig;
use gimli::write::FileId;
-
use rustc_data_structures::sync::Lrc;
use rustc_index::IndexVec;
use rustc_middle::ty::layout::{
@@ -204,9 +203,9 @@ pub(crate) fn type_min_max_value(
(types::I8, false) | (types::I16, false) | (types::I32, false) | (types::I64, false) => {
0i64
}
- (types::I8, true) => i64::from(i8::MIN),
- (types::I16, true) => i64::from(i16::MIN),
- (types::I32, true) => i64::from(i32::MIN),
+ (types::I8, true) => i64::from(i8::MIN as u8),
+ (types::I16, true) => i64::from(i16::MIN as u16),
+ (types::I32, true) => i64::from(i32::MIN as u32),
(types::I64, true) => i64::MIN,
_ => unreachable!(),
};
@@ -216,9 +215,9 @@ pub(crate) fn type_min_max_value(
(types::I16, false) => i64::from(u16::MAX),
(types::I32, false) => i64::from(u32::MAX),
(types::I64, false) => u64::MAX as i64,
- (types::I8, true) => i64::from(i8::MAX),
- (types::I16, true) => i64::from(i16::MAX),
- (types::I32, true) => i64::from(i32::MAX),
+ (types::I8, true) => i64::from(i8::MAX as u8),
+ (types::I16, true) => i64::from(i16::MAX as u16),
+ (types::I32, true) => i64::from(i32::MAX as u32),
(types::I64, true) => i64::MAX,
_ => unreachable!(),
};
@@ -384,6 +383,25 @@ impl<'tcx> FunctionCx<'_, '_, 'tcx> {
})
}
+ pub(crate) fn create_stack_slot(&mut self, size: u32, align: u32) -> Pointer {
+ if align <= 16 {
+ let stack_slot = self.bcx.create_sized_stack_slot(StackSlotData {
+ kind: StackSlotKind::ExplicitSlot,
+ // FIXME Don't force the size to a multiple of 16 bytes once Cranelift gets a way to
+ // specify stack slot alignment.
+ size: (size + 15) / 16 * 16,
+ });
+ Pointer::stack_slot(stack_slot)
+ } else {
+ // Alignment is too big to handle using the above hack. Dynamically realign a stack slot
+ // instead. This wastes some space for the realignment.
+ let base_ptr = self.create_stack_slot(size + align, 16).get_addr(self);
+ let misalign_offset = self.bcx.ins().urem_imm(base_ptr, i64::from(align));
+ let realign_offset = self.bcx.ins().irsub_imm(misalign_offset, i64::from(align));
+ Pointer::new(self.bcx.ins().iadd(base_ptr, realign_offset))
+ }
+ }
+
pub(crate) fn set_debug_loc(&mut self, source_info: mir::SourceInfo) {
if let Some(debug_context) = &mut self.cx.debug_context {
let (file, line, column) =
@@ -412,46 +430,11 @@ impl<'tcx> FunctionCx<'_, '_, 'tcx> {
}
}
- // Note: must be kept in sync with get_caller_location from cg_ssa
- pub(crate) fn get_caller_location(&mut self, mut source_info: mir::SourceInfo) -> CValue<'tcx> {
- let span_to_caller_location = |fx: &mut FunctionCx<'_, '_, 'tcx>, span: Span| {
- let topmost = span.ctxt().outer_expn().expansion_cause().unwrap_or(span);
- let caller = fx.tcx.sess.source_map().lookup_char_pos(topmost.lo());
- let const_loc = fx.tcx.const_caller_location((
- rustc_span::symbol::Symbol::intern(
- &caller.file.name.prefer_remapped().to_string_lossy(),
- ),
- caller.line as u32,
- caller.col_display as u32 + 1,
- ));
- crate::constant::codegen_const_value(fx, const_loc, fx.tcx.caller_location_ty())
- };
-
- // Walk up the `SourceScope`s, in case some of them are from MIR inlining.
- // If so, the starting `source_info.span` is in the innermost inlined
- // function, and will be replaced with outer callsite spans as long
- // as the inlined functions were `#[track_caller]`.
- loop {
- let scope_data = &self.mir.source_scopes[source_info.scope];
-
- if let Some((callee, callsite_span)) = scope_data.inlined {
- // Stop inside the most nested non-`#[track_caller]` function,
- // before ever reaching its caller (which is irrelevant).
- if !callee.def.requires_caller_location(self.tcx) {
- return span_to_caller_location(self, source_info.span);
- }
- source_info.span = callsite_span;
- }
-
- // Skip past all of the parents with `inlined: None`.
- match scope_data.inlined_parent_scope {
- Some(parent) => source_info.scope = parent,
- None => break,
- }
- }
-
- // No inlined `SourceScope`s, or all of them were `#[track_caller]`.
- self.caller_location.unwrap_or_else(|| span_to_caller_location(self, source_info.span))
+ pub(crate) fn get_caller_location(&mut self, source_info: mir::SourceInfo) -> CValue<'tcx> {
+ self.mir.caller_location_span(source_info, self.caller_location, self.tcx, |span| {
+ let const_loc = self.tcx.span_as_caller_location(span);
+ crate::constant::codegen_const_value(self, const_loc, self.tcx.caller_location_ty())
+ })
}
pub(crate) fn anonymous_str(&mut self, msg: &str) -> Value {
diff --git a/compiler/rustc_codegen_cranelift/src/concurrency_limiter.rs b/compiler/rustc_codegen_cranelift/src/concurrency_limiter.rs
index d2b928db7..20f2ee4c7 100644
--- a/compiler/rustc_codegen_cranelift/src/concurrency_limiter.rs
+++ b/compiler/rustc_codegen_cranelift/src/concurrency_limiter.rs
@@ -1,8 +1,7 @@
use std::sync::{Arc, Condvar, Mutex};
-use rustc_session::Session;
-
use jobserver::HelperThread;
+use rustc_session::Session;
// FIXME don't panic when a worker thread panics
diff --git a/compiler/rustc_codegen_cranelift/src/constant.rs b/compiler/rustc_codegen_cranelift/src/constant.rs
index 14b10ed8b..b0853d30e 100644
--- a/compiler/rustc_codegen_cranelift/src/constant.rs
+++ b/compiler/rustc_codegen_cranelift/src/constant.rs
@@ -1,12 +1,11 @@
//! Handling of `static`s, `const`s and promoted allocations
+use cranelift_module::*;
use rustc_data_structures::fx::{FxHashMap, FxHashSet};
use rustc_middle::middle::codegen_fn_attrs::CodegenFnAttrFlags;
use rustc_middle::mir::interpret::{read_target_uint, AllocId, GlobalAlloc, Scalar};
use rustc_middle::mir::ConstValue;
-use cranelift_module::*;
-
use crate::prelude::*;
pub(crate) struct ConstantCx {
@@ -101,7 +100,7 @@ pub(crate) fn codegen_const_value<'tcx>(
if fx.clif_type(layout.ty).is_some() {
return CValue::const_val(fx, layout, int);
} else {
- let raw_val = int.to_bits(int.size()).unwrap();
+ let raw_val = int.size().truncate(int.to_bits(int.size()).unwrap());
let val = match int.size().bytes() {
1 => fx.bcx.ins().iconst(types::I8, raw_val as i64),
2 => fx.bcx.ins().iconst(types::I16, raw_val as i64),
@@ -187,8 +186,7 @@ pub(crate) fn codegen_const_value<'tcx>(
ConstValue::Slice { data, meta } => {
let alloc_id = fx.tcx.reserve_and_set_memory_alloc(data);
let ptr = pointer_for_allocation(fx, alloc_id).get_addr(fx);
- // FIXME: the `try_from` here can actually fail, e.g. for very long ZST slices.
- let len = fx.bcx.ins().iconst(fx.pointer_type, i64::try_from(meta).unwrap());
+ let len = fx.bcx.ins().iconst(fx.pointer_type, meta as i64);
CValue::by_val_pair(ptr, len, layout)
}
}
@@ -512,7 +510,7 @@ pub(crate) fn mir_operand_get_const_val<'tcx>(
| TerminatorKind::Drop { .. }
| TerminatorKind::Assert { .. } => {}
TerminatorKind::Yield { .. }
- | TerminatorKind::GeneratorDrop
+ | TerminatorKind::CoroutineDrop
| TerminatorKind::FalseEdge { .. }
| TerminatorKind::FalseUnwind { .. } => unreachable!(),
TerminatorKind::InlineAsm { .. } => return None,
diff --git a/compiler/rustc_codegen_cranelift/src/debuginfo/emit.rs b/compiler/rustc_codegen_cranelift/src/debuginfo/emit.rs
index c4a5627e6..81b819a55 100644
--- a/compiler/rustc_codegen_cranelift/src/debuginfo/emit.rs
+++ b/compiler/rustc_codegen_cranelift/src/debuginfo/emit.rs
@@ -1,10 +1,9 @@
//! Write the debuginfo into an object file.
use cranelift_object::ObjectProduct;
-use rustc_data_structures::fx::FxHashMap;
-
use gimli::write::{Address, AttributeValue, EndianVec, Result, Sections, Writer};
use gimli::{RunTimeEndian, SectionId};
+use rustc_data_structures::fx::FxHashMap;
use super::object::WriteDebugInfo;
use super::DebugContext;
diff --git a/compiler/rustc_codegen_cranelift/src/debuginfo/line_info.rs b/compiler/rustc_codegen_cranelift/src/debuginfo/line_info.rs
index b19b935a0..6230ca15d 100644
--- a/compiler/rustc_codegen_cranelift/src/debuginfo/line_info.rs
+++ b/compiler/rustc_codegen_cranelift/src/debuginfo/line_info.rs
@@ -3,20 +3,18 @@
use std::ffi::OsStr;
use std::path::{Component, Path};
-use crate::debuginfo::FunctionDebugContext;
-use crate::prelude::*;
-
-use rustc_data_structures::sync::Lrc;
-use rustc_span::{
- FileName, Pos, SourceFile, SourceFileAndLine, SourceFileHash, SourceFileHashAlgorithm,
-};
-
use cranelift_codegen::binemit::CodeOffset;
use cranelift_codegen::MachSrcLoc;
-
use gimli::write::{
Address, AttributeValue, FileId, FileInfo, LineProgram, LineString, LineStringTable,
};
+use rustc_data_structures::sync::Lrc;
+use rustc_span::{
+ FileName, Pos, SourceFile, SourceFileAndLine, SourceFileHash, SourceFileHashAlgorithm,
+};
+
+use crate::debuginfo::FunctionDebugContext;
+use crate::prelude::*;
// OPTIMIZATION: It is cheaper to do this in one pass than using `.parent()` and `.file_name()`.
fn split_path_dir_and_file(path: &Path) -> (&Path, &OsStr) {
@@ -97,7 +95,11 @@ impl DebugContext {
match &source_file.name {
FileName::Real(path) => {
let (dir_path, file_name) =
- split_path_dir_and_file(path.remapped_path_if_available());
+ split_path_dir_and_file(if self.should_remap_filepaths {
+ path.remapped_path_if_available()
+ } else {
+ path.local_path_if_available()
+ });
let dir_name = osstr_as_utf8_bytes(dir_path.as_os_str());
let file_name = osstr_as_utf8_bytes(file_name);
@@ -118,7 +120,14 @@ impl DebugContext {
filename => {
let dir_id = line_program.default_directory();
let dummy_file_name = LineString::new(
- filename.prefer_remapped().to_string().into_bytes(),
+ filename
+ .display(if self.should_remap_filepaths {
+ FileNameDisplayPreference::Remapped
+ } else {
+ FileNameDisplayPreference::Local
+ })
+ .to_string()
+ .into_bytes(),
line_program.encoding(),
line_strings,
);
diff --git a/compiler/rustc_codegen_cranelift/src/debuginfo/mod.rs b/compiler/rustc_codegen_cranelift/src/debuginfo/mod.rs
index 8a4b1cccf..e6edc452c 100644
--- a/compiler/rustc_codegen_cranelift/src/debuginfo/mod.rs
+++ b/compiler/rustc_codegen_cranelift/src/debuginfo/mod.rs
@@ -5,11 +5,8 @@ mod line_info;
mod object;
mod unwind;
-use crate::prelude::*;
-
use cranelift_codegen::ir::Endianness;
use cranelift_codegen::isa::TargetIsa;
-
use gimli::write::{
Address, AttributeValue, DwarfUnit, FileId, LineProgram, LineString, Range, RangeList,
UnitEntryId,
@@ -17,12 +14,13 @@ use gimli::write::{
use gimli::{Encoding, Format, LineEncoding, RunTimeEndian};
use indexmap::IndexSet;
-pub(crate) use emit::{DebugReloc, DebugRelocName};
-pub(crate) use unwind::UnwindContext;
+pub(crate) use self::emit::{DebugReloc, DebugRelocName};
+pub(crate) use self::unwind::UnwindContext;
+use crate::prelude::*;
pub(crate) fn producer() -> String {
format!(
- "cg_clif (rustc {}, cranelift {})",
+ "rustc version {} with cranelift {}",
rustc_interface::util::rustc_version_str().unwrap_or("unknown version"),
cranelift_codegen::VERSION,
)
@@ -33,6 +31,8 @@ pub(crate) struct DebugContext {
dwarf: DwarfUnit,
unit_range_list: RangeList,
+
+ should_remap_filepaths: bool,
}
pub(crate) struct FunctionDebugContext {
@@ -65,12 +65,18 @@ impl DebugContext {
let mut dwarf = DwarfUnit::new(encoding);
+ let should_remap_filepaths = tcx.sess.should_prefer_remapped_for_codegen();
+
let producer = producer();
let comp_dir = tcx
.sess
.opts
.working_dir
- .to_string_lossy(FileNameDisplayPreference::Remapped)
+ .to_string_lossy(if should_remap_filepaths {
+ FileNameDisplayPreference::Remapped
+ } else {
+ FileNameDisplayPreference::Local
+ })
.into_owned();
let (name, file_info) = match tcx.sess.local_crate_source_file() {
Some(path) => {
@@ -104,7 +110,12 @@ impl DebugContext {
root.set(gimli::DW_AT_low_pc, AttributeValue::Address(Address::Constant(0)));
}
- DebugContext { endian, dwarf, unit_range_list: RangeList(Vec::new()) }
+ DebugContext {
+ endian,
+ dwarf,
+ unit_range_list: RangeList(Vec::new()),
+ should_remap_filepaths,
+ }
}
pub(crate) fn define_function(
diff --git a/compiler/rustc_codegen_cranelift/src/debuginfo/object.rs b/compiler/rustc_codegen_cranelift/src/debuginfo/object.rs
index 9dc9b2cf9..f1840a7bf 100644
--- a/compiler/rustc_codegen_cranelift/src/debuginfo/object.rs
+++ b/compiler/rustc_codegen_cranelift/src/debuginfo/object.rs
@@ -1,12 +1,9 @@
-use rustc_data_structures::fx::FxHashMap;
-
use cranelift_module::FuncId;
use cranelift_object::ObjectProduct;
-
+use gimli::SectionId;
use object::write::{Relocation, StandardSegment};
use object::{RelocationEncoding, SectionKind};
-
-use gimli::SectionId;
+use rustc_data_structures::fx::FxHashMap;
use crate::debuginfo::{DebugReloc, DebugRelocName};
diff --git a/compiler/rustc_codegen_cranelift/src/debuginfo/unwind.rs b/compiler/rustc_codegen_cranelift/src/debuginfo/unwind.rs
index 493359c74..35278e6fb 100644
--- a/compiler/rustc_codegen_cranelift/src/debuginfo/unwind.rs
+++ b/compiler/rustc_codegen_cranelift/src/debuginfo/unwind.rs
@@ -1,15 +1,13 @@
//! Unwind info generation (`.eh_frame`)
-use crate::prelude::*;
-
use cranelift_codegen::ir::Endianness;
use cranelift_codegen::isa::{unwind::UnwindInfo, TargetIsa};
-
use cranelift_object::ObjectProduct;
use gimli::write::{Address, CieId, EhFrame, FrameTable, Section};
use gimli::RunTimeEndian;
use super::object::WriteDebugInfo;
+use crate::prelude::*;
pub(crate) struct UnwindContext {
endian: RunTimeEndian,
diff --git a/compiler/rustc_codegen_cranelift/src/driver/aot.rs b/compiler/rustc_codegen_cranelift/src/driver/aot.rs
index 3e9383095..11229dd42 100644
--- a/compiler/rustc_codegen_cranelift/src/driver/aot.rs
+++ b/compiler/rustc_codegen_cranelift/src/driver/aot.rs
@@ -6,19 +6,19 @@ use std::path::PathBuf;
use std::sync::Arc;
use std::thread::JoinHandle;
+use cranelift_object::{ObjectBuilder, ObjectModule};
+use rustc_codegen_ssa::assert_module_sources::CguReuse;
use rustc_codegen_ssa::back::metadata::create_compressed_metadata_file;
+use rustc_codegen_ssa::base::determine_cgu_reuse;
use rustc_codegen_ssa::{CodegenResults, CompiledModule, CrateInfo, ModuleKind};
use rustc_data_structures::profiling::SelfProfilerRef;
use rustc_data_structures::stable_hasher::{HashStable, StableHasher};
use rustc_metadata::EncodedMetadata;
use rustc_middle::dep_graph::{WorkProduct, WorkProductId};
use rustc_middle::mir::mono::{CodegenUnit, MonoItem};
-use rustc_session::cgu_reuse_tracker::CguReuse;
use rustc_session::config::{DebugInfo, OutputFilenames, OutputType};
use rustc_session::Session;
-use cranelift_object::{ObjectBuilder, ObjectModule};
-
use crate::concurrency_limiter::{ConcurrencyLimiter, ConcurrencyLimiterToken};
use crate::global_asm::GlobalAsmConfig;
use crate::{prelude::*, BackendConfig};
@@ -361,12 +361,26 @@ pub(crate) fn run_aot(
metadata: EncodedMetadata,
need_metadata_module: bool,
) -> Box<OngoingCodegen> {
+ // FIXME handle `-Ctarget-cpu=native`
+ let target_cpu = match tcx.sess.opts.cg.target_cpu {
+ Some(ref name) => name,
+ None => tcx.sess.target.cpu.as_ref(),
+ }
+ .to_owned();
+
let cgus = if tcx.sess.opts.output_types.should_codegen() {
tcx.collect_and_partition_mono_items(()).1
} else {
// If only `--emit metadata` is used, we shouldn't perform any codegen.
// Also `tcx.collect_and_partition_mono_items` may panic in that case.
- &[]
+ return Box::new(OngoingCodegen {
+ modules: vec![],
+ allocator_module: None,
+ metadata_module: None,
+ metadata,
+ crate_info: CrateInfo::new(tcx, target_cpu),
+ concurrency_limiter: ConcurrencyLimiter::new(tcx.sess, 0),
+ });
};
if tcx.dep_graph.is_fully_enabled() {
@@ -375,20 +389,28 @@ pub(crate) fn run_aot(
}
}
+ // Calculate the CGU reuse
+ let cgu_reuse = tcx.sess.time("find_cgu_reuse", || {
+ cgus.iter().map(|cgu| determine_cgu_reuse(tcx, &cgu)).collect::<Vec<_>>()
+ });
+
+ rustc_codegen_ssa::assert_module_sources::assert_module_sources(tcx, &|cgu_reuse_tracker| {
+ for (i, cgu) in cgus.iter().enumerate() {
+ let cgu_reuse = cgu_reuse[i];
+ cgu_reuse_tracker.set_actual_reuse(cgu.name().as_str(), cgu_reuse);
+ }
+ });
+
let global_asm_config = Arc::new(crate::global_asm::GlobalAsmConfig::new(tcx));
let mut concurrency_limiter = ConcurrencyLimiter::new(tcx.sess, cgus.len());
let modules = tcx.sess.time("codegen mono items", || {
cgus.iter()
- .map(|cgu| {
- let cgu_reuse = if backend_config.disable_incr_cache {
- CguReuse::No
- } else {
- determine_cgu_reuse(tcx, cgu)
- };
- tcx.sess.cgu_reuse_tracker.set_actual_reuse(cgu.name().as_str(), cgu_reuse);
-
+ .enumerate()
+ .map(|(i, cgu)| {
+ let cgu_reuse =
+ if backend_config.disable_incr_cache { CguReuse::No } else { cgu_reuse[i] };
match cgu_reuse {
CguReuse::No => {
let dep_node = cgu.codegen_dep_node(tcx);
@@ -407,8 +429,7 @@ pub(crate) fn run_aot(
)
.0
}
- CguReuse::PreLto => unreachable!(),
- CguReuse::PostLto => {
+ CguReuse::PreLto | CguReuse::PostLto => {
concurrency_limiter.job_already_done();
OngoingModuleCodegen::Sync(reuse_workproduct_for_cgu(tcx, cgu))
}
@@ -474,13 +495,6 @@ pub(crate) fn run_aot(
None
};
- // FIXME handle `-Ctarget-cpu=native`
- let target_cpu = match tcx.sess.opts.cg.target_cpu {
- Some(ref name) => name,
- None => tcx.sess.target.cpu.as_ref(),
- }
- .to_owned();
-
Box::new(OngoingCodegen {
modules,
allocator_module,
@@ -490,32 +504,3 @@ pub(crate) fn run_aot(
concurrency_limiter,
})
}
-
-// Adapted from https://github.com/rust-lang/rust/blob/303d8aff6092709edd4dbd35b1c88e9aa40bf6d8/src/librustc_codegen_ssa/base.rs#L922-L953
-fn determine_cgu_reuse<'tcx>(tcx: TyCtxt<'tcx>, cgu: &CodegenUnit<'tcx>) -> CguReuse {
- if !tcx.dep_graph.is_fully_enabled() {
- return CguReuse::No;
- }
-
- let work_product_id = &cgu.work_product_id();
- if tcx.dep_graph.previous_work_product(work_product_id).is_none() {
- // We don't have anything cached for this CGU. This can happen
- // if the CGU did not exist in the previous session.
- return CguReuse::No;
- }
-
- // Try to mark the CGU as green. If it we can do so, it means that nothing
- // affecting the LLVM module has changed and we can re-use a cached version.
- // If we compile with any kind of LTO, this means we can re-use the bitcode
- // of the Pre-LTO stage (possibly also the Post-LTO version but we'll only
- // know that later). If we are not doing LTO, there is only one optimized
- // version of each module, so we re-use that.
- let dep_node = cgu.codegen_dep_node(tcx);
- assert!(
- !tcx.dep_graph.dep_node_exists(&dep_node),
- "CompileCodegenUnit dep-node for CGU `{}` already exists before marking.",
- cgu.name()
- );
-
- if tcx.try_mark_green(&dep_node) { CguReuse::PostLto } else { CguReuse::No }
-}
diff --git a/compiler/rustc_codegen_cranelift/src/driver/jit.rs b/compiler/rustc_codegen_cranelift/src/driver/jit.rs
index 1c606494f..6ee65d12c 100644
--- a/compiler/rustc_codegen_cranelift/src/driver/jit.rs
+++ b/compiler/rustc_codegen_cranelift/src/driver/jit.rs
@@ -6,13 +6,12 @@ use std::ffi::CString;
use std::os::raw::{c_char, c_int};
use std::sync::{mpsc, Mutex, OnceLock};
+use cranelift_jit::{JITBuilder, JITModule};
use rustc_codegen_ssa::CrateInfo;
use rustc_middle::mir::mono::MonoItem;
use rustc_session::Session;
use rustc_span::Symbol;
-use cranelift_jit::{JITBuilder, JITModule};
-
use crate::{prelude::*, BackendConfig};
use crate::{CodegenCx, CodegenMode};
diff --git a/compiler/rustc_codegen_cranelift/src/global_asm.rs b/compiler/rustc_codegen_cranelift/src/global_asm.rs
index baadd7a9e..b14007f4e 100644
--- a/compiler/rustc_codegen_cranelift/src/global_asm.rs
+++ b/compiler/rustc_codegen_cranelift/src/global_asm.rs
@@ -9,16 +9,22 @@ use std::sync::Arc;
use rustc_ast::{InlineAsmOptions, InlineAsmTemplatePiece};
use rustc_hir::{InlineAsmOperand, ItemId};
use rustc_session::config::{OutputFilenames, OutputType};
+use rustc_target::asm::InlineAsmArch;
use crate::prelude::*;
pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String, item_id: ItemId) {
let item = tcx.hir().item(item_id);
if let rustc_hir::ItemKind::GlobalAsm(asm) = item.kind {
- if !asm.options.contains(InlineAsmOptions::ATT_SYNTAX) {
- global_asm.push_str("\n.intel_syntax noprefix\n");
- } else {
- global_asm.push_str("\n.att_syntax\n");
+ let is_x86 =
+ matches!(tcx.sess.asm_arch.unwrap(), InlineAsmArch::X86 | InlineAsmArch::X86_64);
+
+ if is_x86 {
+ if !asm.options.contains(InlineAsmOptions::ATT_SYNTAX) {
+ global_asm.push_str("\n.intel_syntax noprefix\n");
+ } else {
+ global_asm.push_str("\n.att_syntax\n");
+ }
}
for piece in asm.template {
match *piece {
@@ -40,6 +46,13 @@ pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String,
global_asm.push_str(&string);
}
InlineAsmOperand::SymFn { anon_const } => {
+ if cfg!(not(feature = "inline_asm_sym")) {
+ tcx.sess.span_err(
+ item.span,
+ "asm! and global_asm! sym operands are not yet supported",
+ );
+ }
+
let ty = tcx.typeck_body(anon_const.body).node_type(anon_const.hir_id);
let instance = match ty.kind() {
&ty::FnDef(def_id, args) => Instance::new(def_id, args),
@@ -51,6 +64,13 @@ pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String,
global_asm.push_str(symbol.name);
}
InlineAsmOperand::SymStatic { path: _, def_id } => {
+ if cfg!(not(feature = "inline_asm_sym")) {
+ tcx.sess.span_err(
+ item.span,
+ "asm! and global_asm! sym operands are not yet supported",
+ );
+ }
+
let instance = Instance::mono(tcx, def_id).polymorphize(tcx);
let symbol = tcx.symbol_name(instance);
global_asm.push_str(symbol.name);
@@ -65,7 +85,11 @@ pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String,
}
}
}
- global_asm.push_str("\n.att_syntax\n\n");
+
+ global_asm.push('\n');
+ if is_x86 {
+ global_asm.push_str(".att_syntax\n\n");
+ }
} else {
bug!("Expected GlobalAsm found {:?}", item);
}
@@ -73,18 +97,21 @@ pub(crate) fn codegen_global_asm_item(tcx: TyCtxt<'_>, global_asm: &mut String,
#[derive(Debug)]
pub(crate) struct GlobalAsmConfig {
- asm_enabled: bool,
assembler: PathBuf,
+ target: String,
pub(crate) output_filenames: Arc<OutputFilenames>,
}
impl GlobalAsmConfig {
pub(crate) fn new(tcx: TyCtxt<'_>) -> Self {
- let asm_enabled = cfg!(feature = "inline_asm") && !tcx.sess.target.is_like_windows;
-
GlobalAsmConfig {
- asm_enabled,
assembler: crate::toolchain::get_toolchain_binary(tcx.sess, "as"),
+ target: match &tcx.sess.opts.target_triple {
+ rustc_target::spec::TargetTriple::TargetTriple(triple) => triple.clone(),
+ rustc_target::spec::TargetTriple::TargetJson { path_for_rustdoc, .. } => {
+ path_for_rustdoc.to_str().unwrap().to_owned()
+ }
+ },
output_filenames: tcx.output_filenames(()).clone(),
}
}
@@ -99,42 +126,75 @@ pub(crate) fn compile_global_asm(
return Ok(None);
}
- if !config.asm_enabled {
- if global_asm.contains("__rust_probestack") {
- return Ok(None);
- }
-
- if cfg!(not(feature = "inline_asm")) {
- return Err(
- "asm! and global_asm! support is disabled while compiling rustc_codegen_cranelift"
- .to_owned(),
- );
- } else {
- return Err("asm! and global_asm! are not yet supported on Windows".to_owned());
- }
- }
-
// Remove all LLVM style comments
- let global_asm = global_asm
+ let mut global_asm = global_asm
.lines()
.map(|line| if let Some(index) = line.find("//") { &line[0..index] } else { line })
.collect::<Vec<_>>()
.join("\n");
+ global_asm.push('\n');
- let output_object_file = config.output_filenames.temp_path(OutputType::Object, Some(cgu_name));
+ let global_asm_object_file = add_file_stem_postfix(
+ config.output_filenames.temp_path(OutputType::Object, Some(cgu_name)),
+ ".asm",
+ );
// Assemble `global_asm`
- let global_asm_object_file = add_file_stem_postfix(output_object_file, ".asm");
- let mut child = Command::new(&config.assembler)
- .arg("-o")
- .arg(&global_asm_object_file)
- .stdin(Stdio::piped())
- .spawn()
- .expect("Failed to spawn `as`.");
- child.stdin.take().unwrap().write_all(global_asm.as_bytes()).unwrap();
- let status = child.wait().expect("Failed to wait for `as`.");
- if !status.success() {
- return Err(format!("Failed to assemble `{}`", global_asm));
+ if option_env!("CG_CLIF_FORCE_GNU_AS").is_some() {
+ let mut child = Command::new(&config.assembler)
+ .arg("-o")
+ .arg(&global_asm_object_file)
+ .stdin(Stdio::piped())
+ .spawn()
+ .expect("Failed to spawn `as`.");
+ child.stdin.take().unwrap().write_all(global_asm.as_bytes()).unwrap();
+ let status = child.wait().expect("Failed to wait for `as`.");
+ if !status.success() {
+ return Err(format!("Failed to assemble `{}`", global_asm));
+ }
+ } else {
+ let mut child = Command::new(std::env::current_exe().unwrap())
+ .arg("--target")
+ .arg(&config.target)
+ .arg("--crate-type")
+ .arg("staticlib")
+ .arg("--emit")
+ .arg("obj")
+ .arg("-o")
+ .arg(&global_asm_object_file)
+ .arg("-")
+ .arg("-Abad_asm_style")
+ .arg("-Zcodegen-backend=llvm")
+ .stdin(Stdio::piped())
+ .spawn()
+ .expect("Failed to spawn `as`.");
+ let mut stdin = child.stdin.take().unwrap();
+ stdin
+ .write_all(
+ br####"
+ #![feature(decl_macro, no_core, rustc_attrs)]
+ #![allow(internal_features)]
+ #![no_core]
+ #[rustc_builtin_macro]
+ #[rustc_macro_transparency = "semitransparent"]
+ macro global_asm() { /* compiler built-in */ }
+ global_asm!(r###"
+ "####,
+ )
+ .unwrap();
+ stdin.write_all(global_asm.as_bytes()).unwrap();
+ stdin
+ .write_all(
+ br####"
+ "###);
+ "####,
+ )
+ .unwrap();
+ std::mem::drop(stdin);
+ let status = child.wait().expect("Failed to wait for `as`.");
+ if !status.success() {
+ return Err(format!("Failed to assemble `{}`", global_asm));
+ }
}
Ok(Some(global_asm_object_file))
diff --git a/compiler/rustc_codegen_cranelift/src/inline_asm.rs b/compiler/rustc_codegen_cranelift/src/inline_asm.rs
index 50bbf8105..ce0eecca8 100644
--- a/compiler/rustc_codegen_cranelift/src/inline_asm.rs
+++ b/compiler/rustc_codegen_cranelift/src/inline_asm.rs
@@ -1,18 +1,19 @@
//! Codegen of `asm!` invocations.
-use crate::prelude::*;
-
use std::fmt::Write;
use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
use rustc_middle::mir::InlineAsmOperand;
use rustc_span::sym;
use rustc_target::asm::*;
+use target_lexicon::BinaryFormat;
+
+use crate::prelude::*;
enum CInlineAsmOperand<'tcx> {
In {
reg: InlineAsmRegOrRegClass,
- value: CValue<'tcx>,
+ value: Value,
},
Out {
reg: InlineAsmRegOrRegClass,
@@ -22,7 +23,7 @@ enum CInlineAsmOperand<'tcx> {
InOut {
reg: InlineAsmRegOrRegClass,
_late: bool,
- in_value: CValue<'tcx>,
+ in_value: Value,
out_place: Option<CPlace<'tcx>>,
},
Const {
@@ -43,191 +44,23 @@ pub(crate) fn codegen_inline_asm<'tcx>(
) {
// FIXME add .eh_frame unwind info directives
- if !template.is_empty() {
- // Used by panic_abort
- if template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string()) {
- fx.bcx.ins().trap(TrapCode::User(1));
- return;
- }
-
- // Used by stdarch
- if template[0] == InlineAsmTemplatePiece::String("mov ".to_string())
- && matches!(
- template[1],
- InlineAsmTemplatePiece::Placeholder {
- operand_idx: 0,
- modifier: Some('r'),
- span: _
- }
- )
- && template[2] == InlineAsmTemplatePiece::String(", rbx".to_string())
- && template[3] == InlineAsmTemplatePiece::String("\n".to_string())
- && template[4] == InlineAsmTemplatePiece::String("cpuid".to_string())
- && template[5] == InlineAsmTemplatePiece::String("\n".to_string())
- && template[6] == InlineAsmTemplatePiece::String("xchg ".to_string())
- && matches!(
- template[7],
- InlineAsmTemplatePiece::Placeholder {
- operand_idx: 0,
- modifier: Some('r'),
- span: _
- }
- )
- && template[8] == InlineAsmTemplatePiece::String(", rbx".to_string())
- {
- assert_eq!(operands.len(), 4);
- let (leaf, eax_place) = match operands[1] {
- InlineAsmOperand::InOut {
- reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)),
- late: _,
- ref in_value,
- out_place: Some(out_place),
- } => (
- crate::base::codegen_operand(fx, in_value).load_scalar(fx),
- crate::base::codegen_place(fx, out_place),
- ),
- _ => unreachable!(),
- };
- let ebx_place = match operands[0] {
- InlineAsmOperand::Out {
- reg:
- InlineAsmRegOrRegClass::RegClass(InlineAsmRegClass::X86(
- X86InlineAsmRegClass::reg,
- )),
- late: _,
- place: Some(place),
- } => crate::base::codegen_place(fx, place),
- _ => unreachable!(),
- };
- let (sub_leaf, ecx_place) = match operands[2] {
- InlineAsmOperand::InOut {
- reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::cx)),
- late: _,
- ref in_value,
- out_place: Some(out_place),
- } => (
- crate::base::codegen_operand(fx, in_value).load_scalar(fx),
- crate::base::codegen_place(fx, out_place),
- ),
- _ => unreachable!(),
- };
- let edx_place = match operands[3] {
- InlineAsmOperand::Out {
- reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx)),
- late: _,
- place: Some(place),
- } => crate::base::codegen_place(fx, place),
- _ => unreachable!(),
- };
-
- let (eax, ebx, ecx, edx) = crate::intrinsics::codegen_cpuid_call(fx, leaf, sub_leaf);
-
- eax_place.write_cvalue(fx, CValue::by_val(eax, fx.layout_of(fx.tcx.types.u32)));
- ebx_place.write_cvalue(fx, CValue::by_val(ebx, fx.layout_of(fx.tcx.types.u32)));
- ecx_place.write_cvalue(fx, CValue::by_val(ecx, fx.layout_of(fx.tcx.types.u32)));
- edx_place.write_cvalue(fx, CValue::by_val(edx, fx.layout_of(fx.tcx.types.u32)));
- let destination_block = fx.get_block(destination.unwrap());
- fx.bcx.ins().jump(destination_block, &[]);
- return;
- }
-
- // Used by compiler-builtins
- if fx.tcx.symbol_name(fx.instance).name.starts_with("___chkstk") {
- // ___chkstk, ___chkstk_ms and __alloca are only used on Windows
- crate::trap::trap_unimplemented(fx, "Stack probes are not supported");
- return;
- } else if fx.tcx.symbol_name(fx.instance).name == "__alloca" {
- crate::trap::trap_unimplemented(fx, "Alloca is not supported");
- return;
- }
-
- // Used by measureme
- if template[0] == InlineAsmTemplatePiece::String("xor %eax, %eax".to_string())
- && template[1] == InlineAsmTemplatePiece::String("\n".to_string())
- && template[2] == InlineAsmTemplatePiece::String("mov %rbx, ".to_string())
- && matches!(
- template[3],
- InlineAsmTemplatePiece::Placeholder {
- operand_idx: 0,
- modifier: Some('r'),
- span: _
- }
- )
- && template[4] == InlineAsmTemplatePiece::String("\n".to_string())
- && template[5] == InlineAsmTemplatePiece::String("cpuid".to_string())
- && template[6] == InlineAsmTemplatePiece::String("\n".to_string())
- && template[7] == InlineAsmTemplatePiece::String("mov ".to_string())
- && matches!(
- template[8],
- InlineAsmTemplatePiece::Placeholder {
- operand_idx: 0,
- modifier: Some('r'),
- span: _
- }
- )
- && template[9] == InlineAsmTemplatePiece::String(", %rbx".to_string())
- {
- let destination_block = fx.get_block(destination.unwrap());
- fx.bcx.ins().jump(destination_block, &[]);
- return;
- } else if template[0] == InlineAsmTemplatePiece::String("rdpmc".to_string()) {
- // Return zero dummy values for all performance counters
- match operands[0] {
- InlineAsmOperand::In {
- reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::cx)),
- value: _,
- } => {}
- _ => unreachable!(),
- };
- let lo = match operands[1] {
- InlineAsmOperand::Out {
- reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)),
- late: true,
- place: Some(place),
- } => crate::base::codegen_place(fx, place),
- _ => unreachable!(),
- };
- let hi = match operands[2] {
- InlineAsmOperand::Out {
- reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx)),
- late: true,
- place: Some(place),
- } => crate::base::codegen_place(fx, place),
- _ => unreachable!(),
- };
-
- let u32_layout = fx.layout_of(fx.tcx.types.u32);
- let zero = fx.bcx.ins().iconst(types::I32, 0);
- lo.write_cvalue(fx, CValue::by_val(zero, u32_layout));
- hi.write_cvalue(fx, CValue::by_val(zero, u32_layout));
-
- let destination_block = fx.get_block(destination.unwrap());
- fx.bcx.ins().jump(destination_block, &[]);
- return;
- } else if template[0] == InlineAsmTemplatePiece::String("lock xadd ".to_string())
- && matches!(
- template[1],
- InlineAsmTemplatePiece::Placeholder { operand_idx: 1, modifier: None, span: _ }
- )
- && template[2] == InlineAsmTemplatePiece::String(", (".to_string())
- && matches!(
- template[3],
- InlineAsmTemplatePiece::Placeholder { operand_idx: 0, modifier: None, span: _ }
- )
- && template[4] == InlineAsmTemplatePiece::String(")".to_string())
- {
- let destination_block = fx.get_block(destination.unwrap());
- fx.bcx.ins().jump(destination_block, &[]);
- return;
- }
+ // Used by panic_abort on Windows, but uses a syntax which only happens to work with
+ // asm!() by accident and breaks with the GNU assembler as well as global_asm!() for
+ // the LLVM backend.
+ if template.len() == 1
+ && template[0] == InlineAsmTemplatePiece::String("int $$0x29".to_string())
+ {
+ fx.bcx.ins().trap(TrapCode::User(1));
+ return;
}
let operands = operands
.into_iter()
.map(|operand| match *operand {
- InlineAsmOperand::In { reg, ref value } => {
- CInlineAsmOperand::In { reg, value: crate::base::codegen_operand(fx, value) }
- }
+ InlineAsmOperand::In { reg, ref value } => CInlineAsmOperand::In {
+ reg,
+ value: crate::base::codegen_operand(fx, value).load_scalar(fx),
+ },
InlineAsmOperand::Out { reg, late, ref place } => CInlineAsmOperand::Out {
reg,
late,
@@ -237,7 +70,7 @@ pub(crate) fn codegen_inline_asm<'tcx>(
CInlineAsmOperand::InOut {
reg,
_late: late,
- in_value: crate::base::codegen_operand(fx, in_value),
+ in_value: crate::base::codegen_operand(fx, in_value).load_scalar(fx),
out_place: out_place.map(|place| crate::base::codegen_place(fx, place)),
}
}
@@ -252,6 +85,12 @@ pub(crate) fn codegen_inline_asm<'tcx>(
CInlineAsmOperand::Const { value }
}
InlineAsmOperand::SymFn { ref value } => {
+ if cfg!(not(feature = "inline_asm_sym")) {
+ fx.tcx
+ .sess
+ .span_err(span, "asm! and global_asm! sym operands are not yet supported");
+ }
+
let const_ = fx.monomorphize(value.const_);
if let ty::FnDef(def_id, args) = *const_.ty().kind() {
let instance = ty::Instance::resolve_for_fn_ptr(
@@ -329,7 +168,7 @@ pub(crate) fn codegen_inline_asm<'tcx>(
for (i, operand) in operands.iter().enumerate() {
match operand {
CInlineAsmOperand::In { reg: _, value } => {
- inputs.push((asm_gen.stack_slots_input[i].unwrap(), value.load_scalar(fx)));
+ inputs.push((asm_gen.stack_slots_input[i].unwrap(), *value));
}
CInlineAsmOperand::Out { reg: _, late: _, place } => {
if let Some(place) = place {
@@ -337,7 +176,7 @@ pub(crate) fn codegen_inline_asm<'tcx>(
}
}
CInlineAsmOperand::InOut { reg: _, _late: _, in_value, out_place } => {
- inputs.push((asm_gen.stack_slots_input[i].unwrap(), in_value.load_scalar(fx)));
+ inputs.push((asm_gen.stack_slots_input[i].unwrap(), *in_value));
if let Some(out_place) = out_place {
outputs.push((asm_gen.stack_slots_output[i].unwrap(), *out_place));
}
@@ -589,11 +428,29 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
}
fn generate_asm_wrapper(&self, asm_name: &str) -> String {
+ let binary_format = crate::target_triple(self.tcx.sess).binary_format;
+
let mut generated_asm = String::new();
- writeln!(generated_asm, ".globl {}", asm_name).unwrap();
- writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
- writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
- writeln!(generated_asm, "{}:", asm_name).unwrap();
+ match binary_format {
+ BinaryFormat::Elf => {
+ writeln!(generated_asm, ".globl {}", asm_name).unwrap();
+ writeln!(generated_asm, ".type {},@function", asm_name).unwrap();
+ writeln!(generated_asm, ".section .text.{},\"ax\",@progbits", asm_name).unwrap();
+ writeln!(generated_asm, "{}:", asm_name).unwrap();
+ }
+ BinaryFormat::Macho => {
+ writeln!(generated_asm, ".globl _{}", asm_name).unwrap();
+ writeln!(generated_asm, "_{}:", asm_name).unwrap();
+ }
+ BinaryFormat::Coff => {
+ writeln!(generated_asm, ".globl {}", asm_name).unwrap();
+ writeln!(generated_asm, "{}:", asm_name).unwrap();
+ }
+ _ => self
+ .tcx
+ .sess
+ .fatal(format!("Unsupported binary format for inline asm: {binary_format:?}")),
+ }
let is_x86 = matches!(self.arch, InlineAsmArch::X86 | InlineAsmArch::X86_64);
@@ -690,8 +547,19 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
if is_x86 {
generated_asm.push_str(".att_syntax\n");
}
- writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
- generated_asm.push_str(".text\n");
+
+ match binary_format {
+ BinaryFormat::Elf => {
+ writeln!(generated_asm, ".size {name}, .-{name}", name = asm_name).unwrap();
+ generated_asm.push_str(".text\n");
+ }
+ BinaryFormat::Macho | BinaryFormat::Coff => {}
+ _ => self
+ .tcx
+ .sess
+ .fatal(format!("Unsupported binary format for inline asm: {binary_format:?}")),
+ }
+
generated_asm.push_str("\n\n");
generated_asm
@@ -699,25 +567,26 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
fn prologue(generated_asm: &mut String, arch: InlineAsmArch) {
match arch {
- InlineAsmArch::X86 => {
- generated_asm.push_str(" push ebp\n");
- generated_asm.push_str(" mov ebp,[esp+8]\n");
- }
InlineAsmArch::X86_64 => {
generated_asm.push_str(" push rbp\n");
- generated_asm.push_str(" mov rbp,rdi\n");
- }
- InlineAsmArch::RiscV32 => {
- generated_asm.push_str(" addi sp, sp, -8\n");
- generated_asm.push_str(" sw ra, 4(sp)\n");
- generated_asm.push_str(" sw s0, 0(sp)\n");
- generated_asm.push_str(" mv s0, a0\n");
+ generated_asm.push_str(" mov rbp,rsp\n");
+ generated_asm.push_str(" push rbx\n"); // rbx is callee saved
+ // rbx is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
+ generated_asm.push_str(" mov rbx,rdi\n");
+ }
+ InlineAsmArch::AArch64 => {
+ generated_asm.push_str(" stp fp, lr, [sp, #-32]!\n");
+ generated_asm.push_str(" mov fp, sp\n");
+ generated_asm.push_str(" str x19, [sp, #24]\n"); // x19 is callee saved
+ // x19 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
+ generated_asm.push_str(" mov x19, x0\n");
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" addi sp, sp, -16\n");
generated_asm.push_str(" sd ra, 8(sp)\n");
- generated_asm.push_str(" sd s0, 0(sp)\n");
- generated_asm.push_str(" mv s0, a0\n");
+ generated_asm.push_str(" sd s1, 0(sp)\n"); // s1 is callee saved
+ // s1/x9 is reserved by LLVM for the "base pointer", so rustc doesn't allow using it
+ generated_asm.push_str(" mv s1, a0\n");
}
_ => unimplemented!("prologue for {:?}", arch),
}
@@ -725,22 +594,18 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
fn epilogue(generated_asm: &mut String, arch: InlineAsmArch) {
match arch {
- InlineAsmArch::X86 => {
- generated_asm.push_str(" pop ebp\n");
- generated_asm.push_str(" ret\n");
- }
InlineAsmArch::X86_64 => {
+ generated_asm.push_str(" pop rbx\n");
generated_asm.push_str(" pop rbp\n");
generated_asm.push_str(" ret\n");
}
- InlineAsmArch::RiscV32 => {
- generated_asm.push_str(" lw s0, 0(sp)\n");
- generated_asm.push_str(" lw ra, 4(sp)\n");
- generated_asm.push_str(" addi sp, sp, 8\n");
+ InlineAsmArch::AArch64 => {
+ generated_asm.push_str(" ldr x19, [sp, #24]\n");
+ generated_asm.push_str(" ldp fp, lr, [sp], #32\n");
generated_asm.push_str(" ret\n");
}
InlineAsmArch::RiscV64 => {
- generated_asm.push_str(" ld s0, 0(sp)\n");
+ generated_asm.push_str(" ld s1, 0(sp)\n");
generated_asm.push_str(" ld ra, 8(sp)\n");
generated_asm.push_str(" addi sp, sp, 16\n");
generated_asm.push_str(" ret\n");
@@ -751,10 +616,13 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
fn epilogue_noreturn(generated_asm: &mut String, arch: InlineAsmArch) {
match arch {
- InlineAsmArch::X86 | InlineAsmArch::X86_64 => {
+ InlineAsmArch::X86_64 => {
generated_asm.push_str(" ud2\n");
}
- InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {
+ InlineAsmArch::AArch64 => {
+ generated_asm.push_str(" brk #0x1\n");
+ }
+ InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ebreak\n");
}
_ => unimplemented!("epilogue_noreturn for {:?}", arch),
@@ -768,25 +636,20 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
offset: Size,
) {
match arch {
- InlineAsmArch::X86 => {
- write!(generated_asm, " mov [ebp+0x{:x}], ", offset.bytes()).unwrap();
- reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
- generated_asm.push('\n');
- }
InlineAsmArch::X86_64 => {
- write!(generated_asm, " mov [rbp+0x{:x}], ", offset.bytes()).unwrap();
+ write!(generated_asm, " mov [rbx+0x{:x}], ", offset.bytes()).unwrap();
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
generated_asm.push('\n');
}
- InlineAsmArch::RiscV32 => {
- generated_asm.push_str(" sw ");
- reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
- writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
+ InlineAsmArch::AArch64 => {
+ generated_asm.push_str(" str ");
+ reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();
+ writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" sd ");
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
- writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
+ writeln!(generated_asm, ", 0x{:x}(s1)", offset.bytes()).unwrap();
}
_ => unimplemented!("save_register for {:?}", arch),
}
@@ -799,25 +662,20 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
offset: Size,
) {
match arch {
- InlineAsmArch::X86 => {
- generated_asm.push_str(" mov ");
- reg.emit(generated_asm, InlineAsmArch::X86, None).unwrap();
- writeln!(generated_asm, ", [ebp+0x{:x}]", offset.bytes()).unwrap();
- }
InlineAsmArch::X86_64 => {
generated_asm.push_str(" mov ");
reg.emit(generated_asm, InlineAsmArch::X86_64, None).unwrap();
- writeln!(generated_asm, ", [rbp+0x{:x}]", offset.bytes()).unwrap();
+ writeln!(generated_asm, ", [rbx+0x{:x}]", offset.bytes()).unwrap();
}
- InlineAsmArch::RiscV32 => {
- generated_asm.push_str(" lw ");
- reg.emit(generated_asm, InlineAsmArch::RiscV32, None).unwrap();
- writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
+ InlineAsmArch::AArch64 => {
+ generated_asm.push_str(" ldr ");
+ reg.emit(generated_asm, InlineAsmArch::AArch64, None).unwrap();
+ writeln!(generated_asm, ", [x19, 0x{:x}]", offset.bytes()).unwrap();
}
InlineAsmArch::RiscV64 => {
generated_asm.push_str(" ld ");
reg.emit(generated_asm, InlineAsmArch::RiscV64, None).unwrap();
- writeln!(generated_asm, ", 0x{:x}(s0)", offset.bytes()).unwrap();
+ writeln!(generated_asm, ", 0x{:x}(s1)", offset.bytes()).unwrap();
}
_ => unimplemented!("restore_register for {:?}", arch),
}
@@ -831,13 +689,7 @@ fn call_inline_asm<'tcx>(
inputs: Vec<(Size, Value)>,
outputs: Vec<(Size, CPlace<'tcx>)>,
) {
- let stack_slot = fx.bcx.func.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- size: u32::try_from(slot_size.bytes()).unwrap(),
- });
- if fx.clif_comments.enabled() {
- fx.add_comment(stack_slot, "inline asm scratch slot");
- }
+ let stack_slot = fx.create_stack_slot(u32::try_from(slot_size.bytes()).unwrap(), 16);
let inline_asm_func = fx
.module
@@ -857,15 +709,103 @@ fn call_inline_asm<'tcx>(
}
for (offset, value) in inputs {
- fx.bcx.ins().stack_store(value, stack_slot, i32::try_from(offset.bytes()).unwrap());
+ stack_slot.offset(fx, i32::try_from(offset.bytes()).unwrap().into()).store(
+ fx,
+ value,
+ MemFlags::trusted(),
+ );
}
- let stack_slot_addr = fx.bcx.ins().stack_addr(fx.pointer_type, stack_slot, 0);
+ let stack_slot_addr = stack_slot.get_addr(fx);
fx.bcx.ins().call(inline_asm_func, &[stack_slot_addr]);
for (offset, place) in outputs {
let ty = fx.clif_type(place.layout().ty).unwrap();
- let value = fx.bcx.ins().stack_load(ty, stack_slot, i32::try_from(offset.bytes()).unwrap());
+ let value = stack_slot.offset(fx, i32::try_from(offset.bytes()).unwrap().into()).load(
+ fx,
+ ty,
+ MemFlags::trusted(),
+ );
place.write_cvalue(fx, CValue::by_val(value, place.layout()));
}
}
+
+pub(crate) fn codegen_xgetbv<'tcx>(
+ fx: &mut FunctionCx<'_, '_, 'tcx>,
+ xcr_no: Value,
+ ret: CPlace<'tcx>,
+) {
+ // FIXME add .eh_frame unwind info directives
+
+ let operands = vec![
+ CInlineAsmOperand::In {
+ reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::cx)),
+ value: xcr_no,
+ },
+ CInlineAsmOperand::Out {
+ reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::ax)),
+ late: true,
+ place: Some(ret),
+ },
+ CInlineAsmOperand::Out {
+ reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::dx)),
+ late: true,
+ place: None,
+ },
+ ];
+ let options = InlineAsmOptions::NOSTACK | InlineAsmOptions::PURE | InlineAsmOptions::NOMEM;
+
+ let mut inputs = Vec::new();
+ let mut outputs = Vec::new();
+
+ let mut asm_gen = InlineAssemblyGenerator {
+ tcx: fx.tcx,
+ arch: fx.tcx.sess.asm_arch.unwrap(),
+ enclosing_def_id: fx.instance.def_id(),
+ template: &[InlineAsmTemplatePiece::String(
+ "
+ xgetbv
+ // out = rdx << 32 | rax
+ shl rdx, 32
+ or rax, rdx
+ "
+ .to_string(),
+ )],
+ operands: &operands,
+ options,
+ registers: Vec::new(),
+ stack_slots_clobber: Vec::new(),
+ stack_slots_input: Vec::new(),
+ stack_slots_output: Vec::new(),
+ stack_slot_size: Size::from_bytes(0),
+ };
+ asm_gen.allocate_registers();
+ asm_gen.allocate_stack_slots();
+
+ let inline_asm_index = fx.cx.inline_asm_index.get();
+ fx.cx.inline_asm_index.set(inline_asm_index + 1);
+ let asm_name = format!(
+ "__inline_asm_{}_n{}",
+ fx.cx.cgu_name.as_str().replace('.', "__").replace('-', "_"),
+ inline_asm_index
+ );
+
+ let generated_asm = asm_gen.generate_asm_wrapper(&asm_name);
+ fx.cx.global_asm.push_str(&generated_asm);
+
+ for (i, operand) in operands.iter().enumerate() {
+ match operand {
+ CInlineAsmOperand::In { reg: _, value } => {
+ inputs.push((asm_gen.stack_slots_input[i].unwrap(), *value));
+ }
+ CInlineAsmOperand::Out { reg: _, late: _, place } => {
+ if let Some(place) = place {
+ outputs.push((asm_gen.stack_slots_output[i].unwrap(), *place));
+ }
+ }
+ _ => unreachable!(),
+ }
+ }
+
+ call_inline_asm(fx, &asm_name, asm_gen.stack_slot_size, inputs, outputs);
+}
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/cpuid.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/cpuid.rs
deleted file mode 100644
index 5120b89c4..000000000
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/cpuid.rs
+++ /dev/null
@@ -1,74 +0,0 @@
-//! Emulation of a subset of the cpuid x86 instruction.
-
-use crate::prelude::*;
-
-/// Emulates a subset of the cpuid x86 instruction.
-///
-/// This emulates an intel cpu with sse and sse2 support, but which doesn't support anything else.
-pub(crate) fn codegen_cpuid_call<'tcx>(
- fx: &mut FunctionCx<'_, '_, 'tcx>,
- leaf: Value,
- _sub_leaf: Value,
-) -> (Value, Value, Value, Value) {
- let leaf_0 = fx.bcx.create_block();
- let leaf_1 = fx.bcx.create_block();
- let leaf_7 = fx.bcx.create_block();
- let leaf_8000_0000 = fx.bcx.create_block();
- let leaf_8000_0001 = fx.bcx.create_block();
- let unsupported_leaf = fx.bcx.create_block();
-
- let dest = fx.bcx.create_block();
- let eax = fx.bcx.append_block_param(dest, types::I32);
- let ebx = fx.bcx.append_block_param(dest, types::I32);
- let ecx = fx.bcx.append_block_param(dest, types::I32);
- let edx = fx.bcx.append_block_param(dest, types::I32);
-
- let mut switch = cranelift_frontend::Switch::new();
- switch.set_entry(0, leaf_0);
- switch.set_entry(1, leaf_1);
- switch.set_entry(7, leaf_7);
- switch.set_entry(0x8000_0000, leaf_8000_0000);
- switch.set_entry(0x8000_0001, leaf_8000_0001);
- switch.emit(&mut fx.bcx, leaf, unsupported_leaf);
-
- fx.bcx.switch_to_block(leaf_0);
- let max_basic_leaf = fx.bcx.ins().iconst(types::I32, 1);
- let vend0 = fx.bcx.ins().iconst(types::I32, i64::from(u32::from_le_bytes(*b"Genu")));
- let vend2 = fx.bcx.ins().iconst(types::I32, i64::from(u32::from_le_bytes(*b"ineI")));
- let vend1 = fx.bcx.ins().iconst(types::I32, i64::from(u32::from_le_bytes(*b"ntel")));
- fx.bcx.ins().jump(dest, &[max_basic_leaf, vend0, vend1, vend2]);
-
- fx.bcx.switch_to_block(leaf_1);
- let cpu_signature = fx.bcx.ins().iconst(types::I32, 0);
- let additional_information = fx.bcx.ins().iconst(types::I32, 0);
- let ecx_features = fx.bcx.ins().iconst(types::I32, 0);
- let edx_features = fx.bcx.ins().iconst(types::I32, 1 << 25 /* sse */ | 1 << 26 /* sse2 */);
- fx.bcx.ins().jump(dest, &[cpu_signature, additional_information, ecx_features, edx_features]);
-
- fx.bcx.switch_to_block(leaf_7);
- // This leaf technically has subleaves, but we just return zero for all subleaves.
- let zero = fx.bcx.ins().iconst(types::I32, 0);
- fx.bcx.ins().jump(dest, &[zero, zero, zero, zero]);
-
- fx.bcx.switch_to_block(leaf_8000_0000);
- let extended_max_basic_leaf = fx.bcx.ins().iconst(types::I32, 0);
- let zero = fx.bcx.ins().iconst(types::I32, 0);
- fx.bcx.ins().jump(dest, &[extended_max_basic_leaf, zero, zero, zero]);
-
- fx.bcx.switch_to_block(leaf_8000_0001);
- let zero = fx.bcx.ins().iconst(types::I32, 0);
- let proc_info_ecx = fx.bcx.ins().iconst(types::I32, 0);
- let proc_info_edx = fx.bcx.ins().iconst(types::I32, 0);
- fx.bcx.ins().jump(dest, &[zero, zero, proc_info_ecx, proc_info_edx]);
-
- fx.bcx.switch_to_block(unsupported_leaf);
- crate::trap::trap_unimplemented(
- fx,
- "__cpuid_count arch intrinsic doesn't yet support specified leaf",
- );
-
- fx.bcx.switch_to_block(dest);
- fx.bcx.ins().nop();
-
- (eax, ebx, ecx, edx)
-}
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs
index 63b5402f2..e9b7daf14 100644
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs
+++ b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm.rs
@@ -1,10 +1,10 @@
//! Emulate LLVM intrinsics
+use rustc_middle::ty::GenericArgsRef;
+
use crate::intrinsics::*;
use crate::prelude::*;
-use rustc_middle::ty::GenericArgsRef;
-
pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
fx: &mut FunctionCx<'_, '_, 'tcx>,
intrinsic: &str,
@@ -51,6 +51,21 @@ pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
});
}
+ _ if intrinsic.starts_with("llvm.fma.v") => {
+ intrinsic_args!(fx, args => (x,y,z); intrinsic);
+
+ simd_trio_for_each_lane(
+ fx,
+ x,
+ y,
+ z,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, lane_x, lane_y, lane_z| {
+ fx.bcx.ins().fma(lane_x, lane_y, lane_z)
+ },
+ );
+ }
+
_ => {
fx.tcx
.sess
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_aarch64.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_aarch64.rs
index c20a99159..ee098be1f 100644
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_aarch64.rs
+++ b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_aarch64.rs
@@ -1,10 +1,10 @@
//! Emulate AArch64 LLVM intrinsics
+use rustc_middle::ty::GenericArgsRef;
+
use crate::intrinsics::*;
use crate::prelude::*;
-use rustc_middle::ty::GenericArgsRef;
-
pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
fx: &mut FunctionCx<'_, '_, 'tcx>,
intrinsic: &str,
@@ -44,7 +44,9 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
});
}
- _ if intrinsic.starts_with("llvm.aarch64.neon.sqadd.v") => {
+ _ if intrinsic.starts_with("llvm.aarch64.neon.sqadd.v")
+ || intrinsic.starts_with("llvm.aarch64.neon.uqadd.v") =>
+ {
intrinsic_args!(fx, args => (x, y); intrinsic);
simd_pair_for_each_lane_typed(fx, x, y, ret, &|fx, x_lane, y_lane| {
@@ -52,7 +54,9 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
});
}
- _ if intrinsic.starts_with("llvm.aarch64.neon.sqsub.v") => {
+ _ if intrinsic.starts_with("llvm.aarch64.neon.sqsub.v")
+ || intrinsic.starts_with("llvm.aarch64.neon.uqsub.v") =>
+ {
intrinsic_args!(fx, args => (x, y); intrinsic);
simd_pair_for_each_lane_typed(fx, x, y, ret, &|fx, x_lane, y_lane| {
@@ -156,6 +160,106 @@ pub(crate) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
});
}
+ _ if intrinsic.starts_with("llvm.aarch64.neon.umaxp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().umax(x_lane, y_lane),
+ );
+ }
+
+ _ if intrinsic.starts_with("llvm.aarch64.neon.smaxp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().smax(x_lane, y_lane),
+ );
+ }
+
+ _ if intrinsic.starts_with("llvm.aarch64.neon.uminp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().umin(x_lane, y_lane),
+ );
+ }
+
+ _ if intrinsic.starts_with("llvm.aarch64.neon.sminp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().smin(x_lane, y_lane),
+ );
+ }
+
+ _ if intrinsic.starts_with("llvm.aarch64.neon.fminp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().fmin(x_lane, y_lane),
+ );
+ }
+
+ _ if intrinsic.starts_with("llvm.aarch64.neon.fmaxp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().fmax(x_lane, y_lane),
+ );
+ }
+
+ _ if intrinsic.starts_with("llvm.aarch64.neon.addp.v") => {
+ intrinsic_args!(fx, args => (x, y); intrinsic);
+
+ simd_horizontal_pair_for_each_lane(
+ fx,
+ x,
+ y,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, x_lane, y_lane| fx.bcx.ins().iadd(x_lane, y_lane),
+ );
+ }
+
+ // FIXME generalize vector types
+ "llvm.aarch64.neon.tbl1.v16i8" => {
+ intrinsic_args!(fx, args => (t, idx); intrinsic);
+
+ let zero = fx.bcx.ins().iconst(types::I8, 0);
+ for i in 0..16 {
+ let idx_lane = idx.value_lane(fx, i).load_scalar(fx);
+ let is_zero =
+ fx.bcx.ins().icmp_imm(IntCC::UnsignedGreaterThanOrEqual, idx_lane, 16);
+ let t_idx = fx.bcx.ins().uextend(fx.pointer_type, idx_lane);
+ let t_lane = t.value_lane_dyn(fx, t_idx).load_scalar(fx);
+ let res = fx.bcx.ins().select(is_zero, zero, t_lane);
+ ret.place_lane(fx, i).to_ptr().store(fx, res, MemFlags::trusted());
+ }
+ }
+
/*
_ if intrinsic.starts_with("llvm.aarch64.neon.sshl.v")
|| intrinsic.starts_with("llvm.aarch64.neon.sqshl.v")
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_x86.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_x86.rs
index e62de6b61..4c5360486 100644
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_x86.rs
+++ b/compiler/rustc_codegen_cranelift/src/intrinsics/llvm_x86.rs
@@ -1,10 +1,10 @@
//! Emulate x86 LLVM intrinsics
+use rustc_middle::ty::GenericArgsRef;
+
use crate::intrinsics::*;
use crate::prelude::*;
-use rustc_middle::ty::GenericArgsRef;
-
pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
fx: &mut FunctionCx<'_, '_, 'tcx>,
intrinsic: &str,
@@ -20,53 +20,23 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
// Used by is_x86_feature_detected!();
"llvm.x86.xgetbv" => {
- // FIXME use the actual xgetbv instruction
- intrinsic_args!(fx, args => (v); intrinsic);
-
- let v = v.load_scalar(fx);
+ intrinsic_args!(fx, args => (xcr_no); intrinsic);
- // As of writing on XCR0 exists
- fx.bcx.ins().trapnz(v, TrapCode::UnreachableCodeReached);
+ let xcr_no = xcr_no.load_scalar(fx);
- let res = fx.bcx.ins().iconst(types::I64, 1 /* bit 0 must be set */);
- ret.write_cvalue(fx, CValue::by_val(res, fx.layout_of(fx.tcx.types.i64)));
+ crate::inline_asm::codegen_xgetbv(fx, xcr_no, ret);
}
- // Used by `_mm_movemask_epi8` and `_mm256_movemask_epi8`
- "llvm.x86.sse2.pmovmskb.128"
- | "llvm.x86.avx2.pmovmskb"
- | "llvm.x86.sse.movmsk.ps"
- | "llvm.x86.sse2.movmsk.pd" => {
- intrinsic_args!(fx, args => (a); intrinsic);
-
- let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);
- let lane_ty = fx.clif_type(lane_ty).unwrap();
- assert!(lane_count <= 32);
-
- let mut res = fx.bcx.ins().iconst(types::I32, 0);
-
- for lane in (0..lane_count).rev() {
- let a_lane = a.value_lane(fx, lane).load_scalar(fx);
+ "llvm.x86.sse3.ldu.dq" | "llvm.x86.avx.ldu.dq.256" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lddqu_si128&ig_expand=4009
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_lddqu_si256&ig_expand=4010
+ intrinsic_args!(fx, args => (ptr); intrinsic);
- // cast float to int
- let a_lane = match lane_ty {
- types::F32 => codegen_bitcast(fx, types::I32, a_lane),
- types::F64 => codegen_bitcast(fx, types::I64, a_lane),
- _ => a_lane,
- };
-
- // extract sign bit of an int
- let a_lane_sign = fx.bcx.ins().ushr_imm(a_lane, i64::from(lane_ty.bits() - 1));
-
- // shift sign bit into result
- let a_lane_sign = clif_intcast(fx, a_lane_sign, types::I32, false);
- res = fx.bcx.ins().ishl_imm(res, 1);
- res = fx.bcx.ins().bor(res, a_lane_sign);
- }
-
- let res = CValue::by_val(res, fx.layout_of(fx.tcx.types.i32));
- ret.write_cvalue(fx, res);
+ // FIXME correctly handle unalignedness
+ let val = CValue::by_ref(Pointer::new(ptr.load_scalar(fx)), ret.layout());
+ ret.write_cvalue(fx, val);
}
+
"llvm.x86.sse.cmp.ps" | "llvm.x86.sse2.cmp.pd" => {
let (x, y, kind) = match args {
[x, y, kind] => (x, y, kind),
@@ -74,8 +44,10 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
};
let x = codegen_operand(fx, x);
let y = codegen_operand(fx, y);
- let kind = crate::constant::mir_operand_get_const_val(fx, kind)
- .expect("llvm.x86.sse2.cmp.* kind not const");
+ let kind = match kind {
+ Operand::Constant(const_) => crate::constant::eval_mir_constant(fx, const_).0,
+ Operand::Copy(_) | Operand::Move(_) => unreachable!("{kind:?}"),
+ };
let flt_cc = match kind
.try_to_bits(Size::from_bytes(1))
@@ -210,8 +182,12 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
}
}
}
- "llvm.x86.avx2.vperm2i128" => {
+ "llvm.x86.avx2.vperm2i128"
+ | "llvm.x86.avx.vperm2f128.ps.256"
+ | "llvm.x86.avx.vperm2f128.pd.256" => {
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permute2x128_si256
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permute2f128_ps
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_permute2f128_pd
let (a, b, imm8) = match args {
[a, b, imm8] => (a, b, imm8),
_ => bug!("wrong number of args for intrinsic {intrinsic}"),
@@ -220,19 +196,11 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
let b = codegen_operand(fx, b);
let imm8 = codegen_operand(fx, imm8).load_scalar(fx);
- let a_0 = a.value_lane(fx, 0).load_scalar(fx);
- let a_1 = a.value_lane(fx, 1).load_scalar(fx);
- let a_low = fx.bcx.ins().iconcat(a_0, a_1);
- let a_2 = a.value_lane(fx, 2).load_scalar(fx);
- let a_3 = a.value_lane(fx, 3).load_scalar(fx);
- let a_high = fx.bcx.ins().iconcat(a_2, a_3);
+ let a_low = a.value_typed_lane(fx, fx.tcx.types.u128, 0).load_scalar(fx);
+ let a_high = a.value_typed_lane(fx, fx.tcx.types.u128, 1).load_scalar(fx);
- let b_0 = b.value_lane(fx, 0).load_scalar(fx);
- let b_1 = b.value_lane(fx, 1).load_scalar(fx);
- let b_low = fx.bcx.ins().iconcat(b_0, b_1);
- let b_2 = b.value_lane(fx, 2).load_scalar(fx);
- let b_3 = b.value_lane(fx, 3).load_scalar(fx);
- let b_high = fx.bcx.ins().iconcat(b_2, b_3);
+ let b_low = b.value_typed_lane(fx, fx.tcx.types.u128, 0).load_scalar(fx);
+ let b_high = b.value_typed_lane(fx, fx.tcx.types.u128, 1).load_scalar(fx);
fn select4(
fx: &mut FunctionCx<'_, '_, '_>,
@@ -257,16 +225,20 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
let control0 = imm8;
let res_low = select4(fx, a_high, a_low, b_high, b_low, control0);
- let (res_0, res_1) = fx.bcx.ins().isplit(res_low);
let control1 = fx.bcx.ins().ushr_imm(imm8, 4);
let res_high = select4(fx, a_high, a_low, b_high, b_low, control1);
- let (res_2, res_3) = fx.bcx.ins().isplit(res_high);
- ret.place_lane(fx, 0).to_ptr().store(fx, res_0, MemFlags::trusted());
- ret.place_lane(fx, 1).to_ptr().store(fx, res_1, MemFlags::trusted());
- ret.place_lane(fx, 2).to_ptr().store(fx, res_2, MemFlags::trusted());
- ret.place_lane(fx, 3).to_ptr().store(fx, res_3, MemFlags::trusted());
+ ret.place_typed_lane(fx, fx.tcx.types.u128, 0).to_ptr().store(
+ fx,
+ res_low,
+ MemFlags::trusted(),
+ );
+ ret.place_typed_lane(fx, fx.tcx.types.u128, 1).to_ptr().store(
+ fx,
+ res_high,
+ MemFlags::trusted(),
+ );
}
"llvm.x86.ssse3.pabs.b.128" | "llvm.x86.ssse3.pabs.w.128" | "llvm.x86.ssse3.pabs.d.128" => {
let a = match args {
@@ -308,6 +280,512 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
let val = CValue::by_val_pair(cb_out, c, layout);
ret.write_cvalue(fx, val);
}
+ "llvm.x86.sse2.pavg.b" | "llvm.x86.sse2.pavg.w" => {
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ // FIXME use vector instructions when possible
+ simd_pair_for_each_lane(
+ fx,
+ a,
+ b,
+ ret,
+ &|fx, _lane_ty, _res_lane_ty, a_lane, b_lane| {
+ // (a + b + 1) >> 1
+ let lane_ty = fx.bcx.func.dfg.value_type(a_lane);
+ let a_lane = fx.bcx.ins().uextend(lane_ty.double_width().unwrap(), a_lane);
+ let b_lane = fx.bcx.ins().uextend(lane_ty.double_width().unwrap(), b_lane);
+ let sum = fx.bcx.ins().iadd(a_lane, b_lane);
+ let num_plus_one = fx.bcx.ins().iadd_imm(sum, 1);
+ let res = fx.bcx.ins().ushr_imm(num_plus_one, 1);
+ fx.bcx.ins().ireduce(lane_ty, res)
+ },
+ );
+ }
+ "llvm.x86.sse2.psra.w" => {
+ intrinsic_args!(fx, args => (a, count); intrinsic);
+
+ let count_lane = count.force_stack(fx).0.load(fx, types::I64, MemFlags::trusted());
+ let lane_ty = fx.clif_type(a.layout().ty.simd_size_and_type(fx.tcx).1).unwrap();
+ let max_count = fx.bcx.ins().iconst(types::I64, i64::from(lane_ty.bits() - 1));
+ let saturated_count = fx.bcx.ins().umin(count_lane, max_count);
+
+ // FIXME use vector instructions when possible
+ simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, a_lane| {
+ fx.bcx.ins().sshr(a_lane, saturated_count)
+ });
+ }
+ "llvm.x86.sse2.psad.bw" | "llvm.x86.avx2.psad.bw" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sad_epu8&ig_expand=5770
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_sad_epu8&ig_expand=5771
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.u8);
+ assert_eq!(ret_lane_ty, fx.tcx.types.u64);
+ assert_eq!(lane_count, ret_lane_count * 8);
+
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.u64);
+ for out_lane_idx in 0..lane_count / 8 {
+ let mut lane_diff_acc = fx.bcx.ins().iconst(types::I64, 0);
+
+ for lane_idx in out_lane_idx * 8..out_lane_idx * 8 + 1 {
+ let a_lane = a.value_lane(fx, lane_idx).load_scalar(fx);
+ let b_lane = b.value_lane(fx, lane_idx).load_scalar(fx);
+
+ let lane_diff = fx.bcx.ins().isub(a_lane, b_lane);
+ let abs_lane_diff = fx.bcx.ins().iabs(lane_diff);
+ let abs_lane_diff = fx.bcx.ins().uextend(types::I64, abs_lane_diff);
+ lane_diff_acc = fx.bcx.ins().iadd(lane_diff_acc, abs_lane_diff);
+ }
+
+ let res_lane = CValue::by_val(lane_diff_acc, ret_lane_layout);
+
+ ret.place_lane(fx, out_lane_idx).write_cvalue(fx, res_lane);
+ }
+ }
+ "llvm.x86.ssse3.pmadd.ub.sw.128" | "llvm.x86.avx2.pmadd.ub.sw" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maddubs_epi16&ig_expand=4267
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maddubs_epi16&ig_expand=4270
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ let (lane_count, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.u8);
+ assert_eq!(ret_lane_ty, fx.tcx.types.i16);
+ assert_eq!(lane_count, ret_lane_count * 2);
+
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.i16);
+ for out_lane_idx in 0..lane_count / 2 {
+ let a_lane0 = a.value_lane(fx, out_lane_idx * 2).load_scalar(fx);
+ let a_lane0 = fx.bcx.ins().uextend(types::I16, a_lane0);
+ let b_lane0 = b.value_lane(fx, out_lane_idx * 2).load_scalar(fx);
+ let b_lane0 = fx.bcx.ins().sextend(types::I16, b_lane0);
+
+ let a_lane1 = a.value_lane(fx, out_lane_idx * 2 + 1).load_scalar(fx);
+ let a_lane1 = fx.bcx.ins().uextend(types::I16, a_lane1);
+ let b_lane1 = b.value_lane(fx, out_lane_idx * 2 + 1).load_scalar(fx);
+ let b_lane1 = fx.bcx.ins().sextend(types::I16, b_lane1);
+
+ let mul0: Value = fx.bcx.ins().imul(a_lane0, b_lane0);
+ let mul1 = fx.bcx.ins().imul(a_lane1, b_lane1);
+
+ let (val, has_overflow) = fx.bcx.ins().sadd_overflow(mul0, mul1);
+
+ let rhs_ge_zero = fx.bcx.ins().icmp_imm(IntCC::SignedGreaterThanOrEqual, mul1, 0);
+
+ let min = fx.bcx.ins().iconst(types::I16, i64::from(i16::MIN as u16));
+ let max = fx.bcx.ins().iconst(types::I16, i64::from(i16::MAX as u16));
+
+ let sat_val = fx.bcx.ins().select(rhs_ge_zero, max, min);
+ let res_lane = fx.bcx.ins().select(has_overflow, sat_val, val);
+
+ let res_lane = CValue::by_val(res_lane, ret_lane_layout);
+
+ ret.place_lane(fx, out_lane_idx).write_cvalue(fx, res_lane);
+ }
+ }
+ "llvm.x86.sse2.pmadd.wd" | "llvm.x86.avx2.pmadd.wd" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_madd_epi16&ig_expand=4231
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_madd_epi16&ig_expand=4234
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i16);
+ assert_eq!(ret_lane_ty, fx.tcx.types.i32);
+ assert_eq!(lane_count, ret_lane_count * 2);
+
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.i32);
+ for out_lane_idx in 0..lane_count / 2 {
+ let a_lane0 = a.value_lane(fx, out_lane_idx * 2).load_scalar(fx);
+ let a_lane0 = fx.bcx.ins().uextend(types::I32, a_lane0);
+ let b_lane0 = b.value_lane(fx, out_lane_idx * 2).load_scalar(fx);
+ let b_lane0 = fx.bcx.ins().sextend(types::I32, b_lane0);
+
+ let a_lane1 = a.value_lane(fx, out_lane_idx * 2 + 1).load_scalar(fx);
+ let a_lane1 = fx.bcx.ins().uextend(types::I32, a_lane1);
+ let b_lane1 = b.value_lane(fx, out_lane_idx * 2 + 1).load_scalar(fx);
+ let b_lane1 = fx.bcx.ins().sextend(types::I32, b_lane1);
+
+ let mul0: Value = fx.bcx.ins().imul(a_lane0, b_lane0);
+ let mul1 = fx.bcx.ins().imul(a_lane1, b_lane1);
+
+ let res_lane = fx.bcx.ins().iadd(mul0, mul1);
+ let res_lane = CValue::by_val(res_lane, ret_lane_layout);
+
+ ret.place_lane(fx, out_lane_idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.ssse3.pmul.hr.sw.128" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mulhrs_epi16&ig_expand=4782
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i16);
+ assert_eq!(ret_lane_ty, fx.tcx.types.i16);
+ assert_eq!(lane_count, ret_lane_count);
+
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.i16);
+ for out_lane_idx in 0..lane_count {
+ let a_lane = a.value_lane(fx, out_lane_idx).load_scalar(fx);
+ let a_lane = fx.bcx.ins().sextend(types::I32, a_lane);
+ let b_lane = b.value_lane(fx, out_lane_idx).load_scalar(fx);
+ let b_lane = fx.bcx.ins().sextend(types::I32, b_lane);
+
+ let mul: Value = fx.bcx.ins().imul(a_lane, b_lane);
+ let shifted = fx.bcx.ins().ushr_imm(mul, 14);
+ let incremented = fx.bcx.ins().iadd_imm(shifted, 1);
+ let shifted_again = fx.bcx.ins().ushr_imm(incremented, 1);
+
+ let res_lane = fx.bcx.ins().ireduce(types::I16, shifted_again);
+ let res_lane = CValue::by_val(res_lane, ret_lane_layout);
+
+ ret.place_lane(fx, out_lane_idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.sse2.packuswb.128" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16&ig_expand=4903
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i16);
+ assert_eq!(ret_lane_ty, fx.tcx.types.u8);
+ assert_eq!(lane_count * 2, ret_lane_count);
+
+ let zero = fx.bcx.ins().iconst(types::I16, 0);
+ let max_u8 = fx.bcx.ins().iconst(types::I16, 255);
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.u8);
+
+ for idx in 0..lane_count {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, zero);
+ let sat = fx.bcx.ins().umin(sat, max_u8);
+ let res = fx.bcx.ins().ireduce(types::I8, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, zero);
+ let sat = fx.bcx.ins().umin(sat, max_u8);
+ let res = fx.bcx.ins().ireduce(types::I8, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count + idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.avx2.packuswb" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packus_epi16&ig_expand=4906
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i16);
+ assert_eq!(ret_lane_ty, fx.tcx.types.u8);
+ assert_eq!(lane_count * 2, ret_lane_count);
+
+ let zero = fx.bcx.ins().iconst(types::I16, 0);
+ let max_u8 = fx.bcx.ins().iconst(types::I16, 255);
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.u8);
+
+ for idx in 0..lane_count / 2 {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, zero);
+ let sat = fx.bcx.ins().umin(sat, max_u8);
+ let res = fx.bcx.ins().ireduce(types::I8, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count / 2 {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, zero);
+ let sat = fx.bcx.ins().umin(sat, max_u8);
+ let res = fx.bcx.ins().ireduce(types::I8, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count / 2 + idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count / 2 {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, zero);
+ let sat = fx.bcx.ins().umin(sat, max_u8);
+ let res = fx.bcx.ins().ireduce(types::I8, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count / 2 * 2 + idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count / 2 {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, zero);
+ let sat = fx.bcx.ins().umin(sat, max_u8);
+ let res = fx.bcx.ins().ireduce(types::I8, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count / 2 * 3 + idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.sse2.packssdw.128" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32&ig_expand=4889
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i32);
+ assert_eq!(ret_lane_ty, fx.tcx.types.i16);
+ assert_eq!(lane_count * 2, ret_lane_count);
+
+ let min_i16 = fx.bcx.ins().iconst(types::I32, i64::from(i16::MIN as u16));
+ let max_i16 = fx.bcx.ins().iconst(types::I32, i64::from(i16::MAX as u16));
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.i16);
+
+ for idx in 0..lane_count {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, min_i16);
+ let sat = fx.bcx.ins().umin(sat, max_i16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, min_i16);
+ let sat = fx.bcx.ins().umin(sat, max_i16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count + idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.sse41.packusdw" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi32&ig_expand=4912
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i32);
+ assert_eq!(ret_lane_ty, fx.tcx.types.u16);
+ assert_eq!(lane_count * 2, ret_lane_count);
+
+ let min_u16 = fx.bcx.ins().iconst(types::I32, i64::from(u16::MIN));
+ let max_u16 = fx.bcx.ins().iconst(types::I32, i64::from(u16::MAX));
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.u16);
+
+ for idx in 0..lane_count {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().umax(lane, min_u16);
+ let sat = fx.bcx.ins().umin(sat, max_u16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().umax(lane, min_u16);
+ let sat = fx.bcx.ins().umin(sat, max_u16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count + idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.avx2.packssdw" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_packs_epi32&ig_expand=4892
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i32);
+ assert_eq!(ret_lane_ty, fx.tcx.types.i16);
+ assert_eq!(lane_count * 2, ret_lane_count);
+
+ let min_i16 = fx.bcx.ins().iconst(types::I32, i64::from(i16::MIN as u16));
+ let max_i16 = fx.bcx.ins().iconst(types::I32, i64::from(i16::MAX as u16));
+ let ret_lane_layout = fx.layout_of(fx.tcx.types.i16);
+
+ for idx in 0..lane_count / 2 {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, min_i16);
+ let sat = fx.bcx.ins().umin(sat, max_i16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count / 2 {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, min_i16);
+ let sat = fx.bcx.ins().umin(sat, max_i16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count / 2 + idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count / 2 {
+ let lane = a.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, min_i16);
+ let sat = fx.bcx.ins().umin(sat, max_i16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count / 2 * 2 + idx).write_cvalue(fx, res_lane);
+ }
+
+ for idx in 0..lane_count / 2 {
+ let lane = b.value_lane(fx, idx).load_scalar(fx);
+ let sat = fx.bcx.ins().smax(lane, min_i16);
+ let sat = fx.bcx.ins().umin(sat, max_i16);
+ let res = fx.bcx.ins().ireduce(types::I16, sat);
+
+ let res_lane = CValue::by_val(res, ret_lane_layout);
+ ret.place_lane(fx, lane_count / 2 * 3 + idx).write_cvalue(fx, res_lane);
+ }
+ }
+
+ "llvm.x86.pclmulqdq" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_clmulepi64_si128&ig_expand=772
+ intrinsic_args!(fx, args => (a, b, imm8); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i64);
+ assert_eq!(ret_lane_ty, fx.tcx.types.i64);
+ assert_eq!(lane_count, 2);
+ assert_eq!(ret_lane_count, 2);
+
+ let imm8 = imm8.load_scalar(fx);
+
+ let control0 = fx.bcx.ins().band_imm(imm8, 0b0000_0001);
+ let a_lane0 = a.value_lane(fx, 0).load_scalar(fx);
+ let a_lane1 = a.value_lane(fx, 1).load_scalar(fx);
+ let temp1 = fx.bcx.ins().select(control0, a_lane1, a_lane0);
+
+ let control4 = fx.bcx.ins().band_imm(imm8, 0b0001_0000);
+ let b_lane0 = b.value_lane(fx, 0).load_scalar(fx);
+ let b_lane1 = b.value_lane(fx, 1).load_scalar(fx);
+ let temp2 = fx.bcx.ins().select(control4, b_lane1, b_lane0);
+
+ fn extract_bit(fx: &mut FunctionCx<'_, '_, '_>, val: Value, bit: i64) -> Value {
+ let tmp = fx.bcx.ins().ushr_imm(val, bit);
+ fx.bcx.ins().band_imm(tmp, 1)
+ }
+
+ let mut res1 = fx.bcx.ins().iconst(types::I64, 0);
+ for i in 0..=63 {
+ let x = extract_bit(fx, temp1, 0);
+ let y = extract_bit(fx, temp2, i);
+ let mut temp = fx.bcx.ins().band(x, y);
+ for j in 1..=i {
+ let x = extract_bit(fx, temp1, j);
+ let y = extract_bit(fx, temp2, i - j);
+ let z = fx.bcx.ins().band(x, y);
+ temp = fx.bcx.ins().bxor(temp, z);
+ }
+ let temp = fx.bcx.ins().ishl_imm(temp, i);
+ res1 = fx.bcx.ins().bor(res1, temp);
+ }
+ ret.place_lane(fx, 0).to_ptr().store(fx, res1, MemFlags::trusted());
+
+ let mut res2 = fx.bcx.ins().iconst(types::I64, 0);
+ for i in 64..=127 {
+ let mut temp = fx.bcx.ins().iconst(types::I64, 0);
+ for j in i - 63..=63 {
+ let x = extract_bit(fx, temp1, j);
+ let y = extract_bit(fx, temp2, i - j);
+ let z = fx.bcx.ins().band(x, y);
+ temp = fx.bcx.ins().bxor(temp, z);
+ }
+ let temp = fx.bcx.ins().ishl_imm(temp, i);
+ res2 = fx.bcx.ins().bor(res2, temp);
+ }
+ ret.place_lane(fx, 1).to_ptr().store(fx, res2, MemFlags::trusted());
+ }
+
+ "llvm.x86.avx.ptestz.256" => {
+ // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testz_si256&ig_expand=6945
+ intrinsic_args!(fx, args => (a, b); intrinsic);
+
+ assert_eq!(a.layout(), b.layout());
+ let layout = a.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ assert_eq!(lane_ty, fx.tcx.types.i64);
+ assert_eq!(ret.layout().ty, fx.tcx.types.i32);
+ assert_eq!(lane_count, 4);
+
+ let a_lane0 = a.value_lane(fx, 0).load_scalar(fx);
+ let a_lane1 = a.value_lane(fx, 1).load_scalar(fx);
+ let a_lane2 = a.value_lane(fx, 2).load_scalar(fx);
+ let a_lane3 = a.value_lane(fx, 3).load_scalar(fx);
+ let b_lane0 = b.value_lane(fx, 0).load_scalar(fx);
+ let b_lane1 = b.value_lane(fx, 1).load_scalar(fx);
+ let b_lane2 = b.value_lane(fx, 2).load_scalar(fx);
+ let b_lane3 = b.value_lane(fx, 3).load_scalar(fx);
+
+ let zero0 = fx.bcx.ins().band(a_lane0, b_lane0);
+ let zero1 = fx.bcx.ins().band(a_lane1, b_lane1);
+ let zero2 = fx.bcx.ins().band(a_lane2, b_lane2);
+ let zero3 = fx.bcx.ins().band(a_lane3, b_lane3);
+
+ let all_zero0 = fx.bcx.ins().bor(zero0, zero1);
+ let all_zero1 = fx.bcx.ins().bor(zero2, zero3);
+ let all_zero = fx.bcx.ins().bor(all_zero0, all_zero1);
+
+ let res = fx.bcx.ins().icmp_imm(IntCC::Equal, all_zero, 0);
+ let res = CValue::by_val(
+ fx.bcx.ins().uextend(types::I32, res),
+ fx.layout_of(fx.tcx.types.i32),
+ );
+ ret.write_cvalue(fx, res);
+ }
+
_ => {
fx.tcx
.sess
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs
index 36e9ba9c7..bfeeb117f 100644
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs
+++ b/compiler/rustc_codegen_cranelift/src/intrinsics/mod.rs
@@ -12,23 +12,20 @@ macro_rules! intrinsic_args {
}
}
-mod cpuid;
mod llvm;
mod llvm_aarch64;
mod llvm_x86;
mod simd;
-pub(crate) use cpuid::codegen_cpuid_call;
-pub(crate) use llvm::codegen_llvm_intrinsic_call;
-
+use cranelift_codegen::ir::AtomicRmwOp;
use rustc_middle::ty;
use rustc_middle::ty::layout::{HasParamEnv, ValidityRequirement};
use rustc_middle::ty::print::{with_no_trimmed_paths, with_no_visible_paths};
use rustc_middle::ty::GenericArgsRef;
use rustc_span::symbol::{kw, sym, Symbol};
+pub(crate) use self::llvm::codegen_llvm_intrinsic_call;
use crate::prelude::*;
-use cranelift_codegen::ir::AtomicRmwOp;
fn bug_on_incorrect_arg_count(intrinsic: impl std::fmt::Display) -> ! {
bug!("wrong number of args for intrinsic {}", intrinsic);
@@ -135,6 +132,65 @@ fn simd_pair_for_each_lane<'tcx>(
}
}
+fn simd_horizontal_pair_for_each_lane<'tcx>(
+ fx: &mut FunctionCx<'_, '_, 'tcx>,
+ x: CValue<'tcx>,
+ y: CValue<'tcx>,
+ ret: CPlace<'tcx>,
+ f: &dyn Fn(&mut FunctionCx<'_, '_, 'tcx>, Ty<'tcx>, Ty<'tcx>, Value, Value) -> Value,
+) {
+ assert_eq!(x.layout(), y.layout());
+ let layout = x.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let lane_layout = fx.layout_of(lane_ty);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ let ret_lane_layout = fx.layout_of(ret_lane_ty);
+ assert_eq!(lane_count, ret_lane_count);
+
+ for lane_idx in 0..lane_count {
+ let src = if lane_idx < (lane_count / 2) { x } else { y };
+ let src_idx = lane_idx % (lane_count / 2);
+
+ let lhs_lane = src.value_lane(fx, src_idx * 2).load_scalar(fx);
+ let rhs_lane = src.value_lane(fx, src_idx * 2 + 1).load_scalar(fx);
+
+ let res_lane = f(fx, lane_layout.ty, ret_lane_layout.ty, lhs_lane, rhs_lane);
+ let res_lane = CValue::by_val(res_lane, ret_lane_layout);
+
+ ret.place_lane(fx, lane_idx).write_cvalue(fx, res_lane);
+ }
+}
+
+fn simd_trio_for_each_lane<'tcx>(
+ fx: &mut FunctionCx<'_, '_, 'tcx>,
+ x: CValue<'tcx>,
+ y: CValue<'tcx>,
+ z: CValue<'tcx>,
+ ret: CPlace<'tcx>,
+ f: &dyn Fn(&mut FunctionCx<'_, '_, 'tcx>, Ty<'tcx>, Ty<'tcx>, Value, Value, Value) -> Value,
+) {
+ assert_eq!(x.layout(), y.layout());
+ let layout = x.layout();
+
+ let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let lane_layout = fx.layout_of(lane_ty);
+ let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
+ let ret_lane_layout = fx.layout_of(ret_lane_ty);
+ assert_eq!(lane_count, ret_lane_count);
+
+ for lane_idx in 0..lane_count {
+ let x_lane = x.value_lane(fx, lane_idx).load_scalar(fx);
+ let y_lane = y.value_lane(fx, lane_idx).load_scalar(fx);
+ let z_lane = z.value_lane(fx, lane_idx).load_scalar(fx);
+
+ let res_lane = f(fx, lane_layout.ty, ret_lane_layout.ty, x_lane, y_lane, z_lane);
+ let res_lane = CValue::by_val(res_lane, ret_lane_layout);
+
+ ret.place_lane(fx, lane_idx).write_cvalue(fx, res_lane);
+ }
+}
+
fn simd_reduce<'tcx>(
fx: &mut FunctionCx<'_, '_, 'tcx>,
val: CValue<'tcx>,
diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs
index 6efbe1498..ea137c4ca 100644
--- a/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs
+++ b/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs
@@ -148,7 +148,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
let total_len = lane_count * 2;
let indexes =
- idx.iter().map(|idx| idx.unwrap_leaf().try_to_u16().unwrap()).collect::<Vec<u16>>();
+ idx.iter().map(|idx| idx.unwrap_leaf().try_to_u32().unwrap()).collect::<Vec<u32>>();
for &idx in &indexes {
assert!(u64::from(idx) < total_len, "idx {} out of range 0..{}", idx, total_len);
@@ -216,8 +216,10 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
let indexes = {
use rustc_middle::mir::interpret::*;
- let idx_const = crate::constant::mir_operand_get_const_val(fx, idx)
- .expect("simd_shuffle idx not const");
+ let idx_const = match idx {
+ Operand::Constant(const_) => crate::constant::eval_mir_constant(fx, const_).0,
+ Operand::Copy(_) | Operand::Move(_) => unreachable!("{idx:?}"),
+ };
let idx_bytes = match idx_const {
ConstValue::Indirect { alloc_id, offset } => {
@@ -343,7 +345,11 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
ret.write_cvalue(fx, ret_lane);
}
- sym::simd_neg => {
+ sym::simd_neg
+ | sym::simd_bswap
+ | sym::simd_bitreverse
+ | sym::simd_ctlz
+ | sym::simd_cttz => {
intrinsic_args!(fx, args => (a); intrinsic);
if !a.layout().ty.is_simd() {
@@ -351,16 +357,21 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>(
return;
}
- simd_for_each_lane(
- fx,
- a,
- ret,
- &|fx, lane_ty, _ret_lane_ty, lane| match lane_ty.kind() {
- ty::Int(_) => fx.bcx.ins().ineg(lane),
- ty::Float(_) => fx.bcx.ins().fneg(lane),
- _ => unreachable!(),
- },
- );
+ simd_for_each_lane(fx, a, ret, &|fx, lane_ty, _ret_lane_ty, lane| match (
+ lane_ty.kind(),
+ intrinsic,
+ ) {
+ (ty::Int(_), sym::simd_neg) => fx.bcx.ins().ineg(lane),
+ (ty::Float(_), sym::simd_neg) => fx.bcx.ins().fneg(lane),
+
+ (ty::Uint(ty::UintTy::U8) | ty::Int(ty::IntTy::I8), sym::simd_bswap) => lane,
+ (ty::Uint(_) | ty::Int(_), sym::simd_bswap) => fx.bcx.ins().bswap(lane),
+ (ty::Uint(_) | ty::Int(_), sym::simd_bitreverse) => fx.bcx.ins().bitrev(lane),
+ (ty::Uint(_) | ty::Int(_), sym::simd_ctlz) => fx.bcx.ins().clz(lane),
+ (ty::Uint(_) | ty::Int(_), sym::simd_cttz) => fx.bcx.ins().ctz(lane),
+
+ _ => unreachable!(),
+ });
}
sym::simd_add
diff --git a/compiler/rustc_codegen_cranelift/src/lib.rs b/compiler/rustc_codegen_cranelift/src/lib.rs
index d01ded8ab..148193b5a 100644
--- a/compiler/rustc_codegen_cranelift/src/lib.rs
+++ b/compiler/rustc_codegen_cranelift/src/lib.rs
@@ -1,3 +1,6 @@
+#![cfg_attr(all(doc, not(bootstrap)), allow(internal_features))]
+#![cfg_attr(all(doc, not(bootstrap)), feature(rustdoc_internals))]
+#![cfg_attr(all(doc, not(bootstrap)), doc(rust_logo))]
#![feature(rustc_private)]
// Note: please avoid adding other feature gates where possible
#![warn(rust_2018_idioms)]
@@ -29,6 +32,8 @@ use std::any::Any;
use std::cell::{Cell, RefCell};
use std::sync::Arc;
+use cranelift_codegen::isa::TargetIsa;
+use cranelift_codegen::settings::{self, Configurable};
use rustc_codegen_ssa::traits::CodegenBackend;
use rustc_codegen_ssa::CodegenResults;
use rustc_data_structures::profiling::SelfProfilerRef;
@@ -39,9 +44,6 @@ use rustc_session::config::OutputFilenames;
use rustc_session::Session;
use rustc_span::Symbol;
-use cranelift_codegen::isa::TargetIsa;
-use cranelift_codegen::settings::{self, Configurable};
-
pub use crate::config::*;
use crate::prelude::*;
@@ -76,22 +78,6 @@ mod value_and_place;
mod vtable;
mod prelude {
- pub(crate) use rustc_span::{FileNameDisplayPreference, Span};
-
- pub(crate) use rustc_hir::def_id::{DefId, LOCAL_CRATE};
- pub(crate) use rustc_middle::bug;
- pub(crate) use rustc_middle::mir::{self, *};
- pub(crate) use rustc_middle::ty::layout::{self, LayoutOf, TyAndLayout};
- pub(crate) use rustc_middle::ty::{
- self, FloatTy, Instance, InstanceDef, IntTy, ParamEnv, Ty, TyCtxt, TypeAndMut,
- TypeFoldable, TypeVisitableExt, UintTy,
- };
- pub(crate) use rustc_target::abi::{Abi, FieldIdx, Scalar, Size, VariantIdx, FIRST_VARIANT};
-
- pub(crate) use rustc_data_structures::fx::{FxHashMap, FxIndexMap};
-
- pub(crate) use rustc_index::Idx;
-
pub(crate) use cranelift_codegen::ir::condcodes::{FloatCC, IntCC};
pub(crate) use cranelift_codegen::ir::function::Function;
pub(crate) use cranelift_codegen::ir::types;
@@ -103,6 +89,18 @@ mod prelude {
pub(crate) use cranelift_codegen::Context;
pub(crate) use cranelift_frontend::{FunctionBuilder, FunctionBuilderContext, Variable};
pub(crate) use cranelift_module::{self, DataDescription, FuncId, Linkage, Module};
+ pub(crate) use rustc_data_structures::fx::{FxHashMap, FxIndexMap};
+ pub(crate) use rustc_hir::def_id::{DefId, LOCAL_CRATE};
+ pub(crate) use rustc_index::Idx;
+ pub(crate) use rustc_middle::bug;
+ pub(crate) use rustc_middle::mir::{self, *};
+ pub(crate) use rustc_middle::ty::layout::{self, LayoutOf, TyAndLayout};
+ pub(crate) use rustc_middle::ty::{
+ self, FloatTy, Instance, InstanceDef, IntTy, ParamEnv, Ty, TyCtxt, TypeAndMut,
+ TypeFoldable, TypeVisitableExt, UintTy,
+ };
+ pub(crate) use rustc_span::{FileNameDisplayPreference, Span};
+ pub(crate) use rustc_target::abi::{Abi, FieldIdx, Scalar, Size, VariantIdx, FIRST_VARIANT};
pub(crate) use crate::abi::*;
pub(crate) use crate::base::{codegen_operand, codegen_place};
@@ -191,7 +189,7 @@ impl CodegenBackend for CraneliftCodegenBackend {
}
fn target_features(&self, _sess: &Session, _allow_unstable: bool) -> Vec<rustc_span::Symbol> {
- vec![]
+ vec![] // FIXME necessary for #[cfg(target_feature]
}
fn print_version(&self) {
@@ -263,9 +261,9 @@ fn build_isa(sess: &Session, backend_config: &BackendConfig) -> Arc<dyn isa::Tar
let preserve_frame_pointer = sess.target.options.frame_pointer
!= rustc_target::spec::FramePointer::MayOmit
|| matches!(sess.opts.cg.force_frame_pointers, Some(true));
- if preserve_frame_pointer {
- flags_builder.set("preserve_frame_pointers", "true").unwrap();
- }
+ flags_builder
+ .set("preserve_frame_pointers", if preserve_frame_pointer { "true" } else { "false" })
+ .unwrap();
let tls_model = match target_triple.binary_format {
BinaryFormat::Elf => "elf_gd",
diff --git a/compiler/rustc_codegen_cranelift/src/pointer.rs b/compiler/rustc_codegen_cranelift/src/pointer.rs
index b60e56720..11ac6b946 100644
--- a/compiler/rustc_codegen_cranelift/src/pointer.rs
+++ b/compiler/rustc_codegen_cranelift/src/pointer.rs
@@ -1,11 +1,10 @@
//! Defines [`Pointer`] which is used to improve the quality of the generated clif ir for pointer
//! operations.
-use crate::prelude::*;
-
+use cranelift_codegen::ir::immediates::Offset32;
use rustc_target::abi::Align;
-use cranelift_codegen::ir::immediates::Offset32;
+use crate::prelude::*;
/// A pointer pointing either to a certain address, a certain stack slot or nothing.
#[derive(Copy, Clone, Debug)]
diff --git a/compiler/rustc_codegen_cranelift/src/pretty_clif.rs b/compiler/rustc_codegen_cranelift/src/pretty_clif.rs
index 0ead50c34..da84e54a9 100644
--- a/compiler/rustc_codegen_cranelift/src/pretty_clif.rs
+++ b/compiler/rustc_codegen_cranelift/src/pretty_clif.rs
@@ -63,8 +63,8 @@ use cranelift_codegen::{
ir::entities::AnyEntity,
write::{FuncWriter, PlainWriter},
};
-
use rustc_middle::ty::layout::FnAbiOf;
+use rustc_middle::ty::print::with_no_trimmed_paths;
use rustc_session::config::{OutputFilenames, OutputType};
use crate::prelude::*;
@@ -80,15 +80,17 @@ impl CommentWriter {
pub(crate) fn new<'tcx>(tcx: TyCtxt<'tcx>, instance: Instance<'tcx>) -> Self {
let enabled = should_write_ir(tcx);
let global_comments = if enabled {
- vec![
- format!("symbol {}", tcx.symbol_name(instance).name),
- format!("instance {:?}", instance),
- format!(
- "abi {:?}",
- RevealAllLayoutCx(tcx).fn_abi_of_instance(instance, ty::List::empty())
- ),
- String::new(),
- ]
+ with_no_trimmed_paths!({
+ vec![
+ format!("symbol {}", tcx.symbol_name(instance).name),
+ format!("instance {:?}", instance),
+ format!(
+ "abi {:?}",
+ RevealAllLayoutCx(tcx).fn_abi_of_instance(instance, ty::List::empty())
+ ),
+ String::new(),
+ ]
+ })
} else {
vec![]
};
diff --git a/compiler/rustc_codegen_cranelift/src/value_and_place.rs b/compiler/rustc_codegen_cranelift/src/value_and_place.rs
index 45893a4f3..21ad2a835 100644
--- a/compiler/rustc_codegen_cranelift/src/value_and_place.rs
+++ b/compiler/rustc_codegen_cranelift/src/value_and_place.rs
@@ -1,11 +1,10 @@
//! Definition of [`CValue`] and [`CPlace`]
-use crate::prelude::*;
-
-use rustc_middle::ty::FnSig;
-
use cranelift_codegen::entity::EntityRef;
use cranelift_codegen::ir::immediates::Offset32;
+use rustc_middle::ty::FnSig;
+
+use crate::prelude::*;
fn codegen_field<'tcx>(
fx: &mut FunctionCx<'_, '_, 'tcx>,
@@ -133,18 +132,11 @@ impl<'tcx> CValue<'tcx> {
(ptr.get_addr(fx), vtable)
}
CValueInner::ByValPair(data, vtable) => {
- let stack_slot = fx.bcx.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- // FIXME Don't force the size to a multiple of 16 bytes once Cranelift gets a way to
- // specify stack slot alignment.
- size: (u32::try_from(fx.target_config.pointer_type().bytes()).unwrap() + 15)
- / 16
- * 16,
- });
- let data_ptr = Pointer::stack_slot(stack_slot);
- let mut flags = MemFlags::new();
- flags.set_notrap();
- data_ptr.store(fx, data, flags);
+ let data_ptr = fx.create_stack_slot(
+ u32::try_from(fx.target_config.pointer_type().bytes()).unwrap(),
+ u32::try_from(fx.target_config.pointer_type().bytes()).unwrap(),
+ );
+ data_ptr.store(fx, data, MemFlags::trusted());
(data_ptr.get_addr(fx), vtable)
}
@@ -251,6 +243,34 @@ impl<'tcx> CValue<'tcx> {
let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
let lane_layout = fx.layout_of(lane_ty);
assert!(lane_idx < lane_count);
+
+ match self.0 {
+ CValueInner::ByVal(_) | CValueInner::ByValPair(_, _) => unreachable!(),
+ CValueInner::ByRef(ptr, None) => {
+ let field_offset = lane_layout.size * lane_idx;
+ let field_ptr = ptr.offset_i64(fx, i64::try_from(field_offset.bytes()).unwrap());
+ CValue::by_ref(field_ptr, lane_layout)
+ }
+ CValueInner::ByRef(_, Some(_)) => unreachable!(),
+ }
+ }
+
+ /// Like [`CValue::value_field`] except using the passed type as lane type instead of the one
+ /// specified by the vector type.
+ pub(crate) fn value_typed_lane(
+ self,
+ fx: &mut FunctionCx<'_, '_, 'tcx>,
+ lane_ty: Ty<'tcx>,
+ lane_idx: u64,
+ ) -> CValue<'tcx> {
+ let layout = self.1;
+ assert!(layout.ty.is_simd());
+ let (orig_lane_count, orig_lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let lane_layout = fx.layout_of(lane_ty);
+ assert!(
+ (lane_idx + 1) * lane_layout.size <= orig_lane_count * fx.layout_of(orig_lane_ty).size
+ );
+
match self.0 {
CValueInner::ByVal(_) | CValueInner::ByValPair(_, _) => unreachable!(),
CValueInner::ByRef(ptr, None) => {
@@ -310,7 +330,8 @@ impl<'tcx> CValue<'tcx> {
fx.bcx.ins().iconcat(lsb, msb)
}
ty::Bool | ty::Char | ty::Uint(_) | ty::Int(_) | ty::Ref(..) | ty::RawPtr(..) => {
- fx.bcx.ins().iconst(clif_ty, const_val.to_bits(layout.size).unwrap() as i64)
+ let raw_val = const_val.size().truncate(const_val.to_bits(layout.size).unwrap());
+ fx.bcx.ins().iconst(clif_ty, raw_val as i64)
}
ty::Float(FloatTy::F32) => {
fx.bcx.ins().f32const(Ieee32::with_bits(u32::try_from(const_val).unwrap()))
@@ -372,13 +393,11 @@ impl<'tcx> CPlace<'tcx> {
.fatal(format!("values of type {} are too big to store on the stack", layout.ty));
}
- let stack_slot = fx.bcx.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- // FIXME Don't force the size to a multiple of 16 bytes once Cranelift gets a way to
- // specify stack slot alignment.
- size: (u32::try_from(layout.size.bytes()).unwrap() + 15) / 16 * 16,
- });
- CPlace { inner: CPlaceInner::Addr(Pointer::stack_slot(stack_slot), None), layout }
+ let stack_slot = fx.create_stack_slot(
+ u32::try_from(layout.size.bytes()).unwrap(),
+ u32::try_from(layout.align.pref.bytes()).unwrap(),
+ );
+ CPlace { inner: CPlaceInner::Addr(stack_slot, None), layout }
}
pub(crate) fn new_var(
@@ -543,13 +562,7 @@ impl<'tcx> CPlace<'tcx> {
_ if src_ty.is_vector() && dst_ty.is_vector() => codegen_bitcast(fx, dst_ty, data),
_ if src_ty.is_vector() || dst_ty.is_vector() => {
// FIXME(bytecodealliance/wasmtime#6104) do something more efficient for transmutes between vectors and integers.
- let stack_slot = fx.bcx.create_sized_stack_slot(StackSlotData {
- kind: StackSlotKind::ExplicitSlot,
- // FIXME Don't force the size to a multiple of 16 bytes once Cranelift gets a way to
- // specify stack slot alignment.
- size: (src_ty.bytes() + 15) / 16 * 16,
- });
- let ptr = Pointer::stack_slot(stack_slot);
+ let ptr = fx.create_stack_slot(src_ty.bytes(), src_ty.bytes());
ptr.store(fx, data, MemFlags::trusted());
ptr.load(fx, dst_ty, MemFlags::trusted())
}
@@ -749,6 +762,34 @@ impl<'tcx> CPlace<'tcx> {
}
}
+ /// Like [`CPlace::place_field`] except using the passed type as lane type instead of the one
+ /// specified by the vector type.
+ pub(crate) fn place_typed_lane(
+ self,
+ fx: &mut FunctionCx<'_, '_, 'tcx>,
+ lane_ty: Ty<'tcx>,
+ lane_idx: u64,
+ ) -> CPlace<'tcx> {
+ let layout = self.layout();
+ assert!(layout.ty.is_simd());
+ let (orig_lane_count, orig_lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
+ let lane_layout = fx.layout_of(lane_ty);
+ assert!(
+ (lane_idx + 1) * lane_layout.size <= orig_lane_count * fx.layout_of(orig_lane_ty).size
+ );
+
+ match self.inner {
+ CPlaceInner::Var(_, _) => unreachable!(),
+ CPlaceInner::VarPair(_, _, _) => unreachable!(),
+ CPlaceInner::Addr(ptr, None) => {
+ let field_offset = lane_layout.size * lane_idx;
+ let field_ptr = ptr.offset_i64(fx, i64::try_from(field_offset.bytes()).unwrap());
+ CPlace::for_ptr(field_ptr, lane_layout)
+ }
+ CPlaceInner::Addr(_, Some(_)) => unreachable!(),
+ }
+ }
+
pub(crate) fn place_index(
self,
fx: &mut FunctionCx<'_, '_, 'tcx>,