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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-17 12:02:58 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-17 12:02:58 +0000
commit698f8c2f01ea549d77d7dc3338a12e04c11057b9 (patch)
tree173a775858bd501c378080a10dca74132f05bc50 /src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff
parentInitial commit. (diff)
downloadrustc-698f8c2f01ea549d77d7dc3338a12e04c11057b9.tar.xz
rustc-698f8c2f01ea549d77d7dc3338a12e04c11057b9.zip
Adding upstream version 1.64.0+dfsg1.upstream/1.64.0+dfsg1
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff')
-rw-r--r--src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff44
1 files changed, 44 insertions, 0 deletions
diff --git a/src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff b/src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff
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+++ b/src/test/mir-opt/inline/inline_instruction_set.default.Inline.diff
@@ -0,0 +1,44 @@
+- // MIR for `default` before Inline
++ // MIR for `default` after Inline
+
+ fn default() -> () {
+ let mut _0: (); // return place in scope 0 at $DIR/inline-instruction-set.rs:+0:18: +0:18
+ let _1: (); // in scope 0 at $DIR/inline-instruction-set.rs:+1:5: +1:26
+ let _2: (); // in scope 0 at $DIR/inline-instruction-set.rs:+2:5: +2:26
+ let _3: (); // in scope 0 at $DIR/inline-instruction-set.rs:+3:5: +3:30
++ scope 1 (inlined instruction_set_default) { // at $DIR/inline-instruction-set.rs:53:5: 53:30
++ }
+
+ bb0: {
+ StorageLive(_1); // scope 0 at $DIR/inline-instruction-set.rs:+1:5: +1:26
+ _1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline-instruction-set.rs:+1:5: +1:26
+ // mir::Constant
+ // + span: $DIR/inline-instruction-set.rs:51:5: 51:24
+ // + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
+ }
+
+ bb1: {
+ StorageDead(_1); // scope 0 at $DIR/inline-instruction-set.rs:+1:26: +1:27
+ StorageLive(_2); // scope 0 at $DIR/inline-instruction-set.rs:+2:5: +2:26
+ _2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline-instruction-set.rs:+2:5: +2:26
+ // mir::Constant
+ // + span: $DIR/inline-instruction-set.rs:52:5: 52:24
+ // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
+ }
+
+ bb2: {
+ StorageDead(_2); // scope 0 at $DIR/inline-instruction-set.rs:+2:26: +2:27
+ StorageLive(_3); // scope 0 at $DIR/inline-instruction-set.rs:+3:5: +3:30
+- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline-instruction-set.rs:+3:5: +3:30
+- // mir::Constant
+- // + span: $DIR/inline-instruction-set.rs:53:5: 53:28
+- // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
+- }
+-
+- bb3: {
+ StorageDead(_3); // scope 0 at $DIR/inline-instruction-set.rs:+3:30: +3:31
+ _0 = const (); // scope 0 at $DIR/inline-instruction-set.rs:+0:18: +4:2
+ return; // scope 0 at $DIR/inline-instruction-set.rs:+4:2: +4:2
+ }
+ }
+