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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-17 12:19:03 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-17 12:19:03 +0000
commit64d98f8ee037282c35007b64c2649055c56af1db (patch)
tree5492bcf97fce41ee1c0b1cc2add283f3e66cdab0 /tests/mir-opt/inline/inline_instruction_set.default.Inline.diff
parentAdding debian version 1.67.1+dfsg1-1. (diff)
downloadrustc-64d98f8ee037282c35007b64c2649055c56af1db.tar.xz
rustc-64d98f8ee037282c35007b64c2649055c56af1db.zip
Merging upstream version 1.68.2+dfsg1.
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tests/mir-opt/inline/inline_instruction_set.default.Inline.diff')
-rw-r--r--tests/mir-opt/inline/inline_instruction_set.default.Inline.diff60
1 files changed, 60 insertions, 0 deletions
diff --git a/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff b/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff
new file mode 100644
index 000000000..f1988ea4b
--- /dev/null
+++ b/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff
@@ -0,0 +1,60 @@
+- // MIR for `default` before Inline
++ // MIR for `default` after Inline
+
+ fn default() -> () {
+ let mut _0: (); // return place in scope 0 at $DIR/inline_instruction_set.rs:+0:18: +0:18
+ let _1: (); // in scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
+ let _2: (); // in scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
+ let _3: (); // in scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
+ let _4: (); // in scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
++ scope 1 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:59:5: 59:30
++ }
++ scope 2 (inlined inline_always_and_using_inline_asm) { // at $DIR/inline_instruction_set.rs:60:5: 60:41
++ scope 3 {
++ }
++ }
+
+ bb0: {
+ StorageLive(_1); // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
+ _1 = instruction_set_a32() -> bb1; // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
+ // mir::Constant
+ // + span: $DIR/inline_instruction_set.rs:57:5: 57:24
+ // + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
+ }
+
+ bb1: {
+ StorageDead(_1); // scope 0 at $DIR/inline_instruction_set.rs:+1:26: +1:27
+ StorageLive(_2); // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
+ _2 = instruction_set_t32() -> bb2; // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
+ // mir::Constant
+ // + span: $DIR/inline_instruction_set.rs:58:5: 58:24
+ // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
+ }
+
+ bb2: {
+ StorageDead(_2); // scope 0 at $DIR/inline_instruction_set.rs:+2:26: +2:27
+ StorageLive(_3); // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
+- _3 = instruction_set_default() -> bb3; // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
+- // mir::Constant
+- // + span: $DIR/inline_instruction_set.rs:59:5: 59:28
+- // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
+- }
+-
+- bb3: {
+ StorageDead(_3); // scope 0 at $DIR/inline_instruction_set.rs:+3:30: +3:31
+ StorageLive(_4); // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
+- _4 = inline_always_and_using_inline_asm() -> bb4; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
+- // mir::Constant
+- // + span: $DIR/inline_instruction_set.rs:60:5: 60:39
+- // + literal: Const { ty: fn() {inline_always_and_using_inline_asm}, val: Value(<ZST>) }
++ asm!("/* do nothing */", options((empty))) -> bb3; // scope 3 at $DIR/inline_instruction_set.rs:43:14: 43:38
+ }
+
+- bb4: {
++ bb3: {
+ StorageDead(_4); // scope 0 at $DIR/inline_instruction_set.rs:+4:41: +4:42
+ _0 = const (); // scope 0 at $DIR/inline_instruction_set.rs:+0:18: +5:2
+ return; // scope 0 at $DIR/inline_instruction_set.rs:+5:2: +5:2
+ }
+ }
+