Adding upstream version 1.67.1+dfsg1.upstream/1.67.1+dfsg1

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

3 files changed, 56 insertions, 7 deletions

diff --git a/vendor/cpufeatures/src/lib.rs b/vendor/cpufeatures/src/lib.rs
index 08b6e528d..b6c7c10b2 100644
--- a/vendor/cpufeatures/src/lib.rs
+++ b/vendor/cpufeatures/src/lib.rs
@@ -59,13 +59,18 @@
     html_favicon_url = "https://raw.githubusercontent.com/RustCrypto/media/6ee8e381/logo.svg"
 )]
 
+#[cfg(not(miri))]
 #[cfg(all(target_arch = "aarch64"))]
 #[doc(hidden)]
 pub mod aarch64;
 
+#[cfg(not(miri))]
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 mod x86;
 
+#[cfg(miri)]
+mod miri;
+
 #[cfg(not(any(target_arch = "aarch64", target_arch = "x86", target_arch = "x86_64")))]
 compile_error!("This crate works only on `aarch64`, `x86`, and `x86-64` targets.");
 
diff --git a/vendor/cpufeatures/src/miri.rs b/vendor/cpufeatures/src/miri.rs
new file mode 100644
index 000000000..8dff21c13
--- /dev/null
+++ b/vendor/cpufeatures/src/miri.rs
@@ -0,0 +1,20 @@
+//! Minimal miri support.
+//!
+//! Miri is an interpreter, and though it tries to emulate the target CPU
+//! it does not support any target features.
+
+#[macro_export]
+#[doc(hidden)]
+macro_rules! __unless_target_features {
+    ($($tf:tt),+ => $body:expr ) => {
+        false
+    };
+}
+
+#[macro_export]
+#[doc(hidden)]
+macro_rules! __detect_target_features {
+    ($($tf:tt),+) => {
+        false
+    };
+}
diff --git a/vendor/cpufeatures/src/x86.rs b/vendor/cpufeatures/src/x86.rs
index 37e20ef6a..c973b7446 100644
--- a/vendor/cpufeatures/src/x86.rs
+++ b/vendor/cpufeatures/src/x86.rs
@@ -33,12 +33,27 @@ macro_rules! __unless_target_features {
 macro_rules! __detect_target_features {
     ($($tf:tt),+) => {{
         #[cfg(target_arch = "x86")]
-        use core::arch::x86::{__cpuid, __cpuid_count};
+        use core::arch::x86::{__cpuid, __cpuid_count, CpuidResult};
         #[cfg(target_arch = "x86_64")]
-        use core::arch::x86_64::{__cpuid, __cpuid_count};
+        use core::arch::x86_64::{__cpuid, __cpuid_count, CpuidResult};
+
+        // These wrappers are workarounds around
+        // https://github.com/rust-lang/rust/issues/101346
+        //
+        // DO NOT remove it until MSRV is bumped to a version
+        // with the issue fix (at least 1.64).
+        #[inline(never)]
+        unsafe fn cpuid(leaf: u32) -> CpuidResult {
+            __cpuid(leaf)
+        }
+
+        #[inline(never)]
+        unsafe fn cpuid_count(leaf: u32, sub_leaf: u32) -> CpuidResult {
+            __cpuid_count(leaf, sub_leaf)
+        }
 
         let cr = unsafe {
-            [__cpuid(1), __cpuid_count(7, 0)]
+            [cpuid(1), cpuid_count(7, 0)]
         };
 
         $($crate::check!(cr, $tf) & )+ true
@@ -46,17 +61,26 @@ macro_rules! __detect_target_features {
 }
 
 macro_rules! __expand_check_macro {
-    ($(($name:tt, $i:expr, $reg:ident, $offset:expr)),* $(,)?) => {
+    ($(($name:tt $(, $i:expr, $reg:ident, $offset:expr)*)),* $(,)?) => {
         #[macro_export]
         #[doc(hidden)]
         macro_rules! check {
             $(
-                ($cr:expr, $name) => { ($cr[$i].$reg & (1 << $offset) != 0) };
+                ($cr:expr, $name) => {
+                    true
+                    $(
+                        & ($cr[$i].$reg & (1 << $offset) != 0)
+                    )*
+                };
             )*
         }
     };
 }
 
+// Note that according to the [Intel manual][0] AVX2 and FMA require
+// that we check availability of AVX before using them.
+//
+// [0]: https://www.intel.com/content/dam/develop/external/us/en/documents/36945
 __expand_check_macro! {
     ("mmx", 0, edx, 23),
     ("sse", 0, edx, 25),
@@ -64,7 +88,7 @@ __expand_check_macro! {
     ("sse3", 0, ecx, 0),
     ("pclmulqdq", 0, ecx, 1),
     ("ssse3", 0, ecx, 9),
-    ("fma", 0, ecx, 12),
+    ("fma", 0, ecx, 28, 0, ecx, 12),
     ("sse4.1", 0, ecx, 19),
     ("sse4.2", 0, ecx, 20),
     ("popcnt", 0, ecx, 23),
@@ -73,7 +97,7 @@ __expand_check_macro! {
     ("rdrand", 0, ecx, 30),
     ("sgx", 1, ebx, 2),
     ("bmi1", 1, ebx, 3),
-    ("avx2", 1, ebx, 5),
+    ("avx2", 0, ecx, 28, 1, ebx, 5),
     ("bmi2", 1, ebx, 8),
     ("rdseed", 1, ebx, 18),
     ("adx", 1, ebx, 19),