Merging upstream version 1.72.1+dfsg1.

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

4 files changed, 91 insertions, 47 deletions

diff --git a/vendor/cpufeatures/.cargo-checksum.json b/vendor/cpufeatures/.cargo-checksum.json
index d1a17210f..bcc82d15c 100644
--- a/vendor/cpufeatures/.cargo-checksum.json
+++ b/vendor/cpufeatures/.cargo-checksum.json
@@ -1 +1 @@
-{"files":{"CHANGELOG.md":"7299f9bd386182280ca0a31f681e0d72b5be6532f7b3669c55760e51a96e96b7","Cargo.toml":"9285d971d84c92b0f1dd5a6cdbf73856d381cbd87c9f3db683c6a93712ef1d0f","LICENSE-APACHE":"a9040321c3712d8fd0b09cf52b17445de04a23a10165049ae187cd39e5c86be5","LICENSE-MIT":"904801faf3f1850328af8e1aa1047b9190cc22ed40df5c87f2d93d17f847ef67","README.md":"3a7469c8306dce5e6c1b4eb3f9d7290174e57e9118911e016a06192bc89ae67f","src/aarch64.rs":"03780cca3518699dd0f57345c9fda1cae7d73a3a77c7f1802f7f172204417694","src/lib.rs":"6e5c3f23006241c3135e8df7d25fb68ca8ee768d065a08db7910a4fcaa786a28","src/miri.rs":"acf1a7e7ae31a1de07941084c6b589a2d4c6ea5f87012c811592c865d04c02cb","src/x86.rs":"7b228a1ec6a10fef9b5e06dd6696a9c7351eb47ca2f8e9e7bea0f54c5536155b","tests/aarch64.rs":"bdabbe67316c128b57003ba5faa07707b5f339b1f3e984da4bc383cc93c2bedd","tests/x86.rs":"fcf476ca6ebd0845ab547cea4fe40c2ba2a2324c024264d9a86f666586f3a480"},"package":"280a9f2d8b3a38871a3c8a46fb80db65e5e5ed97da80c4d08bf27fb63e35e181"}
\ No newline at end of file
+{"files":{"CHANGELOG.md":"688a7222c5a7a23c1095f3d38983c7b529230858e3f5600c1115baf1d81b9809","Cargo.toml":"e23fc3baf256869f019907444cce751c17c5b36d681d5e866cdccc7b1d0a12d9","LICENSE-APACHE":"a9040321c3712d8fd0b09cf52b17445de04a23a10165049ae187cd39e5c86be5","LICENSE-MIT":"904801faf3f1850328af8e1aa1047b9190cc22ed40df5c87f2d93d17f847ef67","README.md":"3a7469c8306dce5e6c1b4eb3f9d7290174e57e9118911e016a06192bc89ae67f","src/aarch64.rs":"03780cca3518699dd0f57345c9fda1cae7d73a3a77c7f1802f7f172204417694","src/lib.rs":"6e5c3f23006241c3135e8df7d25fb68ca8ee768d065a08db7910a4fcaa786a28","src/miri.rs":"acf1a7e7ae31a1de07941084c6b589a2d4c6ea5f87012c811592c865d04c02cb","src/x86.rs":"f4a17990a3a8c1e8286bdda35d19fa1372e0548341ca205f1e7e417fa3f3e966","tests/aarch64.rs":"bdabbe67316c128b57003ba5faa07707b5f339b1f3e984da4bc383cc93c2bedd","tests/x86.rs":"fcf476ca6ebd0845ab547cea4fe40c2ba2a2324c024264d9a86f666586f3a480"},"package":"03e69e28e9f7f77debdedbaafa2866e1de9ba56df55a8bd7cfc724c25a09987c"}
\ No newline at end of file
diff --git a/vendor/cpufeatures/CHANGELOG.md b/vendor/cpufeatures/CHANGELOG.md
index 71acc5de0..a0533ef40 100644
--- a/vendor/cpufeatures/CHANGELOG.md
+++ b/vendor/cpufeatures/CHANGELOG.md
@@ -5,6 +5,18 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## 0.2.8 (2023-06-15)
+### Fixed
+- Check OS register support on x86 targets ([#919])
+
+[#919]: https://github.com/RustCrypto/utils/issues/919
+
+## 0.2.7 (2023-04-20)
+### Added
+- Support freestanding/UEFI `x86` targets ([#821])
+
+[#821]: https://github.com/RustCrypto/utils/issues/821
+
 ## 0.2.6 (2023-03-24)
 ### Added
 - Support dynamic feature detection on iOS and derivative platforms ([#848])
diff --git a/vendor/cpufeatures/Cargo.toml b/vendor/cpufeatures/Cargo.toml
index f6b9b715d..2f8eee1ad 100644
--- a/vendor/cpufeatures/Cargo.toml
+++ b/vendor/cpufeatures/Cargo.toml
@@ -12,7 +12,7 @@
 [package]
 edition = "2018"
 name = "cpufeatures"
-version = "0.2.6"
+version = "0.2.8"
 authors = ["RustCrypto Developers"]
 description = """
 Lightweight runtime CPU feature detection for x86/x86_64 and aarch64 with
diff --git a/vendor/cpufeatures/src/x86.rs b/vendor/cpufeatures/src/x86.rs
index a60fa0d30..2199f2779 100644
--- a/vendor/cpufeatures/src/x86.rs
+++ b/vendor/cpufeatures/src/x86.rs
@@ -3,22 +3,23 @@
 //! Portable, `no_std`-friendly implementation that relies on the x86 `CPUID`
 //! instruction for feature detection.
 
-// Evaluate the given `$body` expression any of the supplied target features
-// are not enabled. Otherwise returns true.
-//
-// The `$body` expression is not evaluated on SGX targets, and returns false
-// on these targets unless *all* supplied target features are enabled.
+/// Evaluate the given `$body` expression any of the supplied target features
+/// are not enabled. Otherwise returns true.
+///
+/// The `$body` expression is not evaluated on SGX targets, and returns false
+/// on these targets unless *all* supplied target features are enabled.
 #[macro_export]
 #[doc(hidden)]
 macro_rules! __unless_target_features {
     ($($tf:tt),+ => $body:expr ) => {{
         #[cfg(not(all($(target_feature=$tf,)*)))]
         {
-            #[cfg(not(target_env = "sgx"))]
+            #[cfg(not(any(target_env = "sgx", target_os = "", target_os = "uefi")))]
             $body
 
-            // CPUID is not available on SGX targets
-            #[cfg(target_env = "sgx")]
+            // CPUID is not available on SGX. Freestanding and UEFI targets
+            // do not support SIMD features with default compilation flags.
+            #[cfg(any(target_env = "sgx", target_os = "", target_os = "uefi"))]
             false
         }
 
@@ -27,7 +28,7 @@ macro_rules! __unless_target_features {
     }};
 }
 
-// Use CPUID to detect the presence of all supplied target features.
+/// Use CPUID to detect the presence of all supplied target features.
 #[macro_export]
 #[doc(hidden)]
 macro_rules! __detect_target_features {
@@ -60,54 +61,85 @@ macro_rules! __detect_target_features {
     }};
 }
 
+/// Check that OS supports required SIMD registers
+#[macro_export]
+#[doc(hidden)]
+macro_rules! __xgetbv {
+    ($cr:expr, $mask:expr) => {{
+        #[cfg(target_arch = "x86")]
+        use core::arch::x86 as arch;
+        #[cfg(target_arch = "x86_64")]
+        use core::arch::x86_64 as arch;
+
+        // Check bits 26 and 27
+        let xmask = 0b11 << 26;
+        let xsave = $cr[0].ecx & xmask == xmask;
+        if xsave {
+            let xcr0 = unsafe { arch::_xgetbv(arch::_XCR_XFEATURE_ENABLED_MASK) };
+            (xcr0 & $mask) == $mask
+        } else {
+            false
+        }
+    }};
+}
+
 macro_rules! __expand_check_macro {
-    ($(($name:tt $(, $i:expr, $reg:ident, $offset:expr)*)),* $(,)?) => {
+    ($(($name:tt, $reg_cap:tt $(, $i:expr, $reg:ident, $offset:expr)*)),* $(,)?) => {
         #[macro_export]
         #[doc(hidden)]
         macro_rules! check {
             $(
-                ($cr:expr, $name) => {
-                    true
+                ($cr:expr, $name) => {{
+                    // Register bits are listed here:
+                    // https://wiki.osdev.org/CPU_Registers_x86#Extended_Control_Registers
+                    let reg_cap = match $reg_cap {
+                        // Bit 1
+                        "xmm" => $crate::__xgetbv!($cr, 0b10),
+                        // Bits 1 and 2
+                        "ymm" => $crate::__xgetbv!($cr, 0b110),
+                        // Bits 1, 2, 5, 6, and 7
+                        "zmm" => $crate::__xgetbv!($cr, 0b1110_0110),
+                        _ => true,
+                    };
+                    reg_cap
                     $(
                         & ($cr[$i].$reg & (1 << $offset) != 0)
                     )*
-                };
+                }};
             )*
         }
     };
 }
 
-// Note that according to the [Intel manual][0] AVX2 and FMA require
-// that we check availability of AVX before using them.
-//
-// [0]: https://www.intel.com/content/dam/develop/external/us/en/documents/36945
 __expand_check_macro! {
-    ("mmx", 0, edx, 23),
-    ("sse", 0, edx, 25),
-    ("sse2", 0, edx, 26),
-    ("sse3", 0, ecx, 0),
-    ("pclmulqdq", 0, ecx, 1),
-    ("ssse3", 0, ecx, 9),
-    ("fma", 0, ecx, 28, 0, ecx, 12),
-    ("sse4.1", 0, ecx, 19),
-    ("sse4.2", 0, ecx, 20),
-    ("popcnt", 0, ecx, 23),
-    ("aes", 0, ecx, 25),
-    ("avx", 0, ecx, 28),
-    ("rdrand", 0, ecx, 30),
-    ("sgx", 1, ebx, 2),
-    ("bmi1", 1, ebx, 3),
-    ("avx2", 0, ecx, 28, 1, ebx, 5),
-    ("bmi2", 1, ebx, 8),
-    ("avx512f", 1, ebx, 16),
-    ("avx512dq", 1, ebx, 17),
-    ("rdseed", 1, ebx, 18),
-    ("adx", 1, ebx, 19),
-    ("avx512ifma", 1, ebx, 21),
-    ("avx512pf", 1, ebx, 26),
-    ("avx512er", 1, ebx, 27),
-    ("avx512cd", 1, ebx, 28),
-    ("sha", 1, ebx, 29),
-    ("avx512bw", 1, ebx, 30),
-    ("avx512vl", 1, ebx, 31),
+    ("sse3", "xmm", 0, ecx, 0),
+    ("pclmulqdq", "xmm", 0, ecx, 1),
+    ("ssse3", "xmm", 0, ecx, 9),
+    ("fma", "xmm", 0, ecx, 12, 0, ecx, 28),
+    ("sse4.1", "xmm", 0, ecx, 19),
+    ("sse4.2", "xmm", 0, ecx, 20),
+    ("popcnt", "", 0, ecx, 23),
+    ("aes", "xmm", 0, ecx, 25),
+    ("avx", "xmm", 0, ecx, 28),
+    ("rdrand", "", 0, ecx, 30),
+
+    ("mmx", "", 0, edx, 23),
+    ("sse", "xmm", 0, edx, 25),
+    ("sse2", "xmm", 0, edx, 26),
+
+    ("sgx", "", 1, ebx, 2),
+    ("bmi1", "", 1, ebx, 3),
+    ("bmi2", "", 1, ebx, 8),
+    ("avx2", "ymm", 1, ebx, 5, 0, ecx, 28),
+    ("avx512f", "zmm", 1, ebx, 16),
+    ("avx512dq", "zmm", 1, ebx, 17),
+    ("rdseed", "", 1, ebx, 18),
+    ("adx", "", 1, ebx, 19),
+    ("avx512ifma", "zmm", 1, ebx, 21),
+    ("avx512pf", "zmm", 1, ebx, 26),
+    ("avx512er", "zmm", 1, ebx, 27),
+    ("avx512cd", "zmm", 1, ebx, 28),
+    ("sha", "xmm", 1, ebx, 29),
+    ("avx512bw", "zmm", 1, ebx, 30),
+    ("avx512vl", "zmm", 1, ebx, 31),
 }