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-rw-r--r--library/stdarch/crates/core_arch/src/arm_shared/registers/aarch32.rs9
-rw-r--r--library/stdarch/crates/core_arch/src/arm_shared/registers/mod.rs121
-rw-r--r--library/stdarch/crates/core_arch/src/arm_shared/registers/v6m.rs39
-rw-r--r--library/stdarch/crates/core_arch/src/arm_shared/registers/v7m.rs17
4 files changed, 186 insertions, 0 deletions
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/registers/aarch32.rs b/library/stdarch/crates/core_arch/src/arm_shared/registers/aarch32.rs
new file mode 100644
index 000000000..e0b71218a
--- /dev/null
+++ b/library/stdarch/crates/core_arch/src/arm_shared/registers/aarch32.rs
@@ -0,0 +1,9 @@
+/// Application Program Status Register
+pub struct APSR;
+
+// Note (@Lokathor): Because this breaks the use of Rust on the Game Boy
+// Advance, this change must be reverted until Rust learns to handle cpu state
+// properly. See also: https://github.com/rust-lang/stdarch/issues/702
+
+//#[cfg(any(not(target_feature = "thumb-state"), target_feature = "v6t2"))]
+//rsr!(APSR);
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/registers/mod.rs b/library/stdarch/crates/core_arch/src/arm_shared/registers/mod.rs
new file mode 100644
index 000000000..621efe2f5
--- /dev/null
+++ b/library/stdarch/crates/core_arch/src/arm_shared/registers/mod.rs
@@ -0,0 +1,121 @@
+#[allow(unused_macros)]
+macro_rules! rsr {
+ ($R:ident) => {
+ impl super::super::sealed::Rsr for $R {
+ unsafe fn __rsr(&self) -> u32 {
+ let r: u32;
+ crate::arch::asm!(concat!("mrs {},", stringify!($R)), out(reg) r, options(nomem, nostack));
+ r
+ }
+ }
+ };
+}
+
+#[allow(unused_macros)]
+macro_rules! rsrp {
+ ($R:ident) => {
+ impl super::super::sealed::Rsrp for $R {
+ unsafe fn __rsrp(&self) -> *const u8 {
+ let r: *const u8;
+ crate::arch::asm!(concat!("mrs {},", stringify!($R)), out(reg) r, options(nomem, nostack));
+ r
+ }
+ }
+ };
+}
+
+#[allow(unused_macros)]
+macro_rules! wsr {
+ ($R:ident) => {
+ impl super::super::sealed::Wsr for $R {
+ unsafe fn __wsr(&self, value: u32) {
+ crate::arch::asm!(concat!("msr ", stringify!($R), ", {}"), in(reg) value, options(nomem, nostack));
+ }
+ }
+ };
+}
+
+#[allow(unused_macros)]
+macro_rules! wsrp {
+ ($R:ident) => {
+ impl super::super::sealed::Wsrp for $R {
+ unsafe fn __wsrp(&self, value: *const u8) {
+ crate::arch::asm!(concat!("msr ", stringify!($R), ", {}"), in(reg) value, options(nomem, nostack));
+ }
+ }
+ };
+}
+
+#[cfg(target_feature = "mclass")]
+mod v6m;
+
+#[cfg(target_feature = "mclass")]
+pub use self::v6m::*;
+
+#[cfg(all(target_feature = "v7", target_feature = "mclass"))]
+mod v7m;
+
+#[cfg(all(target_feature = "v7", target_feature = "mclass"))]
+pub use self::v7m::*;
+
+#[cfg(not(target_arch = "aarch64"))]
+mod aarch32;
+
+#[cfg(not(target_arch = "aarch64"))]
+pub use self::aarch32::*;
+
+/// Reads a 32-bit system register
+#[inline(always)]
+pub unsafe fn __rsr<R>(reg: R) -> u32
+where
+ R: super::sealed::Rsr,
+{
+ reg.__rsr()
+}
+
+/// Reads a 64-bit system register
+#[cfg(target_arch = "aarch64")]
+#[inline(always)]
+pub unsafe fn __rsr64<R>(reg: R) -> u64
+where
+ R: super::sealed::Rsr64,
+{
+ reg.__rsr64()
+}
+
+/// Reads a system register containing an address
+#[inline(always)]
+pub unsafe fn __rsrp<R>(reg: R) -> *const u8
+where
+ R: super::sealed::Rsrp,
+{
+ reg.__rsrp()
+}
+
+/// Writes a 32-bit system register
+#[inline(always)]
+pub unsafe fn __wsr<R>(reg: R, value: u32)
+where
+ R: super::sealed::Wsr,
+{
+ reg.__wsr(value)
+}
+
+/// Writes a 64-bit system register
+#[cfg(target_arch = "aarch64")]
+#[inline(always)]
+pub unsafe fn __wsr64<R>(reg: R, value: u64)
+where
+ R: super::sealed::Wsr64,
+{
+ reg.__wsr64(value)
+}
+
+/// Writes a system register containing an address
+#[inline(always)]
+pub unsafe fn __wsrp<R>(reg: R, value: *const u8)
+where
+ R: super::sealed::Wsrp,
+{
+ reg.__wsrp(value)
+}
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/registers/v6m.rs b/library/stdarch/crates/core_arch/src/arm_shared/registers/v6m.rs
new file mode 100644
index 000000000..7acc63b6d
--- /dev/null
+++ b/library/stdarch/crates/core_arch/src/arm_shared/registers/v6m.rs
@@ -0,0 +1,39 @@
+/// CONTROL register
+pub struct CONTROL;
+
+rsr!(CONTROL);
+wsr!(CONTROL);
+
+/// Execution Program Status Register
+pub struct EPSR;
+
+rsr!(EPSR);
+
+/// Interrupt Program Status Register
+pub struct IPSR;
+
+rsr!(IPSR);
+
+/// Main Stack Pointer
+pub struct MSP;
+
+rsrp!(MSP);
+wsrp!(MSP);
+
+/// Priority Mask Register
+pub struct PRIMASK;
+
+rsr!(PRIMASK);
+wsr!(PRIMASK);
+
+/// Process Stack Pointer
+pub struct PSP;
+
+rsrp!(PSP);
+wsrp!(PSP);
+
+/// Program Status Register
+#[allow(non_camel_case_types)]
+pub struct xPSR;
+
+rsr!(xPSR);
diff --git a/library/stdarch/crates/core_arch/src/arm_shared/registers/v7m.rs b/library/stdarch/crates/core_arch/src/arm_shared/registers/v7m.rs
new file mode 100644
index 000000000..d1b1d474f
--- /dev/null
+++ b/library/stdarch/crates/core_arch/src/arm_shared/registers/v7m.rs
@@ -0,0 +1,17 @@
+/// Base Priority Mask Register
+pub struct BASEPRI;
+
+rsr!(BASEPRI);
+wsr!(BASEPRI);
+
+/// Base Priority Mask Register (conditional write)
+#[allow(non_camel_case_types)]
+pub struct BASEPRI_MAX;
+
+wsr!(BASEPRI_MAX);
+
+/// Fault Mask Register
+pub struct FAULTMASK;
+
+rsr!(FAULTMASK);
+wsr!(FAULTMASK);