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-rw-r--r--library/stdarch/crates/core_arch/src/riscv_shared/mod.rs12
1 files changed, 6 insertions, 6 deletions
diff --git a/library/stdarch/crates/core_arch/src/riscv_shared/mod.rs b/library/stdarch/crates/core_arch/src/riscv_shared/mod.rs
index 0e35fe1f1..ed021df5a 100644
--- a/library/stdarch/crates/core_arch/src/riscv_shared/mod.rs
+++ b/library/stdarch/crates/core_arch/src/riscv_shared/mod.rs
@@ -488,7 +488,7 @@ pub unsafe fn hinval_gvma_all() {
/// Register `fcsr` is a 32-bit read/write register that selects the dynamic rounding mode
/// for floating-point arithmetic operations and holds the accrued exception flag.
///
-/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
+/// According to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
/// register `fcsr` is defined as:
///
/// | Bit index | Meaning |
@@ -521,7 +521,7 @@ pub fn fscsr(value: u32) -> u32 {
/// Reads the floating-point rounding mode register `frm`
///
-/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
+/// According to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
/// the rounding mode field is defined as listed in the table below:
///
/// | Rounding Mode | Mnemonic | Meaning |
@@ -558,8 +558,8 @@ pub fn fsrm(value: u32) -> u32 {
/// The accrued exception flags indicate the exception conditions that have arisen
/// on any floating-point arithmetic instruction since the field was last reset by software.
///
-/// Accoding to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
-/// the accured exception flags is defined as a bit vector of 5 bits.
+/// According to "F" Standard Extension for Single-Precision Floating-Point, Version 2.2,
+/// the accrued exception flags is defined as a bit vector of 5 bits.
/// The meaning of each binary bit is listed in the table below.
///
/// | Bit index | Mnemonic | Meaning |
@@ -691,7 +691,7 @@ pub fn sm3p1(x: u32) -> u32 {
#[inline]
#[target_feature(enable = "zksed")]
pub fn sm4ed<const BS: u8>(x: u32, a: u32) -> u32 {
- static_assert!(BS: u8 where BS <= 3);
+ static_assert!(BS <= 3);
let ans: u32;
unsafe {
asm!("sm4ed {}, {}, {}, {}", lateout(reg) ans, in(reg) x, in(reg) a, const BS, options(pure, nomem, nostack))
@@ -751,7 +751,7 @@ pub fn sm4ed<const BS: u8>(x: u32, a: u32) -> u32 {
#[inline]
#[target_feature(enable = "zksed")]
pub fn sm4ks<const BS: u8>(x: u32, k: u32) -> u32 {
- static_assert!(BS: u8 where BS <= 3);
+ static_assert!(BS <= 3);
let ans: u32;
unsafe {
asm!("sm4ks {}, {}, {}, {}", lateout(reg) ans, in(reg) x, in(reg) k, const BS, options(pure, nomem, nostack))