diff options
Diffstat (limited to 'library/stdarch/crates/core_arch/src/x86/bmi1.rs')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/x86/bmi1.rs | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/library/stdarch/crates/core_arch/src/x86/bmi1.rs b/library/stdarch/crates/core_arch/src/x86/bmi1.rs index 0f769f33b..713ebf76e 100644 --- a/library/stdarch/crates/core_arch/src/x86/bmi1.rs +++ b/library/stdarch/crates/core_arch/src/x86/bmi1.rs @@ -15,7 +15,7 @@ use stdarch_test::assert_instr; /// Extracts bits in range [`start`, `start` + `length`) from `a` into /// the least significant bits of the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_bextr_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(bextr))] @@ -30,7 +30,7 @@ pub unsafe fn _bextr_u32(a: u32, start: u32, len: u32) -> u32 { /// Bits `[7,0]` of `control` specify the index to the first bit in the range /// to be extracted, and bits `[15,8]` specify the length of the range. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_bextr2_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_bextr2_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(bextr))] @@ -41,7 +41,7 @@ pub unsafe fn _bextr2_u32(a: u32, control: u32) -> u32 { /// Bitwise logical `AND` of inverted `a` with `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_andn_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_andn_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(andn))] @@ -52,7 +52,7 @@ pub unsafe fn _andn_u32(a: u32, b: u32) -> u32 { /// Extracts lowest set isolated bit. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsi_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsi_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(blsi))] @@ -63,7 +63,7 @@ pub unsafe fn _blsi_u32(x: u32) -> u32 { /// Gets mask up to lowest set bit. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsmsk_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsmsk_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(blsmsk))] @@ -76,7 +76,7 @@ pub unsafe fn _blsmsk_u32(x: u32) -> u32 { /// /// If `x` is sets CF. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_blsr_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_blsr_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(blsr))] @@ -89,7 +89,7 @@ pub unsafe fn _blsr_u32(x: u32) -> u32 { /// /// When the source operand is `0`, it returns its size in bits. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_tzcnt_u32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_tzcnt_u32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(tzcnt))] @@ -102,7 +102,7 @@ pub unsafe fn _tzcnt_u32(x: u32) -> u32 { /// /// When the source operand is `0`, it returns its size in bits. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_tzcnt_32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_tzcnt_32) #[inline] #[target_feature(enable = "bmi1")] #[cfg_attr(test, assert_instr(tzcnt))] |