diff options
Diffstat (limited to 'library/stdarch/crates/core_arch/src/x86/gfni.rs')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/x86/gfni.rs | 94 |
1 files changed, 47 insertions, 47 deletions
diff --git a/library/stdarch/crates/core_arch/src/x86/gfni.rs b/library/stdarch/crates/core_arch/src/x86/gfni.rs index 679b2548a..7c2195e71 100644 --- a/library/stdarch/crates/core_arch/src/x86/gfni.rs +++ b/library/stdarch/crates/core_arch/src/x86/gfni.rs @@ -63,7 +63,7 @@ extern "C" { /// The field is in polynomial representation with the reduction polynomial /// x^8 + x^4 + x^3 + x + 1. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -78,7 +78,7 @@ pub unsafe fn _mm512_gf2p8mul_epi8(a: __m512i, b: __m512i) -> __m512i { /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -102,7 +102,7 @@ pub unsafe fn _mm512_mask_gf2p8mul_epi8( /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -119,7 +119,7 @@ pub unsafe fn _mm512_maskz_gf2p8mul_epi8(k: __mmask64, a: __m512i, b: __m512i) - /// The field is in polynomial representation with the reduction polynomial /// x^8 + x^4 + x^3 + x + 1. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -134,7 +134,7 @@ pub unsafe fn _mm256_gf2p8mul_epi8(a: __m256i, b: __m256i) -> __m256i { /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -158,7 +158,7 @@ pub unsafe fn _mm256_mask_gf2p8mul_epi8( /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -175,7 +175,7 @@ pub unsafe fn _mm256_maskz_gf2p8mul_epi8(k: __mmask32, a: __m256i, b: __m256i) - /// The field is in polynomial representation with the reduction polynomial /// x^8 + x^4 + x^3 + x + 1. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni")] #[cfg_attr(test, assert_instr(gf2p8mulb))] @@ -190,7 +190,7 @@ pub unsafe fn _mm_gf2p8mul_epi8(a: __m128i, b: __m128i) -> __m128i { /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -214,7 +214,7 @@ pub unsafe fn _mm_mask_gf2p8mul_epi8( /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_gf2p8mul_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_gf2p8mul_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8mulb))] @@ -232,13 +232,13 @@ pub unsafe fn _mm_maskz_gf2p8mul_epi8(k: __mmask16, a: __m128i, b: __m128i) -> _ /// and b being a constant 8-bit immediate value. /// Each pack of 8 bytes in x is paired with the 64-bit word at the same position in a. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_gf2p8affine_epi64_epi8<const B: i32>(x: __m512i, a: __m512i) -> __m512i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x64(); let a = a.as_i8x64(); @@ -254,7 +254,7 @@ pub unsafe fn _mm512_gf2p8affine_epi64_epi8<const B: i32>(x: __m512i, a: __m512i /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] @@ -264,7 +264,7 @@ pub unsafe fn _mm512_maskz_gf2p8affine_epi64_epi8<const B: i32>( x: __m512i, a: __m512i, ) -> __m512i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let zero = _mm512_setzero_si512().as_i8x64(); let x = x.as_i8x64(); @@ -281,7 +281,7 @@ pub unsafe fn _mm512_maskz_gf2p8affine_epi64_epi8<const B: i32>( /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] @@ -292,7 +292,7 @@ pub unsafe fn _mm512_mask_gf2p8affine_epi64_epi8<const B: i32>( x: __m512i, a: __m512i, ) -> __m512i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x64(); let a = a.as_i8x64(); @@ -305,13 +305,13 @@ pub unsafe fn _mm512_mask_gf2p8affine_epi64_epi8<const B: i32>( /// and b being a constant 8-bit immediate value. /// Each pack of 8 bytes in x is paired with the 64-bit word at the same position in a. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm256_gf2p8affine_epi64_epi8<const B: i32>(x: __m256i, a: __m256i) -> __m256i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x32(); let a = a.as_i8x32(); @@ -327,7 +327,7 @@ pub unsafe fn _mm256_gf2p8affine_epi64_epi8<const B: i32>(x: __m256i, a: __m256i /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] @@ -337,7 +337,7 @@ pub unsafe fn _mm256_maskz_gf2p8affine_epi64_epi8<const B: i32>( x: __m256i, a: __m256i, ) -> __m256i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let zero = _mm256_setzero_si256().as_i8x32(); let x = x.as_i8x32(); @@ -354,7 +354,7 @@ pub unsafe fn _mm256_maskz_gf2p8affine_epi64_epi8<const B: i32>( /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] @@ -365,7 +365,7 @@ pub unsafe fn _mm256_mask_gf2p8affine_epi64_epi8<const B: i32>( x: __m256i, a: __m256i, ) -> __m256i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x32(); let a = a.as_i8x32(); @@ -378,13 +378,13 @@ pub unsafe fn _mm256_mask_gf2p8affine_epi64_epi8<const B: i32>( /// and b being a constant 8-bit immediate value. /// Each pack of 8 bytes in x is paired with the 64-bit word at the same position in a. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni")] #[cfg_attr(test, assert_instr(gf2p8affineqb, B = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm_gf2p8affine_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) -> __m128i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x16(); let a = a.as_i8x16(); @@ -400,7 +400,7 @@ pub unsafe fn _mm_gf2p8affine_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) - /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] @@ -410,7 +410,7 @@ pub unsafe fn _mm_maskz_gf2p8affine_epi64_epi8<const B: i32>( x: __m128i, a: __m128i, ) -> __m128i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let zero = _mm_setzero_si128().as_i8x16(); let x = x.as_i8x16(); @@ -427,7 +427,7 @@ pub unsafe fn _mm_maskz_gf2p8affine_epi64_epi8<const B: i32>( /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_gf2p8affine_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_gf2p8affine_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineqb, B = 0))] @@ -438,7 +438,7 @@ pub unsafe fn _mm_mask_gf2p8affine_epi64_epi8<const B: i32>( x: __m128i, a: __m128i, ) -> __m128i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x16(); let a = a.as_i8x16(); @@ -453,13 +453,13 @@ pub unsafe fn _mm_mask_gf2p8affine_epi64_epi8<const B: i32>( /// The inverse of 0 is 0. /// Each pack of 8 bytes in x is paired with the 64-bit word at the same position in a. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm512_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m512i, a: __m512i) -> __m512i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x64(); let a = a.as_i8x64(); @@ -477,7 +477,7 @@ pub unsafe fn _mm512_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m512i, a: __m5 /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_maskz_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_maskz_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] @@ -487,7 +487,7 @@ pub unsafe fn _mm512_maskz_gf2p8affineinv_epi64_epi8<const B: i32>( x: __m512i, a: __m512i, ) -> __m512i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let zero = _mm512_setzero_si512().as_i8x64(); let x = x.as_i8x64(); @@ -506,7 +506,7 @@ pub unsafe fn _mm512_maskz_gf2p8affineinv_epi64_epi8<const B: i32>( /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_mask_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_mask_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512f")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] @@ -517,7 +517,7 @@ pub unsafe fn _mm512_mask_gf2p8affineinv_epi64_epi8<const B: i32>( x: __m512i, a: __m512i, ) -> __m512i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x64(); let a = a.as_i8x64(); @@ -532,13 +532,13 @@ pub unsafe fn _mm512_mask_gf2p8affineinv_epi64_epi8<const B: i32>( /// The inverse of 0 is 0. /// Each pack of 8 bytes in x is paired with the 64-bit word at the same position in a. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm256_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m256i, a: __m256i) -> __m256i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x32(); let a = a.as_i8x32(); @@ -556,7 +556,7 @@ pub unsafe fn _mm256_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m256i, a: __m2 /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_maskz_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_maskz_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] @@ -566,7 +566,7 @@ pub unsafe fn _mm256_maskz_gf2p8affineinv_epi64_epi8<const B: i32>( x: __m256i, a: __m256i, ) -> __m256i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let zero = _mm256_setzero_si256().as_i8x32(); let x = x.as_i8x32(); @@ -585,7 +585,7 @@ pub unsafe fn _mm256_maskz_gf2p8affineinv_epi64_epi8<const B: i32>( /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm256_mask_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_mask_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] @@ -596,7 +596,7 @@ pub unsafe fn _mm256_mask_gf2p8affineinv_epi64_epi8<const B: i32>( x: __m256i, a: __m256i, ) -> __m256i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x32(); let a = a.as_i8x32(); @@ -611,13 +611,13 @@ pub unsafe fn _mm256_mask_gf2p8affineinv_epi64_epi8<const B: i32>( /// The inverse of 0 is 0. /// Each pack of 8 bytes in x is paired with the 64-bit word at the same position in a. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni")] #[cfg_attr(test, assert_instr(gf2p8affineinvqb, B = 0))] #[rustc_legacy_const_generics(2)] pub unsafe fn _mm_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m128i, a: __m128i) -> __m128i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x16(); let a = a.as_i8x16(); @@ -635,7 +635,7 @@ pub unsafe fn _mm_gf2p8affineinv_epi64_epi8<const B: i32>(x: __m128i, a: __m128i /// Uses the writemask in k - elements are zeroed in the result if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskz_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskz_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] @@ -645,7 +645,7 @@ pub unsafe fn _mm_maskz_gf2p8affineinv_epi64_epi8<const B: i32>( x: __m128i, a: __m128i, ) -> __m128i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let zero = _mm_setzero_si128().as_i8x16(); let x = x.as_i8x16(); @@ -664,7 +664,7 @@ pub unsafe fn _mm_maskz_gf2p8affineinv_epi64_epi8<const B: i32>( /// Uses the writemask in k - elements are copied from src if the corresponding mask bit is not set. /// Otherwise the computation result is written into the result. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mask_gf2p8affineinv_epi64_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mask_gf2p8affineinv_epi64_epi8) #[inline] #[target_feature(enable = "gfni,avx512bw,avx512vl")] #[cfg_attr(test, assert_instr(vgf2p8affineinvqb, B = 0))] @@ -675,7 +675,7 @@ pub unsafe fn _mm_mask_gf2p8affineinv_epi64_epi8<const B: i32>( x: __m128i, a: __m128i, ) -> __m128i { - static_assert_imm8!(B); + static_assert_uimm_bits!(B, 8); let b = B as u8; let x = x.as_i8x16(); let a = a.as_i8x16(); @@ -698,7 +698,7 @@ mod tests { fn mulbyte(left: u8, right: u8) -> u8 { // this implementation follows the description in - // https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm512_gf2p8mul_epi8 + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm512_gf2p8mul_epi8 const REDUCTION_POLYNOMIAL: u16 = 0x11b; let left: u16 = left.into(); let right: u16 = right.into(); @@ -742,7 +742,7 @@ mod tests { fn mat_vec_multiply_affine(matrix: u64, x: u8, b: u8) -> u8 { // this implementation follows the description in - // https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_gf2p8affine_epi64_epi8 + // https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_gf2p8affine_epi64_epi8 let mut accumulator = 0; for bit in 0..8 { |