diff options
Diffstat (limited to 'library/stdarch/crates/core_arch/src/x86/sse2.rs')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/x86/sse2.rs | 510 |
1 files changed, 255 insertions, 255 deletions
diff --git a/library/stdarch/crates/core_arch/src/x86/sse2.rs b/library/stdarch/crates/core_arch/src/x86/sse2.rs index cde4bc316..e118ac05f 100644 --- a/library/stdarch/crates/core_arch/src/x86/sse2.rs +++ b/library/stdarch/crates/core_arch/src/x86/sse2.rs @@ -15,7 +15,7 @@ use crate::{ /// This can help improve the performance and power consumption of spin-wait /// loops. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_pause) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_pause) #[inline] #[cfg_attr(all(test, target_feature = "sse2"), assert_instr(pause))] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -28,7 +28,7 @@ pub unsafe fn _mm_pause() { /// Invalidates and flushes the cache line that contains `p` from all levels of /// the cache hierarchy. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_clflush) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_clflush) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(clflush))] @@ -44,7 +44,7 @@ pub unsafe fn _mm_clflush(p: *const u8) { /// globally visible before any load instruction which follows the fence in /// program order. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_lfence) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_lfence) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(lfence))] @@ -60,7 +60,7 @@ pub unsafe fn _mm_lfence() { /// memory fence instruction is globally visible before any memory instruction /// which follows the fence in program order. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mfence) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mfence) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(mfence))] @@ -71,7 +71,7 @@ pub unsafe fn _mm_mfence() { /// Adds packed 8-bit integers in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddb))] @@ -82,7 +82,7 @@ pub unsafe fn _mm_add_epi8(a: __m128i, b: __m128i) -> __m128i { /// Adds packed 16-bit integers in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddw))] @@ -93,7 +93,7 @@ pub unsafe fn _mm_add_epi16(a: __m128i, b: __m128i) -> __m128i { /// Adds packed 32-bit integers in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddd))] @@ -104,7 +104,7 @@ pub unsafe fn _mm_add_epi32(a: __m128i, b: __m128i) -> __m128i { /// Adds packed 64-bit integers in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddq))] @@ -115,7 +115,7 @@ pub unsafe fn _mm_add_epi64(a: __m128i, b: __m128i) -> __m128i { /// Adds packed 8-bit integers in `a` and `b` using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_adds_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddsb))] @@ -126,7 +126,7 @@ pub unsafe fn _mm_adds_epi8(a: __m128i, b: __m128i) -> __m128i { /// Adds packed 16-bit integers in `a` and `b` using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_adds_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddsw))] @@ -137,7 +137,7 @@ pub unsafe fn _mm_adds_epi16(a: __m128i, b: __m128i) -> __m128i { /// Adds packed unsigned 8-bit integers in `a` and `b` using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epu8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_adds_epu8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddusb))] @@ -148,7 +148,7 @@ pub unsafe fn _mm_adds_epu8(a: __m128i, b: __m128i) -> __m128i { /// Adds packed unsigned 16-bit integers in `a` and `b` using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_adds_epu16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_adds_epu16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(paddusw))] @@ -159,7 +159,7 @@ pub unsafe fn _mm_adds_epu16(a: __m128i, b: __m128i) -> __m128i { /// Averages packed unsigned 8-bit integers in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_avg_epu8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_avg_epu8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pavgb))] @@ -170,7 +170,7 @@ pub unsafe fn _mm_avg_epu8(a: __m128i, b: __m128i) -> __m128i { /// Averages packed unsigned 16-bit integers in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_avg_epu16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_avg_epu16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pavgw))] @@ -185,7 +185,7 @@ pub unsafe fn _mm_avg_epu16(a: __m128i, b: __m128i) -> __m128i { /// intermediate signed 32-bit integers. Horizontally add adjacent pairs of /// intermediate 32-bit integers. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_madd_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_madd_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmaddwd))] @@ -197,7 +197,7 @@ pub unsafe fn _mm_madd_epi16(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 16-bit integers in `a` and `b`, and returns the packed /// maximum values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmaxsw))] @@ -211,7 +211,7 @@ pub unsafe fn _mm_max_epi16(a: __m128i, b: __m128i) -> __m128i { /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns the /// packed maximum values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_epu8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_epu8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmaxub))] @@ -225,7 +225,7 @@ pub unsafe fn _mm_max_epu8(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 16-bit integers in `a` and `b`, and returns the packed /// minimum values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pminsw))] @@ -239,7 +239,7 @@ pub unsafe fn _mm_min_epi16(a: __m128i, b: __m128i) -> __m128i { /// Compares packed unsigned 8-bit integers in `a` and `b`, and returns the /// packed minimum values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_epu8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_epu8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pminub))] @@ -255,7 +255,7 @@ pub unsafe fn _mm_min_epu8(a: __m128i, b: __m128i) -> __m128i { /// The multiplication produces intermediate 32-bit integers, and returns the /// high 16 bits of the intermediate integers. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mulhi_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mulhi_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmulhw))] @@ -269,7 +269,7 @@ pub unsafe fn _mm_mulhi_epi16(a: __m128i, b: __m128i) -> __m128i { /// The multiplication produces intermediate 32-bit integers, and returns the /// high 16 bits of the intermediate integers. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mulhi_epu16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mulhi_epu16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmulhuw))] @@ -283,7 +283,7 @@ pub unsafe fn _mm_mulhi_epu16(a: __m128i, b: __m128i) -> __m128i { /// The multiplication produces intermediate 32-bit integers, and returns the /// low 16 bits of the intermediate integers. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mullo_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mullo_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmullw))] @@ -297,7 +297,7 @@ pub unsafe fn _mm_mullo_epi16(a: __m128i, b: __m128i) -> __m128i { /// /// Returns the unsigned 64-bit results. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_epu32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mul_epu32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmuludq))] @@ -313,7 +313,7 @@ pub unsafe fn _mm_mul_epu32(a: __m128i, b: __m128i) -> __m128i { /// two unsigned 16-bit integers, and pack these unsigned 16-bit integers in /// the low 16 bits of 64-bit elements returned. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sad_epu8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sad_epu8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psadbw))] @@ -324,7 +324,7 @@ pub unsafe fn _mm_sad_epu8(a: __m128i, b: __m128i) -> __m128i { /// Subtracts packed 8-bit integers in `b` from packed 8-bit integers in `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sub_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubb))] @@ -335,7 +335,7 @@ pub unsafe fn _mm_sub_epi8(a: __m128i, b: __m128i) -> __m128i { /// Subtracts packed 16-bit integers in `b` from packed 16-bit integers in `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sub_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubw))] @@ -346,7 +346,7 @@ pub unsafe fn _mm_sub_epi16(a: __m128i, b: __m128i) -> __m128i { /// Subtract packed 32-bit integers in `b` from packed 32-bit integers in `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sub_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubd))] @@ -357,7 +357,7 @@ pub unsafe fn _mm_sub_epi32(a: __m128i, b: __m128i) -> __m128i { /// Subtract packed 64-bit integers in `b` from packed 64-bit integers in `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sub_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubq))] @@ -369,7 +369,7 @@ pub unsafe fn _mm_sub_epi64(a: __m128i, b: __m128i) -> __m128i { /// Subtract packed 8-bit integers in `b` from packed 8-bit integers in `a` /// using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_subs_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubsb))] @@ -381,7 +381,7 @@ pub unsafe fn _mm_subs_epi8(a: __m128i, b: __m128i) -> __m128i { /// Subtract packed 16-bit integers in `b` from packed 16-bit integers in `a` /// using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_subs_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubsw))] @@ -393,7 +393,7 @@ pub unsafe fn _mm_subs_epi16(a: __m128i, b: __m128i) -> __m128i { /// Subtract packed unsigned 8-bit integers in `b` from packed unsigned 8-bit /// integers in `a` using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epu8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_subs_epu8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubusb))] @@ -405,7 +405,7 @@ pub unsafe fn _mm_subs_epu8(a: __m128i, b: __m128i) -> __m128i { /// Subtract packed unsigned 16-bit integers in `b` from packed unsigned 16-bit /// integers in `a` using saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_subs_epu16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_subs_epu16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psubusw))] @@ -416,14 +416,14 @@ pub unsafe fn _mm_subs_epu16(a: __m128i, b: __m128i) -> __m128i { /// Shifts `a` left by `IMM8` bytes while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_slli_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pslldq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_slli_si128<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); _mm_slli_si128_impl::<IMM8>(a) } @@ -441,10 +441,10 @@ unsafe fn _mm_slli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i { } } let zero = _mm_set1_epi8(0).as_i8x16(); - transmute::<i8x16, _>(simd_shuffle16!( + transmute::<i8x16, _>(simd_shuffle!( zero, a.as_i8x16(), - <const IMM8: i32> [ + [ mask(IMM8, 0), mask(IMM8, 1), mask(IMM8, 2), @@ -467,47 +467,47 @@ unsafe fn _mm_slli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i { /// Shifts `a` left by `IMM8` bytes while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_bslli_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_bslli_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pslldq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_bslli_si128<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); _mm_slli_si128_impl::<IMM8>(a) } /// Shifts `a` right by `IMM8` bytes while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_bsrli_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_bsrli_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrldq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_bsrli_si128<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); _mm_srli_si128_impl::<IMM8>(a) } /// Shifts packed 16-bit integers in `a` left by `IMM8` while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_slli_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psllw, IMM8 = 7))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_slli_epi16<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(pslliw(a.as_i16x8(), IMM8)) } /// Shifts packed 16-bit integers in `a` left by `count` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sll_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sll_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psllw))] @@ -518,21 +518,21 @@ pub unsafe fn _mm_sll_epi16(a: __m128i, count: __m128i) -> __m128i { /// Shifts packed 32-bit integers in `a` left by `IMM8` while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_slli_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pslld, IMM8 = 7))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_slli_epi32<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(psllid(a.as_i32x4(), IMM8)) } /// Shifts packed 32-bit integers in `a` left by `count` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sll_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sll_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pslld))] @@ -543,21 +543,21 @@ pub unsafe fn _mm_sll_epi32(a: __m128i, count: __m128i) -> __m128i { /// Shifts packed 64-bit integers in `a` left by `IMM8` while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_slli_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_slli_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psllq, IMM8 = 7))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_slli_epi64<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(pslliq(a.as_i64x2(), IMM8)) } /// Shifts packed 64-bit integers in `a` left by `count` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sll_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sll_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psllq))] @@ -569,21 +569,21 @@ pub unsafe fn _mm_sll_epi64(a: __m128i, count: __m128i) -> __m128i { /// Shifts packed 16-bit integers in `a` right by `IMM8` while shifting in sign /// bits. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srai_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srai_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psraw, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_srai_epi16<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(psraiw(a.as_i16x8(), IMM8)) } /// Shifts packed 16-bit integers in `a` right by `count` while shifting in sign /// bits. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sra_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sra_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psraw))] @@ -595,21 +595,21 @@ pub unsafe fn _mm_sra_epi16(a: __m128i, count: __m128i) -> __m128i { /// Shifts packed 32-bit integers in `a` right by `IMM8` while shifting in sign /// bits. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srai_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srai_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrad, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_srai_epi32<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(psraid(a.as_i32x4(), IMM8)) } /// Shifts packed 32-bit integers in `a` right by `count` while shifting in sign /// bits. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sra_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sra_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrad))] @@ -620,14 +620,14 @@ pub unsafe fn _mm_sra_epi32(a: __m128i, count: __m128i) -> __m128i { /// Shifts `a` right by `IMM8` bytes while shifting in zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srli_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrldq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_srli_si128<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); _mm_srli_si128_impl::<IMM8>(a) } @@ -644,10 +644,10 @@ unsafe fn _mm_srli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i { } } let zero = _mm_set1_epi8(0).as_i8x16(); - let x: i8x16 = simd_shuffle16!( + let x: i8x16 = simd_shuffle!( a.as_i8x16(), zero, - <const IMM8: i32> [ + [ mask(IMM8, 0), mask(IMM8, 1), mask(IMM8, 2), @@ -672,21 +672,21 @@ unsafe fn _mm_srli_si128_impl<const IMM8: i32>(a: __m128i) -> __m128i { /// Shifts packed 16-bit integers in `a` right by `IMM8` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srli_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrlw, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_srli_epi16<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(psrliw(a.as_i16x8(), IMM8)) } /// Shifts packed 16-bit integers in `a` right by `count` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srl_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srl_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrlw))] @@ -698,21 +698,21 @@ pub unsafe fn _mm_srl_epi16(a: __m128i, count: __m128i) -> __m128i { /// Shifts packed 32-bit integers in `a` right by `IMM8` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srli_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrld, IMM8 = 8))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_srli_epi32<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(psrlid(a.as_i32x4(), IMM8)) } /// Shifts packed 32-bit integers in `a` right by `count` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srl_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srl_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrld))] @@ -724,21 +724,21 @@ pub unsafe fn _mm_srl_epi32(a: __m128i, count: __m128i) -> __m128i { /// Shifts packed 64-bit integers in `a` right by `IMM8` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srli_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srli_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrlq, IMM8 = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_srli_epi64<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); transmute(psrliq(a.as_i64x2(), IMM8)) } /// Shifts packed 64-bit integers in `a` right by `count` while shifting in /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_srl_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_srl_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(psrlq))] @@ -750,7 +750,7 @@ pub unsafe fn _mm_srl_epi64(a: __m128i, count: __m128i) -> __m128i { /// Computes the bitwise AND of 128 bits (representing integer data) in `a` and /// `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_and_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_and_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(andps))] @@ -762,7 +762,7 @@ pub unsafe fn _mm_and_si128(a: __m128i, b: __m128i) -> __m128i { /// Computes the bitwise NOT of 128 bits (representing integer data) in `a` and /// then AND with `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_andnot_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_andnot_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(andnps))] @@ -774,7 +774,7 @@ pub unsafe fn _mm_andnot_si128(a: __m128i, b: __m128i) -> __m128i { /// Computes the bitwise OR of 128 bits (representing integer data) in `a` and /// `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_or_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_or_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(orps))] @@ -786,7 +786,7 @@ pub unsafe fn _mm_or_si128(a: __m128i, b: __m128i) -> __m128i { /// Computes the bitwise XOR of 128 bits (representing integer data) in `a` and /// `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_xor_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_xor_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(xorps))] @@ -797,7 +797,7 @@ pub unsafe fn _mm_xor_si128(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 8-bit integers in `a` and `b` for equality. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpeqb))] @@ -808,7 +808,7 @@ pub unsafe fn _mm_cmpeq_epi8(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 16-bit integers in `a` and `b` for equality. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpeqw))] @@ -819,7 +819,7 @@ pub unsafe fn _mm_cmpeq_epi16(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 32-bit integers in `a` and `b` for equality. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpeqd))] @@ -830,7 +830,7 @@ pub unsafe fn _mm_cmpeq_epi32(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 8-bit integers in `a` and `b` for greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpgtb))] @@ -841,7 +841,7 @@ pub unsafe fn _mm_cmpgt_epi8(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 16-bit integers in `a` and `b` for greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpgtw))] @@ -852,7 +852,7 @@ pub unsafe fn _mm_cmpgt_epi16(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 32-bit integers in `a` and `b` for greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpgtd))] @@ -863,7 +863,7 @@ pub unsafe fn _mm_cmpgt_epi32(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 8-bit integers in `a` and `b` for less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpgtb))] @@ -874,7 +874,7 @@ pub unsafe fn _mm_cmplt_epi8(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 16-bit integers in `a` and `b` for less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpgtw))] @@ -885,7 +885,7 @@ pub unsafe fn _mm_cmplt_epi16(a: __m128i, b: __m128i) -> __m128i { /// Compares packed 32-bit integers in `a` and `b` for less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pcmpgtd))] @@ -897,20 +897,20 @@ pub unsafe fn _mm_cmplt_epi32(a: __m128i, b: __m128i) -> __m128i { /// Converts the lower two packed 32-bit integers in `a` to packed /// double-precision (64-bit) floating-point elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi32_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi32_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtdq2pd))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_cvtepi32_pd(a: __m128i) -> __m128d { let a = a.as_i32x4(); - simd_cast::<i32x2, __m128d>(simd_shuffle2!(a, a, [0, 1])) + simd_cast::<i32x2, __m128d>(simd_shuffle!(a, a, [0, 1])) } /// Returns `a` with its lower element replaced by `b` after converting it to /// an `f64`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi32_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi32_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtsi2sd))] @@ -922,7 +922,7 @@ pub unsafe fn _mm_cvtsi32_sd(a: __m128d, b: i32) -> __m128d { /// Converts packed 32-bit integers in `a` to packed single-precision (32-bit) /// floating-point elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtepi32_ps) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtepi32_ps) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtdq2ps))] @@ -934,7 +934,7 @@ pub unsafe fn _mm_cvtepi32_ps(a: __m128i) -> __m128 { /// Converts packed single-precision (32-bit) floating-point elements in `a` /// to packed 32-bit integers. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtps_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtps_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtps2dq))] @@ -946,7 +946,7 @@ pub unsafe fn _mm_cvtps_epi32(a: __m128) -> __m128i { /// Returns a vector whose lowest element is `a` and all higher elements are /// `0`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi32_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi32_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, target_arch = "x86_64"), assert_instr(movd))] @@ -957,7 +957,7 @@ pub unsafe fn _mm_cvtsi32_si128(a: i32) -> __m128i { /// Returns the lowest element of `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi128_si32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi128_si32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movd))] @@ -969,7 +969,7 @@ pub unsafe fn _mm_cvtsi128_si32(a: __m128i) -> i32 { /// Sets packed 64-bit integers with the supplied values, from highest to /// lowest. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi64x) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi64x) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -980,7 +980,7 @@ pub unsafe fn _mm_set_epi64x(e1: i64, e0: i64) -> __m128i { /// Sets packed 32-bit integers with the supplied values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi32) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -991,7 +991,7 @@ pub unsafe fn _mm_set_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i { /// Sets packed 16-bit integers with the supplied values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi16) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1011,7 +1011,7 @@ pub unsafe fn _mm_set_epi16( /// Sets packed 8-bit integers with the supplied values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_epi8) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1042,7 +1042,7 @@ pub unsafe fn _mm_set_epi8( /// Broadcasts 64-bit integer `a` to all elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi64x) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi64x) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1053,7 +1053,7 @@ pub unsafe fn _mm_set1_epi64x(a: i64) -> __m128i { /// Broadcasts 32-bit integer `a` to all elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi32) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1064,7 +1064,7 @@ pub unsafe fn _mm_set1_epi32(a: i32) -> __m128i { /// Broadcasts 16-bit integer `a` to all elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi16) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1075,7 +1075,7 @@ pub unsafe fn _mm_set1_epi16(a: i16) -> __m128i { /// Broadcasts 8-bit integer `a` to all elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_epi8) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1086,7 +1086,7 @@ pub unsafe fn _mm_set1_epi8(a: i8) -> __m128i { /// Sets packed 32-bit integers with the supplied values in reverse order. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setr_epi32) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1097,7 +1097,7 @@ pub unsafe fn _mm_setr_epi32(e3: i32, e2: i32, e1: i32, e0: i32) -> __m128i { /// Sets packed 16-bit integers with the supplied values in reverse order. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setr_epi16) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1117,7 +1117,7 @@ pub unsafe fn _mm_setr_epi16( /// Sets packed 8-bit integers with the supplied values in reverse order. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setr_epi8) #[inline] #[target_feature(enable = "sse2")] // no particular instruction to test @@ -1148,7 +1148,7 @@ pub unsafe fn _mm_setr_epi8( /// Returns a vector with all elements set to zero. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setzero_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(xorps))] @@ -1159,7 +1159,7 @@ pub unsafe fn _mm_setzero_si128() -> __m128i { /// Loads 64-bit integer from memory into first element of returned vector. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadl_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadl_epi64) #[inline] #[target_feature(enable = "sse2")] // FIXME movsd on windows @@ -1181,7 +1181,7 @@ pub unsafe fn _mm_loadl_epi64(mem_addr: *const __m128i) -> __m128i { /// /// `mem_addr` must be aligned on a 16-byte boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movaps))] @@ -1194,7 +1194,7 @@ pub unsafe fn _mm_load_si128(mem_addr: *const __m128i) -> __m128i { /// /// `mem_addr` does not need to be aligned on any particular boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movups))] @@ -1218,7 +1218,7 @@ pub unsafe fn _mm_loadu_si128(mem_addr: *const __m128i) -> __m128i { /// `mem_addr` should correspond to a 128-bit memory location and does not need /// to be aligned on any particular boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_maskmoveu_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_maskmoveu_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(maskmovdqu))] @@ -1231,7 +1231,7 @@ pub unsafe fn _mm_maskmoveu_si128(a: __m128i, mask: __m128i, mem_addr: *mut i8) /// /// `mem_addr` must be aligned on a 16-byte boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movaps))] @@ -1244,7 +1244,7 @@ pub unsafe fn _mm_store_si128(mem_addr: *mut __m128i, a: __m128i) { /// /// `mem_addr` does not need to be aligned on any particular boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movups))] // FIXME movdqu expected @@ -1257,7 +1257,7 @@ pub unsafe fn _mm_storeu_si128(mem_addr: *mut __m128i, a: __m128i) { /// /// `mem_addr` does not need to be aligned on any particular boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storel_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storel_epi64) #[inline] #[target_feature(enable = "sse2")] // FIXME mov on windows, movlps on i686 @@ -1279,7 +1279,7 @@ pub unsafe fn _mm_storel_epi64(mem_addr: *mut __m128i, a: __m128i) { /// To minimize caching, the data is flagged as non-temporal (unlikely to be /// used again soon). /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_stream_si128) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movntps))] // FIXME movntdq @@ -1292,7 +1292,7 @@ pub unsafe fn _mm_stream_si128(mem_addr: *mut __m128i, a: __m128i) { /// To minimize caching, the data is flagged as non-temporal (unlikely to be /// used again soon). /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_si32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_stream_si32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movnti))] @@ -1304,7 +1304,7 @@ pub unsafe fn _mm_stream_si32(mem_addr: *mut i32, a: i32) { /// Returns a vector where the low element is extracted from `a` and its upper /// element is zero. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_move_epi64) #[inline] #[target_feature(enable = "sse2")] // FIXME movd on windows, movd on i686 @@ -1312,14 +1312,14 @@ pub unsafe fn _mm_stream_si32(mem_addr: *mut i32, a: i32) { #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_move_epi64(a: __m128i) -> __m128i { let zero = _mm_setzero_si128(); - let r: i64x2 = simd_shuffle2!(a.as_i64x2(), zero.as_i64x2(), [0, 2]); + let r: i64x2 = simd_shuffle!(a.as_i64x2(), zero.as_i64x2(), [0, 2]); transmute(r) } /// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers /// using signed saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packs_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packsswb))] @@ -1331,7 +1331,7 @@ pub unsafe fn _mm_packs_epi16(a: __m128i, b: __m128i) -> __m128i { /// Converts packed 32-bit integers from `a` and `b` to packed 16-bit integers /// using signed saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packs_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packs_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packssdw))] @@ -1343,7 +1343,7 @@ pub unsafe fn _mm_packs_epi32(a: __m128i, b: __m128i) -> __m128i { /// Converts packed 16-bit integers from `a` and `b` to packed 8-bit integers /// using unsigned saturation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_packus_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_packus_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(packuswb))] @@ -1354,33 +1354,33 @@ pub unsafe fn _mm_packus_epi16(a: __m128i, b: __m128i) -> __m128i { /// Returns the `imm8` element of `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_extract_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_extract_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pextrw, IMM8 = 7))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_extract_epi16<const IMM8: i32>(a: __m128i) -> i32 { - static_assert_imm3!(IMM8); + static_assert_uimm_bits!(IMM8, 3); simd_extract::<_, u16>(a.as_u16x8(), IMM8 as u32) as i32 } /// Returns a new vector where the `imm8` element of `a` is replaced with `i`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_insert_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_insert_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pinsrw, IMM8 = 7))] #[rustc_legacy_const_generics(2)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_insert_epi16<const IMM8: i32>(a: __m128i, i: i32) -> __m128i { - static_assert_imm3!(IMM8); + static_assert_uimm_bits!(IMM8, 3); transmute(simd_insert(a.as_i16x8(), IMM8 as u32, i as i16)) } /// Returns a mask of the most significant bit of each element in `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movemask_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movemask_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pmovmskb))] @@ -1393,19 +1393,19 @@ pub unsafe fn _mm_movemask_epi8(a: __m128i) -> i32 { /// Shuffles 32-bit integers in `a` using the control in `IMM8`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shuffle_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pshufd, IMM8 = 9))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_shuffle_epi32<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); let a = a.as_i32x4(); - let x: i32x4 = simd_shuffle4!( + let x: i32x4 = simd_shuffle!( a, a, - <const IMM8: i32> [ + [ IMM8 as u32 & 0b11, (IMM8 as u32 >> 2) & 0b11, (IMM8 as u32 >> 4) & 0b11, @@ -1421,19 +1421,19 @@ pub unsafe fn _mm_shuffle_epi32<const IMM8: i32>(a: __m128i) -> __m128i { /// Put the results in the high 64 bits of the returned vector, with the low 64 /// bits being copied from `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shufflehi_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shufflehi_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pshufhw, IMM8 = 9))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_shufflehi_epi16<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); let a = a.as_i16x8(); - let x: i16x8 = simd_shuffle8!( + let x: i16x8 = simd_shuffle!( a, a, - <const IMM8: i32> [ + [ 0, 1, 2, @@ -1453,19 +1453,19 @@ pub unsafe fn _mm_shufflehi_epi16<const IMM8: i32>(a: __m128i) -> __m128i { /// Put the results in the low 64 bits of the returned vector, with the high 64 /// bits being copied from `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shufflelo_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shufflelo_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(pshuflw, IMM8 = 9))] #[rustc_legacy_const_generics(1)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_shufflelo_epi16<const IMM8: i32>(a: __m128i) -> __m128i { - static_assert_imm8!(IMM8); + static_assert_uimm_bits!(IMM8, 8); let a = a.as_i16x8(); - let x: i16x8 = simd_shuffle8!( + let x: i16x8 = simd_shuffle!( a, a, - <const IMM8: i32> [ + [ IMM8 as u32 & 0b11, (IMM8 as u32 >> 2) & 0b11, (IMM8 as u32 >> 4) & 0b11, @@ -1481,13 +1481,13 @@ pub unsafe fn _mm_shufflelo_epi16<const IMM8: i32>(a: __m128i) -> __m128i { /// Unpacks and interleave 8-bit integers from the high half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpackhi_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(punpckhbw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpackhi_epi8(a: __m128i, b: __m128i) -> __m128i { - transmute::<i8x16, _>(simd_shuffle16!( + transmute::<i8x16, _>(simd_shuffle!( a.as_i8x16(), b.as_i8x16(), [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31], @@ -1496,47 +1496,47 @@ pub unsafe fn _mm_unpackhi_epi8(a: __m128i, b: __m128i) -> __m128i { /// Unpacks and interleave 16-bit integers from the high half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpackhi_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(punpckhwd))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpackhi_epi16(a: __m128i, b: __m128i) -> __m128i { - let x = simd_shuffle8!(a.as_i16x8(), b.as_i16x8(), [4, 12, 5, 13, 6, 14, 7, 15]); + let x = simd_shuffle!(a.as_i16x8(), b.as_i16x8(), [4, 12, 5, 13, 6, 14, 7, 15]); transmute::<i16x8, _>(x) } /// Unpacks and interleave 32-bit integers from the high half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpackhi_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(unpckhps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpackhi_epi32(a: __m128i, b: __m128i) -> __m128i { - transmute::<i32x4, _>(simd_shuffle4!(a.as_i32x4(), b.as_i32x4(), [2, 6, 3, 7])) + transmute::<i32x4, _>(simd_shuffle!(a.as_i32x4(), b.as_i32x4(), [2, 6, 3, 7])) } /// Unpacks and interleave 64-bit integers from the high half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpackhi_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(unpckhpd))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpackhi_epi64(a: __m128i, b: __m128i) -> __m128i { - transmute::<i64x2, _>(simd_shuffle2!(a.as_i64x2(), b.as_i64x2(), [1, 3])) + transmute::<i64x2, _>(simd_shuffle!(a.as_i64x2(), b.as_i64x2(), [1, 3])) } /// Unpacks and interleave 8-bit integers from the low half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi8) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_epi8) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(punpcklbw))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpacklo_epi8(a: __m128i, b: __m128i) -> __m128i { - transmute::<i8x16, _>(simd_shuffle16!( + transmute::<i8x16, _>(simd_shuffle!( a.as_i8x16(), b.as_i8x16(), [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23], @@ -1545,42 +1545,42 @@ pub unsafe fn _mm_unpacklo_epi8(a: __m128i, b: __m128i) -> __m128i { /// Unpacks and interleave 16-bit integers from the low half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi16) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_epi16) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(punpcklwd))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpacklo_epi16(a: __m128i, b: __m128i) -> __m128i { - let x = simd_shuffle8!(a.as_i16x8(), b.as_i16x8(), [0, 8, 1, 9, 2, 10, 3, 11]); + let x = simd_shuffle!(a.as_i16x8(), b.as_i16x8(), [0, 8, 1, 9, 2, 10, 3, 11]); transmute::<i16x8, _>(x) } /// Unpacks and interleave 32-bit integers from the low half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(unpcklps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpacklo_epi32(a: __m128i, b: __m128i) -> __m128i { - transmute::<i32x4, _>(simd_shuffle4!(a.as_i32x4(), b.as_i32x4(), [0, 4, 1, 5])) + transmute::<i32x4, _>(simd_shuffle!(a.as_i32x4(), b.as_i32x4(), [0, 4, 1, 5])) } /// Unpacks and interleave 64-bit integers from the low half of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_epi64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_epi64) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlhps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpacklo_epi64(a: __m128i, b: __m128i) -> __m128i { - transmute::<i64x2, _>(simd_shuffle2!(a.as_i64x2(), b.as_i64x2(), [0, 2])) + transmute::<i64x2, _>(simd_shuffle!(a.as_i64x2(), b.as_i64x2(), [0, 2])) } /// Returns a new vector with the low element of `a` replaced by the sum of the /// low elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(addsd))] @@ -1592,7 +1592,7 @@ pub unsafe fn _mm_add_sd(a: __m128d, b: __m128d) -> __m128d { /// Adds packed double-precision (64-bit) floating-point elements in `a` and /// `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_add_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(addpd))] @@ -1604,7 +1604,7 @@ pub unsafe fn _mm_add_pd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the result of /// diving the lower element of `a` by the lower element of `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_div_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(divsd))] @@ -1616,7 +1616,7 @@ pub unsafe fn _mm_div_sd(a: __m128d, b: __m128d) -> __m128d { /// Divide packed double-precision (64-bit) floating-point elements in `a` by /// packed elements in `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_div_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_div_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(divpd))] @@ -1628,7 +1628,7 @@ pub unsafe fn _mm_div_pd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the maximum /// of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(maxsd))] @@ -1640,7 +1640,7 @@ pub unsafe fn _mm_max_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the maximum values from corresponding elements in /// `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_max_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(maxpd))] @@ -1652,7 +1652,7 @@ pub unsafe fn _mm_max_pd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the minimum /// of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(minsd))] @@ -1664,7 +1664,7 @@ pub unsafe fn _mm_min_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the minimum values from corresponding elements in /// `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_min_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_min_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(minpd))] @@ -1676,7 +1676,7 @@ pub unsafe fn _mm_min_pd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by multiplying the /// low elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mul_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(mulsd))] @@ -1688,7 +1688,7 @@ pub unsafe fn _mm_mul_sd(a: __m128d, b: __m128d) -> __m128d { /// Multiplies packed double-precision (64-bit) floating-point elements in `a` /// and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_mul_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_mul_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(mulpd))] @@ -1700,7 +1700,7 @@ pub unsafe fn _mm_mul_pd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the square /// root of the lower element `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sqrt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(sqrtsd))] @@ -1711,7 +1711,7 @@ pub unsafe fn _mm_sqrt_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the square root of each of the values in `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sqrt_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(sqrtpd))] @@ -1723,7 +1723,7 @@ pub unsafe fn _mm_sqrt_pd(a: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by subtracting the /// low element by `b` from the low element of `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sub_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(subsd))] @@ -1735,7 +1735,7 @@ pub unsafe fn _mm_sub_sd(a: __m128d, b: __m128d) -> __m128d { /// Subtract packed double-precision (64-bit) floating-point elements in `b` /// from `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sub_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sub_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(subpd))] @@ -1747,7 +1747,7 @@ pub unsafe fn _mm_sub_pd(a: __m128d, b: __m128d) -> __m128d { /// Computes the bitwise AND of packed double-precision (64-bit) floating-point /// elements in `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_and_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_and_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(andps))] @@ -1760,7 +1760,7 @@ pub unsafe fn _mm_and_pd(a: __m128d, b: __m128d) -> __m128d { /// Computes the bitwise NOT of `a` and then AND with `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_andnot_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_andnot_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(andnps))] @@ -1773,7 +1773,7 @@ pub unsafe fn _mm_andnot_pd(a: __m128d, b: __m128d) -> __m128d { /// Computes the bitwise OR of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_or_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_or_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(orps))] @@ -1786,7 +1786,7 @@ pub unsafe fn _mm_or_pd(a: __m128d, b: __m128d) -> __m128d { /// Computes the bitwise XOR of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_xor_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_xor_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(xorps))] @@ -1800,7 +1800,7 @@ pub unsafe fn _mm_xor_pd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the equality /// comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpeqsd))] @@ -1812,7 +1812,7 @@ pub unsafe fn _mm_cmpeq_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the less-than /// comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpltsd))] @@ -1824,7 +1824,7 @@ pub unsafe fn _mm_cmplt_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// less-than-or-equal comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmple_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmplesd))] @@ -1836,7 +1836,7 @@ pub unsafe fn _mm_cmple_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// greater-than comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpltsd))] @@ -1848,7 +1848,7 @@ pub unsafe fn _mm_cmpgt_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// greater-than-or-equal comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpge_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmplesd))] @@ -1862,7 +1862,7 @@ pub unsafe fn _mm_cmpge_sd(a: __m128d, b: __m128d) -> __m128d { /// neither are equal to `NaN` then `0xFFFFFFFFFFFFFFFF` is used and `0` /// otherwise. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpord_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpord_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpordsd))] @@ -1875,7 +1875,7 @@ pub unsafe fn _mm_cmpord_sd(a: __m128d, b: __m128d) -> __m128d { /// comparing both of the lower elements of `a` and `b` to `NaN`. If either is /// equal to `NaN` then `0xFFFFFFFFFFFFFFFF` is used and `0` otherwise. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpunord_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpunord_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpunordsd))] @@ -1887,7 +1887,7 @@ pub unsafe fn _mm_cmpunord_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the not-equal /// comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpneq_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpneqsd))] @@ -1899,7 +1899,7 @@ pub unsafe fn _mm_cmpneq_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// not-less-than comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnlt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpnlt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnltsd))] @@ -1911,7 +1911,7 @@ pub unsafe fn _mm_cmpnlt_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// not-less-than-or-equal comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnle_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpnle_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnlesd))] @@ -1923,7 +1923,7 @@ pub unsafe fn _mm_cmpnle_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// not-greater-than comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpngt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpngt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnltsd))] @@ -1935,7 +1935,7 @@ pub unsafe fn _mm_cmpngt_sd(a: __m128d, b: __m128d) -> __m128d { /// Returns a new vector with the low element of `a` replaced by the /// not-greater-than-or-equal comparison of the lower elements of `a` and `b`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnge_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpnge_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnlesd))] @@ -1946,7 +1946,7 @@ pub unsafe fn _mm_cmpnge_sd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for equality. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpeq_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpeq_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpeqpd))] @@ -1957,7 +1957,7 @@ pub unsafe fn _mm_cmpeq_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmplt_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmplt_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpltpd))] @@ -1968,7 +1968,7 @@ pub unsafe fn _mm_cmplt_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for less-than-or-equal /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmple_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmple_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmplepd))] @@ -1979,7 +1979,7 @@ pub unsafe fn _mm_cmple_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpgt_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpgt_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpltpd))] @@ -1990,7 +1990,7 @@ pub unsafe fn _mm_cmpgt_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for greater-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpge_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpge_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmplepd))] @@ -2001,7 +2001,7 @@ pub unsafe fn _mm_cmpge_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` to see if neither is `NaN`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpord_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpord_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpordpd))] @@ -2012,7 +2012,7 @@ pub unsafe fn _mm_cmpord_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` to see if either is `NaN`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpunord_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpunord_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpunordpd))] @@ -2023,7 +2023,7 @@ pub unsafe fn _mm_cmpunord_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for not-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpneq_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpneq_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpneqpd))] @@ -2034,7 +2034,7 @@ pub unsafe fn _mm_cmpneq_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for not-less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnlt_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpnlt_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnltpd))] @@ -2045,7 +2045,7 @@ pub unsafe fn _mm_cmpnlt_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for not-less-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnle_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpnle_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnlepd))] @@ -2056,7 +2056,7 @@ pub unsafe fn _mm_cmpnle_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for not-greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpngt_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpngt_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnltpd))] @@ -2068,7 +2068,7 @@ pub unsafe fn _mm_cmpngt_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares corresponding elements in `a` and `b` for /// not-greater-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cmpnge_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cmpnge_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cmpnlepd))] @@ -2079,7 +2079,7 @@ pub unsafe fn _mm_cmpnge_pd(a: __m128d, b: __m128d) -> __m128d { /// Compares the lower element of `a` and `b` for equality. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comieq_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comieq_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(comisd))] @@ -2090,7 +2090,7 @@ pub unsafe fn _mm_comieq_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comilt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comilt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(comisd))] @@ -2101,7 +2101,7 @@ pub unsafe fn _mm_comilt_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for less-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comile_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comile_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(comisd))] @@ -2112,7 +2112,7 @@ pub unsafe fn _mm_comile_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comigt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comigt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(comisd))] @@ -2123,7 +2123,7 @@ pub unsafe fn _mm_comigt_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for greater-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comige_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comige_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(comisd))] @@ -2134,7 +2134,7 @@ pub unsafe fn _mm_comige_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for not-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_comineq_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_comineq_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(comisd))] @@ -2145,7 +2145,7 @@ pub unsafe fn _mm_comineq_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for equality. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomieq_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ucomieq_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(ucomisd))] @@ -2156,7 +2156,7 @@ pub unsafe fn _mm_ucomieq_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for less-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomilt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ucomilt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(ucomisd))] @@ -2167,7 +2167,7 @@ pub unsafe fn _mm_ucomilt_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for less-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomile_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ucomile_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(ucomisd))] @@ -2178,7 +2178,7 @@ pub unsafe fn _mm_ucomile_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for greater-than. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomigt_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ucomigt_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(ucomisd))] @@ -2189,7 +2189,7 @@ pub unsafe fn _mm_ucomigt_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for greater-than-or-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomige_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ucomige_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(ucomisd))] @@ -2200,7 +2200,7 @@ pub unsafe fn _mm_ucomige_sd(a: __m128d, b: __m128d) -> i32 { /// Compares the lower element of `a` and `b` for not-equal. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_ucomineq_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_ucomineq_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(ucomisd))] @@ -2212,7 +2212,7 @@ pub unsafe fn _mm_ucomineq_sd(a: __m128d, b: __m128d) -> i32 { /// Converts packed double-precision (64-bit) floating-point elements in `a` to /// packed single-precision (32-bit) floating-point elements /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_ps) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtpd_ps) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtpd2ps))] @@ -2225,7 +2225,7 @@ pub unsafe fn _mm_cvtpd_ps(a: __m128d) -> __m128 { /// packed /// double-precision (64-bit) floating-point elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtps_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtps_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtps2pd))] @@ -2237,7 +2237,7 @@ pub unsafe fn _mm_cvtps_pd(a: __m128) -> __m128d { /// Converts packed double-precision (64-bit) floating-point elements in `a` to /// packed 32-bit integers. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtpd_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtpd_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtpd2dq))] @@ -2249,7 +2249,7 @@ pub unsafe fn _mm_cvtpd_epi32(a: __m128d) -> __m128i { /// Converts the lower double-precision (64-bit) floating-point element in a to /// a 32-bit integer. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_si32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_si32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtsd2si))] @@ -2263,7 +2263,7 @@ pub unsafe fn _mm_cvtsd_si32(a: __m128d) -> i32 { /// the lower element of the return value, and copies the upper element from `a` /// to the upper element the return value. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_ss) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_ss) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtsd2ss))] @@ -2274,7 +2274,7 @@ pub unsafe fn _mm_cvtsd_ss(a: __m128, b: __m128d) -> __m128 { /// Returns the lower double-precision (64-bit) floating-point element of `a`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsd_f64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsd_f64) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2287,7 +2287,7 @@ pub unsafe fn _mm_cvtsd_f64(a: __m128d) -> f64 { /// the lower element of the return value, and copies the upper element from `a` /// to the upper element the return value. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvtss2sd))] @@ -2299,7 +2299,7 @@ pub unsafe fn _mm_cvtss_sd(a: __m128d, b: __m128) -> __m128d { /// Converts packed double-precision (64-bit) floating-point elements in `a` to /// packed 32-bit integers with truncation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttpd_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttpd_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvttpd2dq))] @@ -2311,7 +2311,7 @@ pub unsafe fn _mm_cvttpd_epi32(a: __m128d) -> __m128i { /// Converts the lower double-precision (64-bit) floating-point element in `a` /// to a 32-bit integer with truncation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttsd_si32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttsd_si32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvttsd2si))] @@ -2323,7 +2323,7 @@ pub unsafe fn _mm_cvttsd_si32(a: __m128d) -> i32 { /// Converts packed single-precision (32-bit) floating-point elements in `a` to /// packed 32-bit integers with truncation. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttps_epi32) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttps_epi32) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(cvttps2dq))] @@ -2335,7 +2335,7 @@ pub unsafe fn _mm_cvttps_epi32(a: __m128) -> __m128i { /// Copies double-precision (64-bit) floating-point element `a` to the lower /// element of the packed 64-bit return value. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_sd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2346,7 +2346,7 @@ pub unsafe fn _mm_set_sd(a: f64) -> __m128d { /// Broadcasts double-precision (64-bit) floating-point value a to all elements /// of the return value. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set1_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set1_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2357,7 +2357,7 @@ pub unsafe fn _mm_set1_pd(a: f64) -> __m128d { /// Broadcasts double-precision (64-bit) floating-point value a to all elements /// of the return value. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_pd1) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_pd1) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2368,7 +2368,7 @@ pub unsafe fn _mm_set_pd1(a: f64) -> __m128d { /// Sets packed double-precision (64-bit) floating-point elements in the return /// value with the supplied values. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_set_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_set_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2379,7 +2379,7 @@ pub unsafe fn _mm_set_pd(a: f64, b: f64) -> __m128d { /// Sets packed double-precision (64-bit) floating-point elements in the return /// value with the supplied values in reverse order. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setr_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setr_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2390,7 +2390,7 @@ pub unsafe fn _mm_setr_pd(a: f64, b: f64) -> __m128d { /// Returns packed double-precision (64-bit) floating-point elements with all /// zeros. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_setzero_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_setzero_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(xorps))] // FIXME xorpd expected @@ -2404,7 +2404,7 @@ pub unsafe fn _mm_setzero_pd() -> __m128d { /// The mask is stored in the 2 least significant bits of the return value. /// All other bits are set to `0`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_movemask_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_movemask_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movmskpd))] @@ -2418,7 +2418,7 @@ pub unsafe fn _mm_movemask_pd(a: __m128d) -> i32 { /// `mem_addr` must be aligned on a 16-byte boundary or a general-protection /// exception may be generated. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movaps))] @@ -2431,7 +2431,7 @@ pub unsafe fn _mm_load_pd(mem_addr: *const f64) -> __m128d { /// Loads a 64-bit double-precision value to the low element of a /// 128-bit integer vector and clears the upper element. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movsd))] @@ -2444,7 +2444,7 @@ pub unsafe fn _mm_load_sd(mem_addr: *const f64) -> __m128d { /// vector of `[2 x double]`. The low-order bits are copied from the low-order /// bits of the first operand. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadh_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadh_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movhps))] @@ -2457,7 +2457,7 @@ pub unsafe fn _mm_loadh_pd(a: __m128d, mem_addr: *const f64) -> __m128d { /// vector of `[2 x double]`. The high-order bits are copied from the /// high-order bits of the first operand. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadl_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadl_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movlps))] @@ -2471,7 +2471,7 @@ pub unsafe fn _mm_loadl_pd(a: __m128d, mem_addr: *const f64) -> __m128d { /// To minimize caching, the data is flagged as non-temporal (unlikely to be /// used again soon). /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_stream_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_stream_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movntps))] // FIXME movntpd @@ -2484,7 +2484,7 @@ pub unsafe fn _mm_stream_pd(mem_addr: *mut f64, a: __m128d) { /// Stores the lower 64 bits of a 128-bit vector of `[2 x double]` to a /// memory location. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlps))] @@ -2497,7 +2497,7 @@ pub unsafe fn _mm_store_sd(mem_addr: *mut f64, a: __m128d) { /// floating-point elements) from `a` into memory. `mem_addr` must be aligned /// on a 16-byte boundary or a general-protection exception may be generated. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movaps))] @@ -2511,7 +2511,7 @@ pub unsafe fn _mm_store_pd(mem_addr: *mut f64, a: __m128d) { /// floating-point elements) from `a` into memory. /// `mem_addr` does not need to be aligned on any particular boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeu_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeu_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movups))] // FIXME movupd expected @@ -2524,13 +2524,13 @@ pub unsafe fn _mm_storeu_pd(mem_addr: *mut f64, a: __m128d) { /// into 2 contiguous elements in memory. `mem_addr` must be aligned on a /// 16-byte boundary or a general-protection exception may be generated. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store1_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store1_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] #[allow(clippy::cast_ptr_alignment)] pub unsafe fn _mm_store1_pd(mem_addr: *mut f64, a: __m128d) { - let b: __m128d = simd_shuffle2!(a, a, [0, 0]); + let b: __m128d = simd_shuffle!(a, a, [0, 0]); *(mem_addr as *mut __m128d) = b; } @@ -2538,13 +2538,13 @@ pub unsafe fn _mm_store1_pd(mem_addr: *mut f64, a: __m128d) { /// into 2 contiguous elements in memory. `mem_addr` must be aligned on a /// 16-byte boundary or a general-protection exception may be generated. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_store_pd1) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_store_pd1) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] #[allow(clippy::cast_ptr_alignment)] pub unsafe fn _mm_store_pd1(mem_addr: *mut f64, a: __m128d) { - let b: __m128d = simd_shuffle2!(a, a, [0, 0]); + let b: __m128d = simd_shuffle!(a, a, [0, 0]); *(mem_addr as *mut __m128d) = b; } @@ -2553,20 +2553,20 @@ pub unsafe fn _mm_store_pd1(mem_addr: *mut f64, a: __m128d) { /// `mem_addr` must be aligned on a 16-byte boundary or a general-protection /// exception may be generated. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storer_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storer_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] #[allow(clippy::cast_ptr_alignment)] pub unsafe fn _mm_storer_pd(mem_addr: *mut f64, a: __m128d) { - let b: __m128d = simd_shuffle2!(a, a, [1, 0]); + let b: __m128d = simd_shuffle!(a, a, [1, 0]); *(mem_addr as *mut __m128d) = b; } /// Stores the upper 64 bits of a 128-bit vector of `[2 x double]` to a /// memory location. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storeh_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storeh_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movhps))] @@ -2578,7 +2578,7 @@ pub unsafe fn _mm_storeh_pd(mem_addr: *mut f64, a: __m128d) { /// Stores the lower 64 bits of a 128-bit vector of `[2 x double]` to a /// memory location. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_storel_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_storel_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlps))] @@ -2590,7 +2590,7 @@ pub unsafe fn _mm_storel_pd(mem_addr: *mut f64, a: __m128d) { /// Loads a double-precision (64-bit) floating-point element from memory /// into both elements of returned vector. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load1_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load1_pd) #[inline] #[target_feature(enable = "sse2")] // #[cfg_attr(test, assert_instr(movapd))] // FIXME LLVM uses different codegen @@ -2603,7 +2603,7 @@ pub unsafe fn _mm_load1_pd(mem_addr: *const f64) -> __m128d { /// Loads a double-precision (64-bit) floating-point element from memory /// into both elements of returned vector. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_load_pd1) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_load_pd1) #[inline] #[target_feature(enable = "sse2")] // #[cfg_attr(test, assert_instr(movapd))] // FIXME same as _mm_load1_pd @@ -2616,21 +2616,21 @@ pub unsafe fn _mm_load_pd1(mem_addr: *const f64) -> __m128d { /// the returned vector in reverse order. `mem_addr` must be aligned on a /// 16-byte boundary or a general-protection exception may be generated. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadr_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadr_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movaps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_loadr_pd(mem_addr: *const f64) -> __m128d { let a = _mm_load_pd(mem_addr); - simd_shuffle2!(a, a, [1, 0]) + simd_shuffle!(a, a, [1, 0]) } /// Loads 128-bits (composed of 2 packed double-precision (64-bit) /// floating-point elements) from memory into the returned vector. /// `mem_addr` does not need to be aligned on any particular boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_loadu_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_loadu_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movups))] @@ -2649,22 +2649,22 @@ pub unsafe fn _mm_loadu_pd(mem_addr: *const f64) -> __m128d { /// 128-bit vector parameters of `[2 x double]`, using the immediate-value /// parameter as a specifier. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_shuffle_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_shuffle_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(shufps, MASK = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_shuffle_pd<const MASK: i32>(a: __m128d, b: __m128d) -> __m128d { - static_assert_imm8!(MASK); - simd_shuffle2!(a, b, <const MASK: i32> [MASK as u32 & 0b1, ((MASK as u32 >> 1) & 0b1) + 2]) + static_assert_uimm_bits!(MASK, 8); + simd_shuffle!(a, b, [MASK as u32 & 0b1, ((MASK as u32 >> 1) & 0b1) + 2]) } /// Constructs a 128-bit floating-point vector of `[2 x double]`. The lower /// 64 bits are set to the lower 64 bits of the second parameter. The upper /// 64 bits are set to the upper 64 bits of the first parameter. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_move_sd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_move_sd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(movsd))] @@ -2676,7 +2676,7 @@ pub unsafe fn _mm_move_sd(a: __m128d, b: __m128d) -> __m128d { /// Casts a 128-bit floating-point vector of `[2 x double]` into a 128-bit /// floating-point vector of `[4 x float]`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_ps) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_castpd_ps) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2687,7 +2687,7 @@ pub unsafe fn _mm_castpd_ps(a: __m128d) -> __m128 { /// Casts a 128-bit floating-point vector of `[2 x double]` into a 128-bit /// integer vector. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castpd_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_castpd_si128) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2698,7 +2698,7 @@ pub unsafe fn _mm_castpd_si128(a: __m128d) -> __m128i { /// Casts a 128-bit floating-point vector of `[4 x float]` into a 128-bit /// floating-point vector of `[2 x double]`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_castps_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2709,7 +2709,7 @@ pub unsafe fn _mm_castps_pd(a: __m128) -> __m128d { /// Casts a 128-bit floating-point vector of `[4 x float]` into a 128-bit /// integer vector. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castps_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_castps_si128) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2720,7 +2720,7 @@ pub unsafe fn _mm_castps_si128(a: __m128) -> __m128i { /// Casts a 128-bit integer vector into a 128-bit floating-point vector /// of `[2 x double]`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_castsi128_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2731,7 +2731,7 @@ pub unsafe fn _mm_castsi128_pd(a: __m128i) -> __m128d { /// Casts a 128-bit integer vector into a 128-bit floating-point vector /// of `[4 x float]`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_castsi128_ps) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_castsi128_ps) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2741,7 +2741,7 @@ pub unsafe fn _mm_castsi128_ps(a: __m128i) -> __m128 { /// Returns vector of type __m128d with undefined elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_undefined_pd) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2751,7 +2751,7 @@ pub unsafe fn _mm_undefined_pd() -> __m128d { /// Returns vector of type __m128i with undefined elements. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_undefined_si128) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_undefined_si128) #[inline] #[target_feature(enable = "sse2")] #[stable(feature = "simd_x86", since = "1.27.0")] @@ -2766,13 +2766,13 @@ pub unsafe fn _mm_undefined_si128() -> __m128i { /// input * The `[63:0]` bits are copied from the `[127:64]` bits of the first /// input /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpackhi_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpackhi_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(test, assert_instr(unpckhpd))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d { - simd_shuffle2!(a, b, [1, 3]) + simd_shuffle!(a, b, [1, 3]) } /// The resulting `__m128d` element is composed by the high-order values of @@ -2781,13 +2781,13 @@ pub unsafe fn _mm_unpackhi_pd(a: __m128d, b: __m128d) -> __m128d { /// * The `[127:64]` bits are copied from the `[63:0]` bits of the second input /// * The `[63:0]` bits are copied from the `[63:0]` bits of the first input /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_unpacklo_pd) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_unpacklo_pd) #[inline] #[target_feature(enable = "sse2")] #[cfg_attr(all(test, not(target_os = "windows")), assert_instr(movlhps))] #[stable(feature = "simd_x86", since = "1.27.0")] pub unsafe fn _mm_unpacklo_pd(a: __m128d, b: __m128d) -> __m128d { - simd_shuffle2!(a, b, [0, 2]) + simd_shuffle!(a, b, [0, 2]) } #[allow(improper_ctypes)] |