diff options
Diffstat (limited to 'library/stdarch/crates/core_arch/src/x86/xsave.rs')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/x86/xsave.rs | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/library/stdarch/crates/core_arch/src/x86/xsave.rs b/library/stdarch/crates/core_arch/src/x86/xsave.rs index 30f807e44..6cdddcfce 100644 --- a/library/stdarch/crates/core_arch/src/x86/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86/xsave.rs @@ -33,7 +33,7 @@ extern "C" { /// The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of /// Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsave) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsave) #[inline] #[target_feature(enable = "xsave")] #[cfg_attr(test, assert_instr(xsave))] @@ -49,7 +49,7 @@ pub unsafe fn _xsave(mem_addr: *mut u8, save_mask: u64) { /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte /// boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstor) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xrstor) #[inline] #[target_feature(enable = "xsave")] #[cfg_attr(test, assert_instr(xrstor))] @@ -69,7 +69,7 @@ pub const _XCR_XFEATURE_ENABLED_MASK: u32 = 0; /// /// Currently only `XFEATURE_ENABLED_MASK` `XCR` is supported. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsetbv) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsetbv) #[inline] #[target_feature(enable = "xsave")] #[cfg_attr(test, assert_instr(xsetbv))] @@ -81,7 +81,7 @@ pub unsafe fn _xsetbv(a: u32, val: u64) { /// Reads the contents of the extended control register `XCR` /// specified in `xcr_no`. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xgetbv) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xgetbv) #[inline] #[target_feature(enable = "xsave")] #[cfg_attr(test, assert_instr(xgetbv))] @@ -98,7 +98,7 @@ pub unsafe fn _xgetbv(xcr_no: u32) -> u64 { /// the manner in which data is saved. The performance of this instruction will /// be equal to or better than using the `XSAVE` instruction. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaveopt) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsaveopt) #[inline] #[target_feature(enable = "xsave,xsaveopt")] #[cfg_attr(test, assert_instr(xsaveopt))] @@ -114,7 +114,7 @@ pub unsafe fn _xsaveopt(mem_addr: *mut u8, save_mask: u64) { /// use init optimization. State is saved based on bits `[62:0]` in `save_mask` /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsavec) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsavec) #[inline] #[target_feature(enable = "xsave,xsavec")] #[cfg_attr(test, assert_instr(xsavec))] @@ -131,7 +131,7 @@ pub unsafe fn _xsavec(mem_addr: *mut u8, save_mask: u64) { /// modified optimization. State is saved based on bits `[62:0]` in `save_mask` /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaves) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsaves) #[inline] #[target_feature(enable = "xsave,xsaves")] #[cfg_attr(test, assert_instr(xsaves))] @@ -150,7 +150,7 @@ pub unsafe fn _xsaves(mem_addr: *mut u8, save_mask: u64) { /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte /// boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstors) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xrstors) #[inline] #[target_feature(enable = "xsave,xsaves")] #[cfg_attr(test, assert_instr(xrstors))] |