diff options
Diffstat (limited to 'library/stdarch/crates/core_arch/src/x86_64/sse.rs')
| -rw-r--r-- | library/stdarch/crates/core_arch/src/x86_64/sse.rs | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/library/stdarch/crates/core_arch/src/x86_64/sse.rs b/library/stdarch/crates/core_arch/src/x86_64/sse.rs index ca6799c90..cdadc277d 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/sse.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/sse.rs @@ -25,7 +25,7 @@ extern "C" { /// /// This corresponds to the `CVTSS2SI` instruction (with 64 bit output). /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtss_si64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtss_si64) #[inline] #[target_feature(enable = "sse")] #[cfg_attr(test, assert_instr(cvtss2si))] @@ -44,7 +44,7 @@ pub unsafe fn _mm_cvtss_si64(a: __m128) -> i64 { /// /// This corresponds to the `CVTTSS2SI` instruction (with 64 bit output). /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvttss_si64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvttss_si64) #[inline] #[target_feature(enable = "sse")] #[cfg_attr(test, assert_instr(cvttss2si))] @@ -59,7 +59,7 @@ pub unsafe fn _mm_cvttss_si64(a: __m128) -> i64 { /// This intrinsic corresponds to the `CVTSI2SS` instruction (with 64 bit /// input). /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_cvtsi64_ss) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_cvtsi64_ss) #[inline] #[target_feature(enable = "sse")] #[cfg_attr(test, assert_instr(cvtsi2ss))] |