diff options
Diffstat (limited to 'library/stdarch/crates/core_arch/src/x86_64/xsave.rs')
-rw-r--r-- | library/stdarch/crates/core_arch/src/x86_64/xsave.rs | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs index 2afd3e433..7a6ccda90 100644 --- a/library/stdarch/crates/core_arch/src/x86_64/xsave.rs +++ b/library/stdarch/crates/core_arch/src/x86_64/xsave.rs @@ -30,7 +30,7 @@ extern "C" { /// The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of /// Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsave64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsave64) #[inline] #[target_feature(enable = "xsave")] #[cfg_attr(test, assert_instr(xsave64))] @@ -46,7 +46,7 @@ pub unsafe fn _xsave64(mem_addr: *mut u8, save_mask: u64) { /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte /// boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstor64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xrstor64) #[inline] #[target_feature(enable = "xsave")] #[cfg_attr(test, assert_instr(xrstor64))] @@ -63,7 +63,7 @@ pub unsafe fn _xrstor64(mem_addr: *const u8, rs_mask: u64) { /// the manner in which data is saved. The performance of this instruction will /// be equal to or better than using the `XSAVE64` instruction. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaveopt64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsaveopt64) #[inline] #[target_feature(enable = "xsave,xsaveopt")] #[cfg_attr(test, assert_instr(xsaveopt64))] @@ -79,7 +79,7 @@ pub unsafe fn _xsaveopt64(mem_addr: *mut u8, save_mask: u64) { /// use init optimization. State is saved based on bits `[62:0]` in `save_mask` /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsavec64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsavec64) #[inline] #[target_feature(enable = "xsave,xsavec")] #[cfg_attr(test, assert_instr(xsavec64))] @@ -96,7 +96,7 @@ pub unsafe fn _xsavec64(mem_addr: *mut u8, save_mask: u64) { /// modified optimization. State is saved based on bits `[62:0]` in `save_mask` /// and `XCR0`. `mem_addr` must be aligned on a 64-byte boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xsaves64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xsaves64) #[inline] #[target_feature(enable = "xsave,xsaves")] #[cfg_attr(test, assert_instr(xsaves64))] @@ -115,7 +115,7 @@ pub unsafe fn _xsaves64(mem_addr: *mut u8, save_mask: u64) { /// `mem_addr.HEADER.XSTATE_BV`. `mem_addr` must be aligned on a 64-byte /// boundary. /// -/// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_xrstors64) +/// [Intel's documentation](https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_xrstors64) #[inline] #[target_feature(enable = "xsave,xsaves")] #[cfg_attr(test, assert_instr(xrstors64))] |