1 files changed, 24 insertions, 14 deletions
diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs
index e9586eace..b2db52c89 100644
--- a/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs
+++ b/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs
@@ -19,7 +19,7 @@ macro_rules! aarch64_128_neon_impl {
                 $vmax(crate::mem::transmute(self)) != 0
             }
         }
-    }
+    };
 }
 
 /// 64-bit wide vectors
@@ -35,9 +35,7 @@ macro_rules! aarch64_64_neon_impl {
                     halves: ($id, $id),
                     vec: $vec128,
                 }
-                U {
-                    halves: (self, self),
-                }.vec.all()
+                U { halves: (self, self) }.vec.all()
             }
         }
         impl Any for $id {
@@ -48,9 +46,7 @@ macro_rules! aarch64_64_neon_impl {
                     halves: ($id, $id),
                     vec: $vec128,
                 }
-                U {
-                    halves: (self, self),
-                }.vec.any()
+                U { halves: (self, self) }.vec.any()
             }
         }
     };
@@ -59,13 +55,27 @@ macro_rules! aarch64_64_neon_impl {
 /// Mask reduction implementation for `aarch64` targets
 macro_rules! impl_mask_reductions {
     // 64-bit wide masks
-    (m8x8) => { aarch64_64_neon_impl!(m8x8, m8x16); };
-    (m16x4) => { aarch64_64_neon_impl!(m16x4, m16x8); };
-    (m32x2) => { aarch64_64_neon_impl!(m32x2, m32x4); };
+    (m8x8) => {
+        aarch64_64_neon_impl!(m8x8, m8x16);
+    };
+    (m16x4) => {
+        aarch64_64_neon_impl!(m16x4, m16x8);
+    };
+    (m32x2) => {
+        aarch64_64_neon_impl!(m32x2, m32x4);
+    };
     // 128-bit wide masks
-    (m8x16) => { aarch64_128_neon_impl!(m8x16, vminvq_u8, vmaxvq_u8); };
-    (m16x8) => { aarch64_128_neon_impl!(m16x8, vminvq_u16, vmaxvq_u16); };
-    (m32x4) => { aarch64_128_neon_impl!(m32x4, vminvq_u32, vmaxvq_u32); };
+    (m8x16) => {
+        aarch64_128_neon_impl!(m8x16, vminvq_u8, vmaxvq_u8);
+    };
+    (m16x8) => {
+        aarch64_128_neon_impl!(m16x8, vminvq_u16, vmaxvq_u16);
+    };
+    (m32x4) => {
+        aarch64_128_neon_impl!(m32x4, vminvq_u32, vmaxvq_u32);
+    };
     // Fallback to LLVM's default code-generation:
-    ($id:ident) => { fallback_impl!($id); };
+    ($id:ident) => {
+        fallback_impl!($id);
+    };
 }