From 218caa410aa38c29984be31a5229b9fa717560ee Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 17 Apr 2024 14:19:13 +0200 Subject: Merging upstream version 1.68.2+dfsg1. Signed-off-by: Daniel Baumann --- compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs') diff --git a/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs b/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs index 51fce8c85..14f5e9187 100644 --- a/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs +++ b/compiler/rustc_codegen_cranelift/src/intrinsics/simd.rs @@ -112,10 +112,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>( _ => unreachable!(), }; - let ty = fx.clif_type(res_lane_ty).unwrap(); - - let res_lane = fx.bcx.ins().bint(ty, res_lane); - fx.bcx.ins().ineg(res_lane) + bool_to_zero_or_max_uint(fx, res_lane_ty, res_lane) }); } @@ -716,7 +713,7 @@ pub(super) fn codegen_simd_intrinsic_call<'tcx>( let res_type = Type::int_with_byte_size(u16::try_from(expected_bytes).unwrap()).unwrap(); - let mut res = fx.bcx.ins().iconst(res_type, 0); + let mut res = type_zero_value(&mut fx.bcx, res_type); let lanes = match fx.tcx.sess.target.endian { Endian::Big => Box::new(0..lane_count) as Box>, -- cgit v1.2.3