From 218caa410aa38c29984be31a5229b9fa717560ee Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 17 Apr 2024 14:19:13 +0200 Subject: Merging upstream version 1.68.2+dfsg1. Signed-off-by: Daniel Baumann --- compiler/rustc_target/src/asm/aarch64.rs | 2 +- compiler/rustc_target/src/asm/arm.rs | 2 +- compiler/rustc_target/src/asm/mod.rs | 16 ++++++++-------- compiler/rustc_target/src/asm/x86.rs | 30 +++++++++++++++--------------- 4 files changed, 25 insertions(+), 25 deletions(-) (limited to 'compiler/rustc_target/src/asm') diff --git a/compiler/rustc_target/src/asm/aarch64.rs b/compiler/rustc_target/src/asm/aarch64.rs index 62a0f9fb0..28493c770 100644 --- a/compiler/rustc_target/src/asm/aarch64.rs +++ b/compiler/rustc_target/src/asm/aarch64.rs @@ -195,6 +195,6 @@ impl AArch64InlineAsmReg { (modifier.unwrap_or('v'), self as u32 - Self::v0 as u32) }; assert!(index < 32); - write!(out, "{}{}", prefix, index) + write!(out, "{prefix}{index}") } } diff --git a/compiler/rustc_target/src/asm/arm.rs b/compiler/rustc_target/src/asm/arm.rs index 0db3eb6fc..ec7429a30 100644 --- a/compiler/rustc_target/src/asm/arm.rs +++ b/compiler/rustc_target/src/asm/arm.rs @@ -249,7 +249,7 @@ impl ArmInlineAsmReg { let index = self as u32 - Self::q0 as u32; assert!(index < 16); let index = index * 2 + (modifier == 'f') as u32; - write!(out, "d{}", index) + write!(out, "d{index}") } else { out.write_str(self.name()) } diff --git a/compiler/rustc_target/src/asm/mod.rs b/compiler/rustc_target/src/asm/mod.rs index 65d2cd64b..70cd883be 100644 --- a/compiler/rustc_target/src/asm/mod.rs +++ b/compiler/rustc_target/src/asm/mod.rs @@ -462,7 +462,7 @@ impl InlineAsmRegClass { } /// Returns a suggested template modifier to use for this type and an - /// example of a register named formatted with it. + /// example of a register named formatted with it. /// /// Such suggestions are useful if a type smaller than the full register /// size is used and a modifier can be used to point to the subregister of @@ -679,13 +679,13 @@ impl fmt::Display for InlineAsmType { Self::I128 => f.write_str("i128"), Self::F32 => f.write_str("f32"), Self::F64 => f.write_str("f64"), - Self::VecI8(n) => write!(f, "i8x{}", n), - Self::VecI16(n) => write!(f, "i16x{}", n), - Self::VecI32(n) => write!(f, "i32x{}", n), - Self::VecI64(n) => write!(f, "i64x{}", n), - Self::VecI128(n) => write!(f, "i128x{}", n), - Self::VecF32(n) => write!(f, "f32x{}", n), - Self::VecF64(n) => write!(f, "f64x{}", n), + Self::VecI8(n) => write!(f, "i8x{n}"), + Self::VecI16(n) => write!(f, "i16x{n}"), + Self::VecI32(n) => write!(f, "i32x{n}"), + Self::VecI64(n) => write!(f, "i64x{n}"), + Self::VecI128(n) => write!(f, "i128x{n}"), + Self::VecF32(n) => write!(f, "f32x{n}"), + Self::VecF64(n) => write!(f, "f64x{n}"), } } } diff --git a/compiler/rustc_target/src/asm/x86.rs b/compiler/rustc_target/src/asm/x86.rs index 238c36509..5eae07f14 100644 --- a/compiler/rustc_target/src/asm/x86.rs +++ b/compiler/rustc_target/src/asm/x86.rs @@ -357,28 +357,28 @@ impl X86InlineAsmReg { if self as u32 <= Self::dx as u32 { let root = ['a', 'b', 'c', 'd'][self as usize - Self::ax as usize]; match modifier.unwrap_or(reg_default_modifier) { - 'l' => write!(out, "{}l", root), - 'h' => write!(out, "{}h", root), - 'x' => write!(out, "{}x", root), - 'e' => write!(out, "e{}x", root), - 'r' => write!(out, "r{}x", root), + 'l' => write!(out, "{root}l"), + 'h' => write!(out, "{root}h"), + 'x' => write!(out, "{root}x"), + 'e' => write!(out, "e{root}x"), + 'r' => write!(out, "r{root}x"), _ => unreachable!(), } } else if self as u32 <= Self::di as u32 { let root = self.name(); match modifier.unwrap_or(reg_default_modifier) { - 'l' => write!(out, "{}l", root), - 'x' => write!(out, "{}", root), - 'e' => write!(out, "e{}", root), - 'r' => write!(out, "r{}", root), + 'l' => write!(out, "{root}l"), + 'x' => write!(out, "{root}"), + 'e' => write!(out, "e{root}"), + 'r' => write!(out, "r{root}"), _ => unreachable!(), } } else if self as u32 <= Self::r15 as u32 { let root = self.name(); match modifier.unwrap_or(reg_default_modifier) { - 'l' => write!(out, "{}b", root), - 'x' => write!(out, "{}w", root), - 'e' => write!(out, "{}d", root), + 'l' => write!(out, "{root}b"), + 'x' => write!(out, "{root}w"), + 'e' => write!(out, "{root}d"), 'r' => out.write_str(root), _ => unreachable!(), } @@ -387,15 +387,15 @@ impl X86InlineAsmReg { } else if self as u32 <= Self::xmm15 as u32 { let prefix = modifier.unwrap_or('x'); let index = self as u32 - Self::xmm0 as u32; - write!(out, "{}{}", prefix, index) + write!(out, "{prefix}{index}") } else if self as u32 <= Self::ymm15 as u32 { let prefix = modifier.unwrap_or('y'); let index = self as u32 - Self::ymm0 as u32; - write!(out, "{}{}", prefix, index) + write!(out, "{prefix}{index}") } else if self as u32 <= Self::zmm31 as u32 { let prefix = modifier.unwrap_or('z'); let index = self as u32 - Self::zmm0 as u32; - write!(out, "{}{}", prefix, index) + write!(out, "{prefix}{index}") } else { out.write_str(self.name()) } -- cgit v1.2.3