From ef24de24a82fe681581cc130f342363c47c0969a Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Fri, 7 Jun 2024 07:48:48 +0200 Subject: Merging upstream version 1.75.0+dfsg1. Signed-off-by: Daniel Baumann --- .../rustc_target/src/spec/thumbv6m_none_eabi.rs | 25 ---------------------- 1 file changed, 25 deletions(-) delete mode 100644 compiler/rustc_target/src/spec/thumbv6m_none_eabi.rs (limited to 'compiler/rustc_target/src/spec/thumbv6m_none_eabi.rs') diff --git a/compiler/rustc_target/src/spec/thumbv6m_none_eabi.rs b/compiler/rustc_target/src/spec/thumbv6m_none_eabi.rs deleted file mode 100644 index c9bb0112f..000000000 --- a/compiler/rustc_target/src/spec/thumbv6m_none_eabi.rs +++ /dev/null @@ -1,25 +0,0 @@ -// Targets the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture) - -use crate::spec::{Target, TargetOptions}; - -pub fn target() -> Target { - Target { - llvm_target: "thumbv6m-none-eabi".into(), - pointer_width: 32, - data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), - arch: "arm".into(), - - options: TargetOptions { - abi: "eabi".into(), - // The ARMv6-M architecture doesn't support unaligned loads/stores so we disable them - // with +strict-align. - // Also force-enable 32-bit atomics, which allows the use of atomic load/store only. - // The resulting atomics are ABI incompatible with atomics backed by libatomic. - features: "+strict-align,+atomics-32".into(), - // There are no atomic CAS instructions available in the instruction set of the ARMv6-M - // architecture - atomic_cas: false, - ..super::thumb_base::opts() - }, - } -} -- cgit v1.2.3