From 698f8c2f01ea549d77d7dc3338a12e04c11057b9 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 17 Apr 2024 14:02:58 +0200 Subject: Adding upstream version 1.64.0+dfsg1. Signed-off-by: Daniel Baumann --- .../src/spec/thumbv8m_main_none_eabihf.rs | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 compiler/rustc_target/src/spec/thumbv8m_main_none_eabihf.rs (limited to 'compiler/rustc_target/src/spec/thumbv8m_main_none_eabihf.rs') diff --git a/compiler/rustc_target/src/spec/thumbv8m_main_none_eabihf.rs b/compiler/rustc_target/src/spec/thumbv8m_main_none_eabihf.rs new file mode 100644 index 000000000..86c25f9e4 --- /dev/null +++ b/compiler/rustc_target/src/spec/thumbv8m_main_none_eabihf.rs @@ -0,0 +1,25 @@ +// Targets the Cortex-M33 processor (Armv8-M Mainline architecture profile), +// with the Floating Point extension. + +use crate::spec::{Target, TargetOptions}; + +pub fn target() -> Target { + Target { + llvm_target: "thumbv8m.main-none-eabihf".into(), + pointer_width: 32, + data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(), + arch: "arm".into(), + + options: TargetOptions { + abi: "eabihf".into(), + // If the Floating Point extension is implemented in the Cortex-M33 + // processor, the Cortex-M33 Technical Reference Manual states that + // the FPU uses the FPv5 architecture, single-precision instructions + // and 16 D registers. + // These parameters map to the following LLVM features. + features: "+fp-armv8,-fp64,-d32".into(), + max_atomic_width: Some(32), + ..super::thumb_base::opts() + }, + } +} -- cgit v1.2.3