Technologies | NEON Intrinsics Reference

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int8x8_t vadd_s8 (int8x8_t a, int8x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vaddq_s8 (int8x16_t a, int8x16_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vadd_s16 (int16x4_t a, int16x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddq_s16 (int16x8_t a, int16x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vadd_s32 (int32x2_t a, int32x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddq_s32 (int32x4_t a, int32x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vadd_s64 (int64x1_t a, int64x1_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddq_s64 (int64x2_t a, int64x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vadd_u8 (uint8x8_t a, uint8x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vaddq_u8 (uint8x16_t a, uint8x16_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vadd_u16 (uint16x4_t a, uint16x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddq_u16 (uint16x8_t a, uint16x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vadd_u32 (uint32x2_t a, uint32x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddq_u32 (uint32x4_t a, uint32x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vadd_u64 (uint64x1_t a, uint64x1_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddq_u64 (uint64x2_t a, uint64x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vadd_f32 (float32x2_t a, float32x2_t b)Floating-point add

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vaddq_f32 (float32x4_t a, float32x4_t b)Floating-point add

Description

A64 Instruction

FADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vadd_f64 (float64x1_t a, float64x1_t b)Floating-point add

Description

A64 Instruction

FADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vaddq_f64 (float64x2_t a, float64x2_t b)Floating-point add

Description

A64 Instruction

FADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int64_t vaddd_s64 (int64_t a, int64_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint64_t vaddd_u64 (uint64_t a, uint64_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vaddl_s8 (int8x8_t a, int8x8_t b)Signed add long

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

A64 Instruction

SADDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddl_s16 (int16x4_t a, int16x4_t b)Signed add long

Description

A64 Instruction

SADDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddl_s32 (int32x2_t a, int32x2_t b)Signed add long

Description

A64 Instruction

SADDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddl_u8 (uint8x8_t a, uint8x8_t b)Unsigned add long

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

A64 Instruction

UADDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddl_u16 (uint16x4_t a, uint16x4_t b)Unsigned add long

Description

A64 Instruction

UADDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddl_u32 (uint32x2_t a, uint32x2_t b)Unsigned add long

Description

A64 Instruction

UADDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddl_high_s8 (int8x16_t a, int8x16_t b)Signed add long

Description

A64 Instruction

SADDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vaddl_high_s16 (int16x8_t a, int16x8_t b)Signed add long

Description

A64 Instruction

SADDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vaddl_high_s32 (int32x4_t a, int32x4_t b)Signed add long

Description

A64 Instruction

SADDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vaddl_high_u8 (uint8x16_t a, uint8x16_t b)Unsigned add long

Description

A64 Instruction

UADDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vaddl_high_u16 (uint16x8_t a, uint16x8_t b)Unsigned add long

Description

A64 Instruction

UADDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vaddl_high_u32 (uint32x4_t a, uint32x4_t b)Unsigned add long

Description

A64 Instruction

UADDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vaddw_s8 (int16x8_t a, int8x8_t b)Signed add wide

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

A64 Instruction

SADDW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddw_s16 (int32x4_t a, int16x4_t b)Signed add wide

Description

A64 Instruction

SADDW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddw_s32 (int64x2_t a, int32x2_t b)Signed add wide

Description

A64 Instruction

SADDW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddw_u8 (uint16x8_t a, uint8x8_t b)Unsigned add wide

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

A64 Instruction

UADDW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddw_u16 (uint32x4_t a, uint16x4_t b)Unsigned add wide

Description

A64 Instruction

UADDW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddw_u32 (uint64x2_t a, uint32x2_t b)Unsigned add wide

Description

A64 Instruction

UADDW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddw_high_s8 (int16x8_t a, int8x16_t b)Signed add wide

Description

A64 Instruction

SADDW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vaddw_high_s16 (int32x4_t a, int16x8_t b)Signed add wide

Description

A64 Instruction

SADDW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vaddw_high_s32 (int64x2_t a, int32x4_t b)Signed add wide

Description

A64 Instruction

SADDW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vaddw_high_u8 (uint16x8_t a, uint8x16_t b)Unsigned add wide

Description

A64 Instruction

UADDW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vaddw_high_u16 (uint32x4_t a, uint16x8_t b)Unsigned add wide

Description

A64 Instruction

UADDW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vaddw_high_u32 (uint64x2_t a, uint32x4_t b)Unsigned add wide

Description

A64 Instruction

UADDW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vhadd_s8 (int8x8_t a, int8x8_t b)Signed halving add

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vhaddq_s8 (int8x16_t a, int8x16_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vhadd_s16 (int16x4_t a, int16x4_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vhaddq_s16 (int16x8_t a, int16x8_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vhadd_s32 (int32x2_t a, int32x2_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vhaddq_s32 (int32x4_t a, int32x4_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vhadd_u8 (uint8x8_t a, uint8x8_t b)Unsigned halving add

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vhaddq_u8 (uint8x16_t a, uint8x16_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vhadd_u16 (uint16x4_t a, uint16x4_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vhaddq_u16 (uint16x8_t a, uint16x8_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vhadd_u32 (uint32x2_t a, uint32x2_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vhaddq_u32 (uint32x4_t a, uint32x4_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vrhadd_s8 (int8x8_t a, int8x8_t b)Signed rounding halving add

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SRHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrhaddq_s8 (int8x16_t a, int8x16_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrhadd_s16 (int16x4_t a, int16x4_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrhaddq_s16 (int16x8_t a, int16x8_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vrhadd_s32 (int32x2_t a, int32x2_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vrhaddq_s32 (int32x4_t a, int32x4_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrhadd_u8 (uint8x8_t a, uint8x8_t b)Unsigned rounding halving add

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

URHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrhaddq_u8 (uint8x16_t a, uint8x16_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrhadd_u16 (uint16x4_t a, uint16x4_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrhaddq_u16 (uint16x8_t a, uint16x8_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrhadd_u32 (uint32x2_t a, uint32x2_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrhaddq_u32 (uint32x4_t a, uint32x4_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vqadd_s8 (int8x8_t a, int8x8_t b)Signed saturating add

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqaddq_s8 (int8x16_t a, int8x16_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqadd_s16 (int16x4_t a, int16x4_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqaddq_s16 (int16x8_t a, int16x8_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqadd_s32 (int32x2_t a, int32x2_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqaddq_s32 (int32x4_t a, int32x4_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqadd_s64 (int64x1_t a, int64x1_t b)Signed saturating add

Description

A64 Instruction

SQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqaddq_s64 (int64x2_t a, int64x2_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqadd_u8 (uint8x8_t a, uint8x8_t b)Unsigned saturating add

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UQADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqaddq_u8 (uint8x16_t a, uint8x16_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqadd_u16 (uint16x4_t a, uint16x4_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqaddq_u16 (uint16x8_t a, uint16x8_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqadd_u32 (uint32x2_t a, uint32x2_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqaddq_u32 (uint32x4_t a, uint32x4_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqadd_u64 (uint64x1_t a, uint64x1_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqaddq_u64 (uint64x2_t a, uint64x2_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8_t vqaddb_s8 (int8_t a, int8_t b)Signed saturating add

Description

A64 Instruction

SQADD Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16_t vqaddh_s16 (int16_t a, int16_t b)Signed saturating add

Description

A64 Instruction

SQADD Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqadds_s32 (int32_t a, int32_t b)Signed saturating add

Description

A64 Instruction

SQADD Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqaddd_s64 (int64_t a, int64_t b)Signed saturating add

Description

A64 Instruction

SQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint8_t vqaddb_u8 (uint8_t a, uint8_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint16_t vqaddh_u16 (uint16_t a, uint16_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint32_t vqadds_u32 (uint32_t a, uint32_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint64_t vqaddd_u64 (uint64_t a, uint64_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vuqadd_s8 (int8x8_t a, uint8x8_t b)Signed saturating accumulate of unsigned value

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

A64 Instruction

SUQADD Vd.8B,Vn.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int8x16_t vuqaddq_s8 (int8x16_t a, uint8x16_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.16B,Vn.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int16x4_t vuqadd_s16 (int16x4_t a, uint16x4_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.4H,Vn.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int16x8_t vuqaddq_s16 (int16x8_t a, uint16x8_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.8H,Vn.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int32x2_t vuqadd_s32 (int32x2_t a, uint32x2_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.2S,Vn.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int32x4_t vuqaddq_s32 (int32x4_t a, uint32x4_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.4S,Vn.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int64x1_t vuqadd_s64 (int64x1_t a, uint64x1_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Dd,Dn
+

Argument Preparation

a → Dd 

+b → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int64x2_t vuqaddq_s64 (int64x2_t a, uint64x2_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.2D,Vn.2D
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int8_t vuqaddb_s8 (int8_t a, uint8_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Bd,Bn
+

Argument Preparation

a → Bd 

+b → Bn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int16_t vuqaddh_s16 (int16_t a, uint16_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Hd,Hn
+

Argument Preparation

a → Hd 

+b → Hn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int32_t vuqadds_s32 (int32_t a, uint32_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Sd,Sn
+

Argument Preparation

a → Sd 

+b → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int64_t vuqaddd_s64 (int64_t a, uint64_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Dd,Dn
+

Argument Preparation

a → Dd 

+b → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint8x8_t vsqadd_u8 (uint8x8_t a, int8x8_t b)Unsigned saturating accumulate of signed value

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

A64 Instruction

USQADD Vd.8B,Vn.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint8x16_t vsqaddq_u8 (uint8x16_t a, int8x16_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.16B,Vn.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint16x4_t vsqadd_u16 (uint16x4_t a, int16x4_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.4H,Vn.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint16x8_t vsqaddq_u16 (uint16x8_t a, int16x8_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.8H,Vn.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint32x2_t vsqadd_u32 (uint32x2_t a, int32x2_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.2S,Vn.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint32x4_t vsqaddq_u32 (uint32x4_t a, int32x4_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.4S,Vn.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint64x1_t vsqadd_u64 (uint64x1_t a, int64x1_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Dd,Dn
+

Argument Preparation

a → Dd 

+b → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint64x2_t vsqaddq_u64 (uint64x2_t a, int64x2_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.2D,Vn.2D
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint8_t vsqaddb_u8 (uint8_t a, int8_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Bd,Bn
+

Argument Preparation

a → Bd 

+b → Bn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint16_t vsqaddh_u16 (uint16_t a, int16_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Hd,Hn
+

Argument Preparation

a → Hd 

+b → Hn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint32_t vsqadds_u32 (uint32_t a, int32_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Sd,Sn
+

Argument Preparation

a → Sd 

+b → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

uint64_t vsqaddd_u64 (uint64_t a, int64_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Dd,Dn
+

Argument Preparation

a → Dd 

+b → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;

Supported architectures

A64

int8x8_t vaddhn_s16 (int16x8_t a, int16x8_t b)Add returning high narrow

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vaddhn_s32 (int32x4_t a, int32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vaddhn_s64 (int64x2_t a, int64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vaddhn_u16 (uint16x8_t a, uint16x8_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vaddhn_u32 (uint32x4_t a, uint32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vaddhn_u64 (uint64x2_t a, uint64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vaddhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vaddhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vaddhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vaddhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vaddhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vaddhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vraddhn_s16 (int16x8_t a, int16x8_t b)Rounding add returning high narrow

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vraddhn_s32 (int32x4_t a, int32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vraddhn_s64 (int64x2_t a, int64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vraddhn_u16 (uint16x8_t a, uint16x8_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vraddhn_u32 (uint32x4_t a, uint32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vraddhn_u64 (uint64x2_t a, uint64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vraddhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vraddhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vraddhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vraddhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vraddhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vraddhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vmul_s8 (int8x8_t a, int8x8_t b)Multiply

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmulq_s8 (int8x16_t a, int8x16_t b)Multiply

Description

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmul_s16 (int16x4_t a, int16x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmulq_s16 (int16x8_t a, int16x8_t b)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmul_s32 (int32x2_t a, int32x2_t b)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmulq_s32 (int32x4_t a, int32x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmul_u8 (uint8x8_t a, uint8x8_t b)Multiply

Description

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmulq_u8 (uint8x16_t a, uint8x16_t b)Multiply

Description

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmul_u16 (uint16x4_t a, uint16x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmulq_u16 (uint16x8_t a, uint16x8_t b)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmul_u32 (uint32x2_t a, uint32x2_t b)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmulq_u32 (uint32x4_t a, uint32x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmul_f32 (float32x2_t a, float32x2_t b)Floating-point multiply

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vmulq_f32 (float32x4_t a, float32x4_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vmul_p8 (poly8x8_t a, poly8x8_t b)Polynomial multiply

Description

Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

PMUL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vmulq_p8 (poly8x16_t a, poly8x16_t b)Polynomial multiply

Description

A64 Instruction

PMUL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmul_f64 (float64x1_t a, float64x1_t b)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulq_f64 (float64x2_t a, float64x2_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmulx_f32 (float32x2_t a, float32x2_t b)Floating-point multiply extended (by element)

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vmulxq_f32 (float32x4_t a, float32x4_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vmulx_f64 (float64x1_t a, float64x1_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulxq_f64 (float64x2_t a, float64x2_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmulxs_f32 (float32_t a, float32_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vmulxd_f64 (float64_t a, float64_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmulx_lane_f32 (float32x2_t a, float32x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vmulxq_lane_f32 (float32x4_t a, float32x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vmulx_lane_f64 (float64x1_t a, float64x1_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulxq_lane_f64 (float64x2_t a, float64x1_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 

+v → Vm.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmulxs_lane_f32 (float32_t a, float32x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vmulxd_lane_f64 (float64_t a, float64x1_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmulx_laneq_f32 (float32x2_t a, float32x4_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vmulxq_laneq_f32 (float32x4_t a, float32x4_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vmulx_laneq_f64 (float64x1_t a, float64x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulxq_laneq_f64 (float64x2_t a, float64x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 

+v → Vm.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmulxs_laneq_f32 (float32_t a, float32x4_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vmulxd_laneq_f64 (float64_t a, float64x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vdiv_f32 (float32x2_t a, float32x2_t b)Floating-point divide

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FDIV Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vdivq_f32 (float32x4_t a, float32x4_t b)Floating-point divide

Description

A64 Instruction

FDIV Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vdiv_f64 (float64x1_t a, float64x1_t b)Floating-point divide

Description

A64 Instruction

FDIV Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vdivq_f64 (float64x2_t a, float64x2_t b)Floating-point divide

Description

A64 Instruction

FDIV Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)Multiply-add to accumulator

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

float32x4_t vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

float64x1_t vmla_f64 (float64x1_t a, float64x1_t b, float64x1_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

A64

float64x2_t vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

A64

int16x8_t vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)Signed multiply-add long

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

SMLAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)Unsigned multiply-add long

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

UMLAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)Multiply-subtract from accumulator

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

float32x4_t vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

float64x1_t vmls_f64 (float64x1_t a, float64x1_t b, float64x1_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

A64

float64x2_t vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

A64

int16x8_t vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)Signed multiply-subtract long

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

SMLSL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)Unsigned multiply-subtract long

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

A64 Instruction

UMLSL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfma_f32 (float32x2_t a, float32x2_t b, float32x2_t c)Floating-point fused multiply-add to accumulator

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vfmaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vfma_f64 (float64x1_t a, float64x1_t b, float64x1_t c)Floating-point fused multiply-add

Description

Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

A64 Instruction

FMADD Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 

+b → Dn 

+c → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+c → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfma_lane_f32 (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vfmaq_lane_f32 (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vfma_lane_f64 (float64x1_t a, float64x1_t b, float64x1_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmaq_lane_f64 (float64x2_t a, float64x2_t b, float64x1_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+v → Vm.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vfmas_lane_f32 (float32_t a, float32_t b, float32x2_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 

+b → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vfmad_lane_f64 (float64_t a, float64_t b, float64x1_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfma_laneq_f32 (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vfmaq_laneq_f32 (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vfma_laneq_f64 (float64x1_t a, float64x1_t b, float64x2_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmaq_laneq_f64 (float64x2_t a, float64x2_t b, float64x2_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+v → Vm.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vfmas_laneq_f32 (float32_t a, float32_t b, float32x4_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 

+b → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vfmad_laneq_f64 (float64_t a, float64_t b, float64x2_t v, const int lane)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfms_f32 (float32x2_t a, float32x2_t b, float32x2_t c)Floating-point fused multiply-subtract from accumulator

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vfmsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vfms_f64 (float64x1_t a, float64x1_t b, float64x1_t c)Floating-point fused multiply-subtract

Description

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

A64 Instruction

FMSUB Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 

+b → Dn 

+c → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+operand1 = FPNeg(operand1);
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+c → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfms_lane_f32 (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vfmsq_lane_f32 (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vfms_lane_f64 (float64x1_t a, float64x1_t b, float64x1_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmsq_lane_f64 (float64x2_t a, float64x2_t b, float64x1_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+v → Vm.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vfmss_lane_f32 (float32_t a, float32_t b, float32x2_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 

+b → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vfmsd_lane_f64 (float64_t a, float64_t b, float64x1_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfms_laneq_f32 (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vfmsq_laneq_f32 (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vfms_laneq_f64 (float64x1_t a, float64x1_t b, float64x2_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmsq_laneq_f64 (float64x2_t a, float64x2_t b, float64x2_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+v → Vm.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vfmss_laneq_f32 (float32_t a, float32_t b, float32x4_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 

+b → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vfmsd_laneq_f64 (float64_t a, float64_t b, float64x2_t v, const int lane)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 

+b → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int16x4_t vqdmulh_s16 (int16x4_t a, int16x4_t b)Signed saturating doubling multiply returning high half

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqdmulhq_s16 (int16x8_t a, int16x8_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqdmulh_s32 (int32x2_t a, int32x2_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqdmulhq_s32 (int32x4_t a, int32x4_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16_t vqdmulhh_s16 (int16_t a, int16_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqdmulhs_s32 (int32_t a, int32_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vqrdmulh_s16 (int16x4_t a, int16x4_t b)Signed saturating rounding doubling multiply returning high half

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqrdmulhq_s16 (int16x8_t a, int16x8_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqrdmulh_s32 (int32x2_t a, int32x2_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqrdmulhq_s32 (int32x4_t a, int32x4_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16_t vqrdmulhh_s16 (int16_t a, int16_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqrdmulhs_s32 (int32_t a, int32_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed saturating doubling multiply-add long

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vqdmlalh_s16 (int32_t a, int16_t b, int16_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Sd,Hn,Hm
+

Argument Preparation

a → Sd 

+b → Hn 

+c → Hm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmlals_s32 (int64_t a, int32_t b, int32_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Dd,Sn,Sm
+

Argument Preparation

a → Dd 

+b → Sn 

+c → Sm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed saturating doubling multiply-subtract long

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vqdmlslh_s16 (int32_t a, int16_t b, int16_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Sd,Hn,Hm
+

Argument Preparation

a → Sd 

+b → Hn 

+c → Hm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmlsls_s32 (int64_t a, int32_t b, int32_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Dd,Sn,Sm
+

Argument Preparation

a → Dd 

+b → Sn 

+c → Sm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x8_t vmull_s8 (int8x8_t a, int8x8_t b)Signed multiply long

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SMULL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmull_s16 (int16x4_t a, int16x4_t b)Signed multiply long

Description

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmull_s32 (int32x2_t a, int32x2_t b)Signed multiply long

Description

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmull_u8 (uint8x8_t a, uint8x8_t b)Unsigned multiply long

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

A64 Instruction

UMULL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmull_u16 (uint16x4_t a, uint16x4_t b)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmull_u32 (uint32x2_t a, uint32x2_t b)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vmull_p8 (poly8x8_t a, poly8x8_t b)Polynomial multiply long

Description

Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

PMULL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmull_high_s8 (int8x16_t a, int8x16_t b)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmull_high_s16 (int16x8_t a, int16x8_t b)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmull_high_s32 (int32x4_t a, int32x4_t b)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmull_high_u8 (uint8x16_t a, uint8x16_t b)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmull_high_u16 (uint16x8_t a, uint16x8_t b)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmull_high_u32 (uint32x4_t a, uint32x4_t b)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vmull_high_p8 (poly8x16_t a, poly8x16_t b)Polynomial multiply long

Description

A64 Instruction

PMULL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_s16 (int16x4_t a, int16x4_t b)Signed saturating doubling multiply long

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmull_s32 (int32x2_t a, int32x2_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vqdmullh_s16 (int16_t a, int16_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Sd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmulls_s32 (int32_t a, int32_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Dd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_high_s16 (int16x8_t a, int16x8_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmull_high_s32 (int32x4_t a, int32x4_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vsub_s8 (int8x8_t a, int8x8_t b)Subtract

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vsubq_s8 (int8x16_t a, int8x16_t b)Subtract

Description

A64 Instruction

SUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vsub_s16 (int16x4_t a, int16x4_t b)Subtract

Description

A64 Instruction

SUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsubq_s16 (int16x8_t a, int16x8_t b)Subtract

Description

A64 Instruction

SUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vsub_s32 (int32x2_t a, int32x2_t b)Subtract

Description

A64 Instruction

SUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsubq_s32 (int32x4_t a, int32x4_t b)Subtract

Description

A64 Instruction

SUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vsub_s64 (int64x1_t a, int64x1_t b)Subtract

Description

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsubq_s64 (int64x2_t a, int64x2_t b)Subtract

Description

A64 Instruction

SUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vsub_u8 (uint8x8_t a, uint8x8_t b)Subtract

Description

A64 Instruction

SUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vsubq_u8 (uint8x16_t a, uint8x16_t b)Subtract

Description

A64 Instruction

SUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vsub_u16 (uint16x4_t a, uint16x4_t b)Subtract

Description

A64 Instruction

SUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsubq_u16 (uint16x8_t a, uint16x8_t b)Subtract

Description

A64 Instruction

SUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vsub_u32 (uint32x2_t a, uint32x2_t b)Subtract

Description

A64 Instruction

SUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsubq_u32 (uint32x4_t a, uint32x4_t b)Subtract

Description

A64 Instruction

SUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vsub_u64 (uint64x1_t a, uint64x1_t b)Subtract

Description

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsubq_u64 (uint64x2_t a, uint64x2_t b)Subtract

Description

A64 Instruction

SUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vsub_f32 (float32x2_t a, float32x2_t b)Floating-point subtract

Description

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vsubq_f32 (float32x4_t a, float32x4_t b)Floating-point subtract

Description

A64 Instruction

FSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vsub_f64 (float64x1_t a, float64x1_t b)Floating-point subtract

Description

A64 Instruction

FSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

A64

float64x2_t vsubq_f64 (float64x2_t a, float64x2_t b)Floating-point subtract

Description

A64 Instruction

FSUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

A64

int64_t vsubd_s64 (int64_t a, int64_t b)Subtract

Description

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint64_t vsubd_u64 (uint64_t a, uint64_t b)Subtract

Description

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vsubl_s8 (int8x8_t a, int8x8_t b)Signed subtract long

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

SSUBL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsubl_s16 (int16x4_t a, int16x4_t b)Signed subtract long

Description

A64 Instruction

SSUBL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsubl_s32 (int32x2_t a, int32x2_t b)Signed subtract long

Description

A64 Instruction

SSUBL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsubl_u8 (uint8x8_t a, uint8x8_t b)Unsigned subtract long

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

USUBL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsubl_u16 (uint16x4_t a, uint16x4_t b)Unsigned subtract long

Description

A64 Instruction

USUBL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsubl_u32 (uint32x2_t a, uint32x2_t b)Unsigned subtract long

Description

A64 Instruction

USUBL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsubl_high_s8 (int8x16_t a, int8x16_t b)Signed subtract long

Description

A64 Instruction

SSUBL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vsubl_high_s16 (int16x8_t a, int16x8_t b)Signed subtract long

Description

A64 Instruction

SSUBL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vsubl_high_s32 (int32x4_t a, int32x4_t b)Signed subtract long

Description

A64 Instruction

SSUBL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vsubl_high_u8 (uint8x16_t a, uint8x16_t b)Unsigned subtract long

Description

A64 Instruction

USUBL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vsubl_high_u16 (uint16x8_t a, uint16x8_t b)Unsigned subtract long

Description

A64 Instruction

USUBL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vsubl_high_u32 (uint32x4_t a, uint32x4_t b)Unsigned subtract long

Description

A64 Instruction

USUBL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vsubw_s8 (int16x8_t a, int8x8_t b)Signed subtract wide

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

A64 Instruction

SSUBW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsubw_s16 (int32x4_t a, int16x4_t b)Signed subtract wide

Description

A64 Instruction

SSUBW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsubw_s32 (int64x2_t a, int32x2_t b)Signed subtract wide

Description

A64 Instruction

SSUBW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsubw_u8 (uint16x8_t a, uint8x8_t b)Unsigned subtract wide

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

A64 Instruction

USUBW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsubw_u16 (uint32x4_t a, uint16x4_t b)Unsigned subtract wide

Description

A64 Instruction

USUBW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsubw_u32 (uint64x2_t a, uint32x2_t b)Unsigned subtract wide

Description

A64 Instruction

USUBW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsubw_high_s8 (int16x8_t a, int8x16_t b)Signed subtract wide

Description

A64 Instruction

SSUBW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vsubw_high_s16 (int32x4_t a, int16x8_t b)Signed subtract wide

Description

A64 Instruction

SSUBW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vsubw_high_s32 (int64x2_t a, int32x4_t b)Signed subtract wide

Description

A64 Instruction

SSUBW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vsubw_high_u8 (uint16x8_t a, uint8x16_t b)Unsigned subtract wide

Description

A64 Instruction

USUBW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vsubw_high_u16 (uint32x4_t a, uint16x8_t b)Unsigned subtract wide

Description

A64 Instruction

USUBW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vsubw_high_u32 (uint64x2_t a, uint32x4_t b)Unsigned subtract wide

Description

A64 Instruction

USUBW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vhsub_s8 (int8x8_t a, int8x8_t b)Signed halving subtract

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SHSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vhsubq_s8 (int8x16_t a, int8x16_t b)Signed halving subtract

Description

A64 Instruction

SHSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vhsub_s16 (int16x4_t a, int16x4_t b)Signed halving subtract

Description

A64 Instruction

SHSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vhsubq_s16 (int16x8_t a, int16x8_t b)Signed halving subtract

Description

A64 Instruction

SHSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vhsub_s32 (int32x2_t a, int32x2_t b)Signed halving subtract

Description

A64 Instruction

SHSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vhsubq_s32 (int32x4_t a, int32x4_t b)Signed halving subtract

Description

A64 Instruction

SHSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vhsub_u8 (uint8x8_t a, uint8x8_t b)Unsigned halving subtract

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UHSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vhsubq_u8 (uint8x16_t a, uint8x16_t b)Unsigned halving subtract

Description

A64 Instruction

UHSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vhsub_u16 (uint16x4_t a, uint16x4_t b)Unsigned halving subtract

Description

A64 Instruction

UHSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vhsubq_u16 (uint16x8_t a, uint16x8_t b)Unsigned halving subtract

Description

A64 Instruction

UHSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vhsub_u32 (uint32x2_t a, uint32x2_t b)Unsigned halving subtract

Description

A64 Instruction

UHSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vhsubq_u32 (uint32x4_t a, uint32x4_t b)Unsigned halving subtract

Description

A64 Instruction

UHSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vqsub_s8 (int8x8_t a, int8x8_t b)Signed saturating subtract

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqsubq_s8 (int8x16_t a, int8x16_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqsub_s16 (int16x4_t a, int16x4_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqsubq_s16 (int16x8_t a, int16x8_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqsub_s32 (int32x2_t a, int32x2_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqsubq_s32 (int32x4_t a, int32x4_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqsub_s64 (int64x1_t a, int64x1_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqsubq_s64 (int64x2_t a, int64x2_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqsub_u8 (uint8x8_t a, uint8x8_t b)Unsigned saturating subtract

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UQSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqsubq_u8 (uint8x16_t a, uint8x16_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqsub_u16 (uint16x4_t a, uint16x4_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqsubq_u16 (uint16x8_t a, uint16x8_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqsub_u32 (uint32x2_t a, uint32x2_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqsubq_u32 (uint32x4_t a, uint32x4_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqsub_u64 (uint64x1_t a, uint64x1_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqsubq_u64 (uint64x2_t a, uint64x2_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8_t vqsubb_s8 (int8_t a, int8_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16_t vqsubh_s16 (int16_t a, int16_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqsubs_s32 (int32_t a, int32_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqsubd_s64 (int64_t a, int64_t b)Signed saturating subtract

Description

A64 Instruction

SQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint8_t vqsubb_u8 (uint8_t a, uint8_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint16_t vqsubh_u16 (uint16_t a, uint16_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint32_t vqsubs_u32 (uint32_t a, uint32_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint64_t vqsubd_u64 (uint64_t a, uint64_t b)Unsigned saturating subtract

Description

A64 Instruction

UQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vsubhn_s16 (int16x8_t a, int16x8_t b)Subtract returning high narrow

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

A64 Instruction

SUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vsubhn_s32 (int32x4_t a, int32x4_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vsubhn_s64 (int64x2_t a, int64x2_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vsubhn_u16 (uint16x8_t a, uint16x8_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vsubhn_u32 (uint32x4_t a, uint32x4_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vsubhn_u64 (uint64x2_t a, uint64x2_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vsubhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vsubhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vsubhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vsubhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vsubhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vsubhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)Subtract returning high narrow

Description

A64 Instruction

SUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vrsubhn_s16 (int16x8_t a, int16x8_t b)Rounding subtract returning high narrow

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

A64 Instruction

RSUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vrsubhn_s32 (int32x4_t a, int32x4_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vrsubhn_s64 (int64x2_t a, int64x2_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrsubhn_u16 (uint16x8_t a, uint16x8_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrsubhn_u32 (uint32x4_t a, uint32x4_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrsubhn_u64 (uint64x2_t a, uint64x2_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vrsubhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vrsubhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vrsubhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vrsubhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+b → Vm.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vrsubhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+b → Vm.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vrsubhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)Rounding subtract returning high narrow

Description

A64 Instruction

RSUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+b → Vm.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x8_t vceq_s8 (int8x8_t a, int8x8_t b)Compare bitwise equal to zero

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vceqq_s8 (int8x16_t a, int8x16_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vceq_s16 (int16x4_t a, int16x4_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vceqq_s16 (int16x8_t a, int16x8_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vceq_s32 (int32x2_t a, int32x2_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vceqq_s32 (int32x4_t a, int32x4_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vceq_u8 (uint8x8_t a, uint8x8_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vceqq_u8 (uint8x16_t a, uint8x16_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vceq_u16 (uint16x4_t a, uint16x4_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vceqq_u16 (uint16x8_t a, uint16x8_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vceq_u32 (uint32x2_t a, uint32x2_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vceqq_u32 (uint32x4_t a, uint32x4_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vceq_f32 (float32x2_t a, float32x2_t b)Floating-point compare equal to zero

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FCMEQ Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vceqq_f32 (float32x4_t a, float32x4_t b)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vceq_p8 (poly8x8_t a, poly8x8_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vceqq_p8 (poly8x16_t a, poly8x16_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vceq_s64 (int64x1_t a, int64x1_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vceqq_s64 (int64x2_t a, int64x2_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vceq_u64 (uint64x1_t a, uint64x1_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vceqq_u64 (uint64x2_t a, uint64x2_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vceq_p64 (poly64x1_t a, poly64x1_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A32/A64

uint64x2_t vceqq_p64 (poly64x2_t a, poly64x2_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A32/A64

uint64x1_t vceq_f64 (float64x1_t a, float64x1_t b)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vceqq_f64 (float64x2_t a, float64x2_t b)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vceqd_s64 (int64_t a, int64_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vceqd_u64 (uint64_t a, uint64_t b)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vceqs_f32 (float32_t a, float32_t b)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vceqd_f64 (float64_t a, float64_t b)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vceqz_s8 (int8x8_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vceqzq_s8 (int8x16_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vceqz_s16 (int16x4_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vceqzq_s16 (int16x8_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vceqz_s32 (int32x2_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vceqzq_s32 (int32x4_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vceqz_u8 (uint8x8_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vceqzq_u8 (uint8x16_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vceqz_u16 (uint16x4_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vceqzq_u16 (uint16x8_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vceqz_u32 (uint32x2_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vceqzq_u32 (uint32x4_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vceqz_f32 (float32x2_t a)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vceqzq_f32 (float32x4_t a)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vceqz_p8 (poly8x8_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vceqzq_p8 (poly8x16_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vceqz_s64 (int64x1_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vceqzq_s64 (int64x2_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vceqz_u64 (uint64x1_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vceqzq_u64 (uint64x2_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vceqz_p64 (poly64x1_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A32/A64

uint64x2_t vceqzq_p64 (poly64x2_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A32/A64

uint64x1_t vceqz_f64 (float64x1_t a)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vceqzq_f64 (float64x2_t a)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vceqzd_s64 (int64_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vceqzd_u64 (uint64_t a)Compare bitwise equal to zero

Description

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vceqzs_f32 (float32_t a)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Sd,Sn,#0
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vceqzd_f64 (float64_t a)Floating-point compare equal to zero

Description

A64 Instruction

FCMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vcge_s8 (int8x8_t a, int8x8_t b)Compare signed greater than or equal to zero

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMGE Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcgeq_s8 (int8x16_t a, int8x16_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcge_s16 (int16x4_t a, int16x4_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcgeq_s16 (int16x8_t a, int16x8_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcge_s32 (int32x2_t a, int32x2_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcgeq_s32 (int32x4_t a, int32x4_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vcge_u8 (uint8x8_t a, uint8x8_t b)Compare unsigned higher or same

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMHS Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcgeq_u8 (uint8x16_t a, uint8x16_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcge_u16 (uint16x4_t a, uint16x4_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcgeq_u16 (uint16x8_t a, uint16x8_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcge_u32 (uint32x2_t a, uint32x2_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcgeq_u32 (uint32x4_t a, uint32x4_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcge_f32 (float32x2_t a, float32x2_t b)Floating-point compare greater than or equal to zero

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FCMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcgeq_f32 (float32x4_t a, float32x4_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcge_s64 (int64x1_t a, int64x1_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgeq_s64 (int64x2_t a, int64x2_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcge_u64 (uint64x1_t a, uint64x1_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgeq_u64 (uint64x2_t a, uint64x2_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcge_f64 (float64x1_t a, float64x1_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgeq_f64 (float64x2_t a, float64x2_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcged_s64 (int64_t a, int64_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcged_u64 (uint64_t a, uint64_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcges_f32 (float32_t a, float32_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcged_f64 (float64_t a, float64_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vcgez_s8 (int8x8_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vcgezq_s8 (int8x16_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vcgez_s16 (int16x4_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vcgezq_s16 (int16x8_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcgez_s32 (int32x2_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vcgezq_s32 (int32x4_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcgez_s64 (int64x1_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgezq_s64 (int64x2_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcgez_f32 (float32x2_t a)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vcgezq_f32 (float32x4_t a)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcgez_f64 (float64x1_t a)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgezq_f64 (float64x2_t a)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgezd_s64 (int64_t a)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcgezs_f32 (float32_t a)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Sd,Sn,#0
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgezd_f64 (float64_t a)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vcle_s8 (int8x8_t a, int8x8_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcleq_s8 (int8x16_t a, int8x16_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcle_s16 (int16x4_t a, int16x4_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcleq_s16 (int16x8_t a, int16x8_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcle_s32 (int32x2_t a, int32x2_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcleq_s32 (int32x4_t a, int32x4_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vcle_u8 (uint8x8_t a, uint8x8_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcleq_u8 (uint8x16_t a, uint8x16_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcle_u16 (uint16x4_t a, uint16x4_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcleq_u16 (uint16x8_t a, uint16x8_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcle_u32 (uint32x2_t a, uint32x2_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcleq_u32 (uint32x4_t a, uint32x4_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcle_f32 (float32x2_t a, float32x2_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcleq_f32 (float32x4_t a, float32x4_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcle_s64 (int64x1_t a, int64x1_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcleq_s64 (int64x2_t a, int64x2_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcle_u64 (uint64x1_t a, uint64x1_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcleq_u64 (uint64x2_t a, uint64x2_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcle_f64 (float64x1_t a, float64x1_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcleq_f64 (float64x2_t a, float64x2_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcled_s64 (int64_t a, int64_t b)Compare signed greater than or equal to zero

Description

A64 Instruction

CMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcled_u64 (uint64_t a, uint64_t b)Compare unsigned higher or same

Description

A64 Instruction

CMHS Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcles_f32 (float32_t a, float32_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Sd,Sm,Sn
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcled_f64 (float64_t a, float64_t b)Floating-point compare greater than or equal to zero

Description

A64 Instruction

FCMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vclez_s8 (int8x8_t a)Compare signed less than or equal to zero

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMLE Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vclezq_s8 (int8x16_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vclez_s16 (int16x4_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vclezq_s16 (int16x8_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vclez_s32 (int32x2_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vclezq_s32 (int32x4_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vclez_s64 (int64x1_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vclezq_s64 (int64x2_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vclez_f32 (float32x2_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vclezq_f32 (float32x4_t a)Floating-point compare less than or equal to zero

Description

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FCMLE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vclez_f64 (float64x1_t a)Floating-point compare less than or equal to zero

Description

A64 Instruction

FCMLE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vclezq_f64 (float64x2_t a)Floating-point compare less than or equal to zero

Description

A64 Instruction

FCMLE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vclezd_s64 (int64_t a)Compare signed less than or equal to zero

Description

A64 Instruction

CMLE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vclezs_f32 (float32_t a)Floating-point compare less than or equal to zero

Description

A64 Instruction

FCMLE Sd,Sn,#0
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vclezd_f64 (float64_t a)Floating-point compare less than or equal to zero

Description

A64 Instruction

FCMLE Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vcgt_s8 (int8x8_t a, int8x8_t b)Compare signed greater than zero

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMGT Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcgtq_s8 (int8x16_t a, int8x16_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcgt_s16 (int16x4_t a, int16x4_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcgtq_s16 (int16x8_t a, int16x8_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcgt_s32 (int32x2_t a, int32x2_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcgtq_s32 (int32x4_t a, int32x4_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vcgt_u8 (uint8x8_t a, uint8x8_t b)Compare unsigned higher

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMHI Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcgtq_u8 (uint8x16_t a, uint8x16_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcgt_u16 (uint16x4_t a, uint16x4_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcgtq_u16 (uint16x8_t a, uint16x8_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcgt_u32 (uint32x2_t a, uint32x2_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcgtq_u32 (uint32x4_t a, uint32x4_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcgt_f32 (float32x2_t a, float32x2_t b)Floating-point compare greater than zero

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FCMGT Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcgtq_f32 (float32x4_t a, float32x4_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcgt_s64 (int64x1_t a, int64x1_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgtq_s64 (int64x2_t a, int64x2_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcgt_u64 (uint64x1_t a, uint64x1_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgtq_u64 (uint64x2_t a, uint64x2_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcgt_f64 (float64x1_t a, float64x1_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgtq_f64 (float64x2_t a, float64x2_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgtd_s64 (int64_t a, int64_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgtd_u64 (uint64_t a, uint64_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcgts_f32 (float32_t a, float32_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgtd_f64 (float64_t a, float64_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vcgtz_s8 (int8x8_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vcgtzq_s8 (int8x16_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vcgtz_s16 (int16x4_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vcgtzq_s16 (int16x8_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcgtz_s32 (int32x2_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vcgtzq_s32 (int32x4_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcgtz_s64 (int64x1_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgtzq_s64 (int64x2_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcgtz_f32 (float32x2_t a)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vcgtzq_f32 (float32x4_t a)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcgtz_f64 (float64x1_t a)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcgtzq_f64 (float64x2_t a)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgtzd_s64 (int64_t a)Compare signed greater than zero

Description

A64 Instruction

CMGT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcgtzs_f32 (float32_t a)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Sd,Sn,#0
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcgtzd_f64 (float64_t a)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vclt_s8 (int8x8_t a, int8x8_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcltq_s8 (int8x16_t a, int8x16_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vclt_s16 (int16x4_t a, int16x4_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcltq_s16 (int16x8_t a, int16x8_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vclt_s32 (int32x2_t a, int32x2_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcltq_s32 (int32x4_t a, int32x4_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vclt_u8 (uint8x8_t a, uint8x8_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcltq_u8 (uint8x16_t a, uint8x16_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vclt_u16 (uint16x4_t a, uint16x4_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcltq_u16 (uint16x8_t a, uint16x8_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vclt_u32 (uint32x2_t a, uint32x2_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcltq_u32 (uint32x4_t a, uint32x4_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vclt_f32 (float32x2_t a, float32x2_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcltq_f32 (float32x4_t a, float32x4_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vclt_s64 (int64x1_t a, int64x1_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcltq_s64 (int64x2_t a, int64x2_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vclt_u64 (uint64x1_t a, uint64x1_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcltq_u64 (uint64x2_t a, uint64x2_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vclt_f64 (float64x1_t a, float64x1_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcltq_f64 (float64x2_t a, float64x2_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcltd_s64 (int64_t a, int64_t b)Compare signed greater than zero

Description

A64 Instruction

CMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcltd_u64 (uint64_t a, uint64_t b)Compare unsigned higher

Description

A64 Instruction

CMHI Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vclts_f32 (float32_t a, float32_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Sd,Sm,Sn
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcltd_f64 (float64_t a, float64_t b)Floating-point compare greater than zero

Description

A64 Instruction

FCMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vcltz_s8 (int8x8_t a)Compare signed less than zero

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMLT Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vcltzq_s8 (int8x16_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vcltz_s16 (int16x4_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vcltzq_s16 (int16x8_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcltz_s32 (int32x2_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vcltzq_s32 (int32x4_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcltz_s64 (int64x1_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcltzq_s64 (int64x2_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcltz_f32 (float32x2_t a)Floating-point compare less than zero

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FCMLT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vcltzq_f32 (float32x4_t a)Floating-point compare less than zero

Description

A64 Instruction

FCMLT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcltz_f64 (float64x1_t a)Floating-point compare less than zero

Description

A64 Instruction

FCMLT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcltzq_f64 (float64x2_t a)Floating-point compare less than zero

Description

A64 Instruction

FCMLT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcltzd_s64 (int64_t a)Compare signed less than zero

Description

A64 Instruction

CMLT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcltzs_f32 (float32_t a)Floating-point compare less than zero

Description

A64 Instruction

FCMLT Sd,Sn,#0
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcltzd_f64 (float64_t a)Floating-point compare less than zero

Description

A64 Instruction

FCMLT Dd,Dn,#0
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcage_f32 (float32x2_t a, float32x2_t b)Floating-point absolute compare greater than or equal

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FACGE Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcageq_f32 (float32x4_t a, float32x4_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcage_f64 (float64x1_t a, float64x1_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcageq_f64 (float64x2_t a, float64x2_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcages_f32 (float32_t a, float32_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcaged_f64 (float64_t a, float64_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcale_f32 (float32x2_t a, float32x2_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcaleq_f32 (float32x4_t a, float32x4_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcale_f64 (float64x1_t a, float64x1_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcaleq_f64 (float64x2_t a, float64x2_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcales_f32 (float32_t a, float32_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Sd,Sm,Sn
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcaled_f64 (float64_t a, float64_t b)Floating-point absolute compare greater than or equal

Description

A64 Instruction

FACGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcagt_f32 (float32x2_t a, float32x2_t b)Floating-point absolute compare greater than

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

FACGT Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcagtq_f32 (float32x4_t a, float32x4_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcagt_f64 (float64x1_t a, float64x1_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcagtq_f64 (float64x2_t a, float64x2_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcagts_f32 (float32_t a, float32_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcagtd_f64 (float64_t a, float64_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vcalt_f32 (float32x2_t a, float32x2_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcaltq_f32 (float32x4_t a, float32x4_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcalt_f64 (float64x1_t a, float64x1_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcaltq_f64 (float64x2_t a, float64x2_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint32_t vcalts_f32 (float32_t a, float32_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Sd,Sm,Sn
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vcaltd_f64 (float64_t a, float64_t b)Floating-point absolute compare greater than

Description

A64 Instruction

FACGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vtst_s8 (int8x8_t a, int8x8_t b)Compare bitwise test bits nonzero

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vtstq_s8 (int8x16_t a, int8x16_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vtst_s16 (int16x4_t a, int16x4_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vtstq_s16 (int16x8_t a, int16x8_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vtst_s32 (int32x2_t a, int32x2_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vtstq_s32 (int32x4_t a, int32x4_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtst_u8 (uint8x8_t a, uint8x8_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vtstq_u8 (uint8x16_t a, uint8x16_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vtst_u16 (uint16x4_t a, uint16x4_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vtstq_u16 (uint16x8_t a, uint16x8_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vtst_u32 (uint32x2_t a, uint32x2_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vtstq_u32 (uint32x4_t a, uint32x4_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtst_p8 (poly8x8_t a, poly8x8_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vtstq_p8 (poly8x16_t a, poly8x16_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vtst_s64 (int64x1_t a, int64x1_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vtstq_s64 (int64x2_t a, int64x2_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vtst_u64 (uint64x1_t a, uint64x1_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vtstq_u64 (uint64x2_t a, uint64x2_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vtst_p64 (poly64x1_t a, poly64x1_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A32/A64

uint64x2_t vtstq_p64 (poly64x2_t a, poly64x2_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A32/A64

uint64_t vtstd_s64 (int64_t a, int64_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

uint64_t vtstd_u64 (uint64_t a, uint64_t b)Compare bitwise test bits nonzero

Description

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;

Supported architectures

A64

int8x8_t vabd_s8 (int8x8_t a, int8x8_t b)Signed absolute difference

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SABD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vabdq_s8 (int8x16_t a, int8x16_t b)Signed absolute difference

Description

A64 Instruction

SABD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vabd_s16 (int16x4_t a, int16x4_t b)Signed absolute difference

Description

A64 Instruction

SABD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vabdq_s16 (int16x8_t a, int16x8_t b)Signed absolute difference

Description

A64 Instruction

SABD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vabd_s32 (int32x2_t a, int32x2_t b)Signed absolute difference

Description

A64 Instruction

SABD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vabdq_s32 (int32x4_t a, int32x4_t b)Signed absolute difference

Description

A64 Instruction

SABD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vabd_u8 (uint8x8_t a, uint8x8_t b)Unsigned absolute difference

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UABD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vabdq_u8 (uint8x16_t a, uint8x16_t b)Unsigned absolute difference

Description

A64 Instruction

UABD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vabd_u16 (uint16x4_t a, uint16x4_t b)Unsigned absolute difference

Description

A64 Instruction

UABD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vabdq_u16 (uint16x8_t a, uint16x8_t b)Unsigned absolute difference

Description

A64 Instruction

UABD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vabd_u32 (uint32x2_t a, uint32x2_t b)Unsigned absolute difference

Description

A64 Instruction

UABD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vabdq_u32 (uint32x4_t a, uint32x4_t b)Unsigned absolute difference

Description

A64 Instruction

UABD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vabd_f32 (float32x2_t a, float32x2_t b)Floating-point absolute difference

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FABD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vabdq_f32 (float32x4_t a, float32x4_t b)Floating-point absolute difference

Description

A64 Instruction

FABD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vabd_f64 (float64x1_t a, float64x1_t b)Floating-point absolute difference

Description

A64 Instruction

FABD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

A64

float64x2_t vabdq_f64 (float64x2_t a, float64x2_t b)Floating-point absolute difference

Description

A64 Instruction

FABD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

A64

float32_t vabds_f32 (float32_t a, float32_t b)Floating-point absolute difference

Description

A64 Instruction

FABD Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

A64

float64_t vabdd_f64 (float64_t a, float64_t b)Floating-point absolute difference

Description

A64 Instruction

FABD Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vabdl_s8 (int8x8_t a, int8x8_t b)Signed absolute difference long

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

SABDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vabdl_s16 (int16x4_t a, int16x4_t b)Signed absolute difference long

Description

A64 Instruction

SABDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vabdl_s32 (int32x2_t a, int32x2_t b)Signed absolute difference long

Description

A64 Instruction

SABDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vabdl_u8 (uint8x8_t a, uint8x8_t b)Unsigned absolute difference long

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

A64 Instruction

UABDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vabdl_u16 (uint16x4_t a, uint16x4_t b)Unsigned absolute difference long

Description

A64 Instruction

UABDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vabdl_u32 (uint32x2_t a, uint32x2_t b)Unsigned absolute difference long

Description

A64 Instruction

UABDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vabdl_high_s8 (int8x16_t a, int8x16_t b)Signed absolute difference long

Description

A64 Instruction

SABDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

int32x4_t vabdl_high_s16 (int16x8_t a, int16x8_t b)Signed absolute difference long

Description

A64 Instruction

SABDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

int64x2_t vabdl_high_s32 (int32x4_t a, int32x4_t b)Signed absolute difference long

Description

A64 Instruction

SABDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

uint16x8_t vabdl_high_u8 (uint8x16_t a, uint8x16_t b)Unsigned absolute difference long

Description

A64 Instruction

UABDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

uint32x4_t vabdl_high_u16 (uint16x8_t a, uint16x8_t b)Unsigned absolute difference long

Description

A64 Instruction

UABDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

uint64x2_t vabdl_high_u32 (uint32x4_t a, uint32x4_t b)Unsigned absolute difference long

Description

A64 Instruction

UABDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

int8x8_t vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c)Signed absolute difference and accumulate

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

A64 Instruction

SABA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)Signed absolute difference and accumulate

Description

A64 Instruction

SABA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c)Signed absolute difference and accumulate

Description

A64 Instruction

SABA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)Signed absolute difference and accumulate

Description

A64 Instruction

SABA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c)Signed absolute difference and accumulate

Description

A64 Instruction

SABA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)Signed absolute difference and accumulate

Description

A64 Instruction

SABA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Unsigned absolute difference and accumulate

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

A64 Instruction

UABA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)Unsigned absolute difference and accumulate

Description

A64 Instruction

UABA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)Unsigned absolute difference and accumulate

Description

A64 Instruction

UABA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)Unsigned absolute difference and accumulate

Description

A64 Instruction

UABA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)Unsigned absolute difference and accumulate

Description

A64 Instruction

UABA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)Unsigned absolute difference and accumulate

Description

A64 Instruction

UABA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)Signed absolute difference and accumulate long

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

SABAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed absolute difference and accumulate long

Description

A64 Instruction

SABAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)Signed absolute difference and accumulate long

Description

A64 Instruction

SABAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)Unsigned absolute difference and accumulate long

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

A64 Instruction

UABAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)Unsigned absolute difference and accumulate long

Description

A64 Instruction

UABAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)Unsigned absolute difference and accumulate long

Description

A64 Instruction

UABAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)Signed absolute difference and accumulate long

Description

A64 Instruction

SABAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

int32x4_t vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)Signed absolute difference and accumulate long

Description

A64 Instruction

SABAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

int64x2_t vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)Signed absolute difference and accumulate long

Description

A64 Instruction

SABAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

uint16x8_t vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)Unsigned absolute difference and accumulate long

Description

A64 Instruction

UABAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

uint32x4_t vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)Unsigned absolute difference and accumulate long

Description

A64 Instruction

UABAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

uint64x2_t vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)Unsigned absolute difference and accumulate long

Description

A64 Instruction

UABAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;

Supported architectures

A64

int8x8_t vmax_s8 (int8x8_t a, int8x8_t b)Signed maximum

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SMAX Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmaxq_s8 (int8x16_t a, int8x16_t b)Signed maximum

Description

A64 Instruction

SMAX Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmax_s16 (int16x4_t a, int16x4_t b)Signed maximum

Description

A64 Instruction

SMAX Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmaxq_s16 (int16x8_t a, int16x8_t b)Signed maximum

Description

A64 Instruction

SMAX Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmax_s32 (int32x2_t a, int32x2_t b)Signed maximum

Description

A64 Instruction

SMAX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmaxq_s32 (int32x4_t a, int32x4_t b)Signed maximum

Description

A64 Instruction

SMAX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmax_u8 (uint8x8_t a, uint8x8_t b)Unsigned maximum

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UMAX Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmaxq_u8 (uint8x16_t a, uint8x16_t b)Unsigned maximum

Description

A64 Instruction

UMAX Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmax_u16 (uint16x4_t a, uint16x4_t b)Unsigned maximum

Description

A64 Instruction

UMAX Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmaxq_u16 (uint16x8_t a, uint16x8_t b)Unsigned maximum

Description

A64 Instruction

UMAX Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmax_u32 (uint32x2_t a, uint32x2_t b)Unsigned maximum

Description

A64 Instruction

UMAX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmaxq_u32 (uint32x4_t a, uint32x4_t b)Unsigned maximum

Description

A64 Instruction

UMAX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmax_f32 (float32x2_t a, float32x2_t b)Floating-point maximum

Description

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMAX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vmaxq_f32 (float32x4_t a, float32x4_t b)Floating-point maximum

Description

A64 Instruction

FMAX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmax_f64 (float64x1_t a, float64x1_t b)Floating-point maximum

Description

A64 Instruction

FMAX Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmaxq_f64 (float64x2_t a, float64x2_t b)Floating-point maximum

Description

A64 Instruction

FMAX Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vmin_s8 (int8x8_t a, int8x8_t b)Signed minimum

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SMIN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vminq_s8 (int8x16_t a, int8x16_t b)Signed minimum

Description

A64 Instruction

SMIN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmin_s16 (int16x4_t a, int16x4_t b)Signed minimum

Description

A64 Instruction

SMIN Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vminq_s16 (int16x8_t a, int16x8_t b)Signed minimum

Description

A64 Instruction

SMIN Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmin_s32 (int32x2_t a, int32x2_t b)Signed minimum

Description

A64 Instruction

SMIN Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vminq_s32 (int32x4_t a, int32x4_t b)Signed minimum

Description

A64 Instruction

SMIN Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmin_u8 (uint8x8_t a, uint8x8_t b)Unsigned minimum

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UMIN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vminq_u8 (uint8x16_t a, uint8x16_t b)Unsigned minimum

Description

A64 Instruction

UMIN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmin_u16 (uint16x4_t a, uint16x4_t b)Unsigned minimum

Description

A64 Instruction

UMIN Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vminq_u16 (uint16x8_t a, uint16x8_t b)Unsigned minimum

Description

A64 Instruction

UMIN Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmin_u32 (uint32x2_t a, uint32x2_t b)Unsigned minimum

Description

A64 Instruction

UMIN Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vminq_u32 (uint32x4_t a, uint32x4_t b)Unsigned minimum

Description

A64 Instruction

UMIN Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmin_f32 (float32x2_t a, float32x2_t b)Floating-point minimum

Description

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMIN Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vminq_f32 (float32x4_t a, float32x4_t b)Floating-point minimum

Description

A64 Instruction

FMIN Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmin_f64 (float64x1_t a, float64x1_t b)Floating-point minimum

Description

A64 Instruction

FMIN Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vminq_f64 (float64x2_t a, float64x2_t b)Floating-point minimum

Description

A64 Instruction

FMIN Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmaxnm_f32 (float32x2_t a, float32x2_t b)Floating-point maximum number

Description

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMAXNM Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vmaxnmq_f32 (float32x4_t a, float32x4_t b)Floating-point maximum number

Description

A64 Instruction

FMAXNM Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vmaxnm_f64 (float64x1_t a, float64x1_t b)Floating-point maximum number

Description

A64 Instruction

FMAXNM Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmaxnmq_f64 (float64x2_t a, float64x2_t b)Floating-point maximum number

Description

A64 Instruction

FMAXNM Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vminnm_f32 (float32x2_t a, float32x2_t b)Floating-point minimum number

Description

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMINNM Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vminnmq_f32 (float32x4_t a, float32x4_t b)Floating-point minimum number

Description

A64 Instruction

FMINNM Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vminnm_f64 (float64x1_t a, float64x1_t b)Floating-point minimum number

Description

A64 Instruction

FMINNM Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vminnmq_f64 (float64x2_t a, float64x2_t b)Floating-point minimum number

Description

A64 Instruction

FMINNM Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vshl_s8 (int8x8_t a, int8x8_t b)Signed shift left

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vshlq_s8 (int8x16_t a, int8x16_t b)Signed shift left

Description

A64 Instruction

SSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vshl_s16 (int16x4_t a, int16x4_t b)Signed shift left

Description

A64 Instruction

SSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vshlq_s16 (int16x8_t a, int16x8_t b)Signed shift left

Description

A64 Instruction

SSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vshl_s32 (int32x2_t a, int32x2_t b)Signed shift left

Description

A64 Instruction

SSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vshlq_s32 (int32x4_t a, int32x4_t b)Signed shift left

Description

A64 Instruction

SSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vshl_s64 (int64x1_t a, int64x1_t b)Signed shift left

Description

A64 Instruction

SSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vshlq_s64 (int64x2_t a, int64x2_t b)Signed shift left

Description

A64 Instruction

SSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vshl_u8 (uint8x8_t a, int8x8_t b)Unsigned shift left

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

USHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vshlq_u8 (uint8x16_t a, int8x16_t b)Unsigned shift left

Description

A64 Instruction

USHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vshl_u16 (uint16x4_t a, int16x4_t b)Unsigned shift left

Description

A64 Instruction

USHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vshlq_u16 (uint16x8_t a, int16x8_t b)Unsigned shift left

Description

A64 Instruction

USHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vshl_u32 (uint32x2_t a, int32x2_t b)Unsigned shift left

Description

A64 Instruction

USHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vshlq_u32 (uint32x4_t a, int32x4_t b)Unsigned shift left

Description

A64 Instruction

USHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vshl_u64 (uint64x1_t a, int64x1_t b)Unsigned shift left

Description

A64 Instruction

USHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vshlq_u64 (uint64x2_t a, int64x2_t b)Unsigned shift left

Description

A64 Instruction

USHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vshld_s64 (int64_t a, int64_t b)Signed shift left

Description

A64 Instruction

SSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vshld_u64 (uint64_t a, int64_t b)Unsigned shift left

Description

A64 Instruction

USHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqshl_s8 (int8x8_t a, int8x8_t b)Signed saturating shift left

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqshlq_s8 (int8x16_t a, int8x16_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqshl_s16 (int16x4_t a, int16x4_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqshlq_s16 (int16x8_t a, int16x8_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqshl_s32 (int32x2_t a, int32x2_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqshlq_s32 (int32x4_t a, int32x4_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqshl_s64 (int64x1_t a, int64x1_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqshlq_s64 (int64x2_t a, int64x2_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqshl_u8 (uint8x8_t a, int8x8_t b)Unsigned saturating shift left

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UQSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqshlq_u8 (uint8x16_t a, int8x16_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqshl_u16 (uint16x4_t a, int16x4_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqshlq_u16 (uint16x8_t a, int16x8_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqshl_u32 (uint32x2_t a, int32x2_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqshlq_u32 (uint32x4_t a, int32x4_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqshl_u64 (uint64x1_t a, int64x1_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqshlq_u64 (uint64x2_t a, int64x2_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8_t vqshlb_s8 (int8_t a, int8_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16_t vqshlh_s16 (int16_t a, int16_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32_t vqshls_s32 (int32_t a, int32_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64_t vqshld_s64 (int64_t a, int64_t b)Signed saturating shift left

Description

A64 Instruction

SQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint8_t vqshlb_u8 (uint8_t a, int8_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16_t vqshlh_u16 (uint16_t a, int16_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32_t vqshls_u32 (uint32_t a, int32_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vqshld_u64 (uint64_t a, int64_t b)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vrshl_s8 (int8x8_t a, int8x8_t b)Signed rounding shift left

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SRSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrshlq_s8 (int8x16_t a, int8x16_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrshl_s16 (int16x4_t a, int16x4_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrshlq_s16 (int16x8_t a, int16x8_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vrshl_s32 (int32x2_t a, int32x2_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vrshlq_s32 (int32x4_t a, int32x4_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vrshl_s64 (int64x1_t a, int64x1_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vrshlq_s64 (int64x2_t a, int64x2_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrshl_u8 (uint8x8_t a, int8x8_t b)Unsigned rounding shift left

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

URSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrshlq_u8 (uint8x16_t a, int8x16_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrshl_u16 (uint16x4_t a, int16x4_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrshlq_u16 (uint16x8_t a, int16x8_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrshl_u32 (uint32x2_t a, int32x2_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrshlq_u32 (uint32x4_t a, int32x4_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vrshl_u64 (uint64x1_t a, int64x1_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vrshlq_u64 (uint64x2_t a, int64x2_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vrshld_s64 (int64_t a, int64_t b)Signed rounding shift left

Description

A64 Instruction

SRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vrshld_u64 (uint64_t a, int64_t b)Unsigned rounding shift left

Description

A64 Instruction

URSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqrshl_s8 (int8x8_t a, int8x8_t b)Signed saturating rounding shift left

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQRSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqrshlq_s8 (int8x16_t a, int8x16_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqrshl_s16 (int16x4_t a, int16x4_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqrshlq_s16 (int16x8_t a, int16x8_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqrshl_s32 (int32x2_t a, int32x2_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqrshlq_s32 (int32x4_t a, int32x4_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqrshl_s64 (int64x1_t a, int64x1_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqrshlq_s64 (int64x2_t a, int64x2_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqrshl_u8 (uint8x8_t a, int8x8_t b)Unsigned saturating rounding shift left

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UQRSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqrshlq_u8 (uint8x16_t a, int8x16_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqrshl_u16 (uint16x4_t a, int16x4_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqrshlq_u16 (uint16x8_t a, int16x8_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqrshl_u32 (uint32x2_t a, int32x2_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqrshlq_u32 (uint32x4_t a, int32x4_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqrshl_u64 (uint64x1_t a, int64x1_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqrshlq_u64 (uint64x2_t a, int64x2_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8_t vqrshlb_s8 (int8_t a, int8_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16_t vqrshlh_s16 (int16_t a, int16_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32_t vqrshls_s32 (int32_t a, int32_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64_t vqrshld_s64 (int64_t a, int64_t b)Signed saturating rounding shift left

Description

A64 Instruction

SQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint8_t vqrshlb_u8 (uint8_t a, int8_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 

+b → Bm

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16_t vqrshlh_u16 (uint16_t a, int16_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 

+b → Hm

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32_t vqrshls_u32 (uint32_t a, int32_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vqrshld_u64 (uint64_t a, int64_t b)Unsigned saturating rounding shift left

Description

A64 Instruction

UQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vshr_n_s8 (int8x8_t a, const int n)Signed shift right

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

A64 Instruction

SSHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vshrq_n_s8 (int8x16_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vshr_n_s16 (int16x4_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vshrq_n_s16 (int16x8_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vshr_n_s32 (int32x2_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vshrq_n_s32 (int32x4_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vshr_n_s64 (int64x1_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vshrq_n_s64 (int64x2_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vshr_n_u8 (uint8x8_t a, const int n)Unsigned shift right

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

A64 Instruction

USHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vshrq_n_u8 (uint8x16_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vshr_n_u16 (uint16x4_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vshrq_n_u16 (uint16x8_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vshr_n_u32 (uint32x2_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vshrq_n_u32 (uint32x4_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vshr_n_u64 (uint64x1_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vshrq_n_u64 (uint64x2_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vshrd_n_s64 (int64_t a, const int n)Signed shift right

Description

A64 Instruction

SSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vshrd_n_u64 (uint64_t a, const int n)Unsigned shift right

Description

A64 Instruction

USHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vshl_n_s8 (int8x8_t a, const int n)Shift left

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vshlq_n_s8 (int8x16_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vshl_n_s16 (int16x4_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vshlq_n_s16 (int16x8_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vshl_n_s32 (int32x2_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vshlq_n_s32 (int32x4_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vshl_n_s64 (int64x1_t a, const int n)Shift left

Description

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vshlq_n_s64 (int64x2_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vshl_n_u8 (uint8x8_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vshlq_n_u8 (uint8x16_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vshl_n_u16 (uint16x4_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vshlq_n_u16 (uint16x8_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vshl_n_u32 (uint32x2_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vshlq_n_u32 (uint32x4_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vshl_n_u64 (uint64x1_t a, const int n)Shift left

Description

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vshlq_n_u64 (uint64x2_t a, const int n)Shift left

Description

A64 Instruction

SHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vshld_n_s64 (int64_t a, const int n)Shift left

Description

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

A64

uint64_t vshld_n_u64 (uint64_t a, const int n)Shift left

Description

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vrshr_n_s8 (int8x8_t a, const int n)Signed rounding shift right

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

A64 Instruction

SRSHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrshrq_n_s8 (int8x16_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrshr_n_s16 (int16x4_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrshrq_n_s16 (int16x8_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vrshr_n_s32 (int32x2_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vrshrq_n_s32 (int32x4_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vrshr_n_s64 (int64x1_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vrshrq_n_s64 (int64x2_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrshr_n_u8 (uint8x8_t a, const int n)Unsigned rounding shift right

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

A64 Instruction

URSHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrshrq_n_u8 (uint8x16_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrshr_n_u16 (uint16x4_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrshrq_n_u16 (uint16x8_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrshr_n_u32 (uint32x2_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrshrq_n_u32 (uint32x4_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vrshr_n_u64 (uint64x1_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vrshrq_n_u64 (uint64x2_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vrshrd_n_s64 (int64_t a, const int n)Signed rounding shift right

Description

A64 Instruction

SRSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vrshrd_n_u64 (uint64_t a, const int n)Unsigned rounding shift right

Description

A64 Instruction

URSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vsra_n_s8 (int8x8_t a, int8x8_t b, const int n)Signed shift right and accumulate

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

A64 Instruction

SSRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vsraq_n_s8 (int8x16_t a, int8x16_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vsra_n_s16 (int16x4_t a, int16x4_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsraq_n_s16 (int16x8_t a, int16x8_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vsra_n_s32 (int32x2_t a, int32x2_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsraq_n_s32 (int32x4_t a, int32x4_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vsra_n_s64 (int64x1_t a, int64x1_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsraq_n_s64 (int64x2_t a, int64x2_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vsra_n_u8 (uint8x8_t a, uint8x8_t b, const int n)Unsigned shift right and accumulate

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

A64 Instruction

USRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vsraq_n_u8 (uint8x16_t a, uint8x16_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vsra_n_u16 (uint16x4_t a, uint16x4_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsraq_n_u16 (uint16x8_t a, uint16x8_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vsra_n_u32 (uint32x2_t a, uint32x2_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsraq_n_u32 (uint32x4_t a, uint32x4_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vsra_n_u64 (uint64x1_t a, uint64x1_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsraq_n_u64 (uint64x2_t a, uint64x2_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vsrad_n_s64 (int64_t a, int64_t b, const int n)Signed shift right and accumulate

Description

A64 Instruction

SSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vsrad_n_u64 (uint64_t a, uint64_t b, const int n)Unsigned shift right and accumulate

Description

A64 Instruction

USRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vrsra_n_s8 (int8x8_t a, int8x8_t b, const int n)Signed rounding shift right and accumulate

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

A64 Instruction

SRSRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrsraq_n_s8 (int8x16_t a, int8x16_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrsra_n_s16 (int16x4_t a, int16x4_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrsraq_n_s16 (int16x8_t a, int16x8_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vrsra_n_s32 (int32x2_t a, int32x2_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vrsraq_n_s32 (int32x4_t a, int32x4_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vrsra_n_s64 (int64x1_t a, int64x1_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vrsraq_n_s64 (int64x2_t a, int64x2_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrsra_n_u8 (uint8x8_t a, uint8x8_t b, const int n)Unsigned rounding shift right and accumulate

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

A64 Instruction

URSRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrsraq_n_u8 (uint8x16_t a, uint8x16_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrsra_n_u16 (uint16x4_t a, uint16x4_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrsraq_n_u16 (uint16x8_t a, uint16x8_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrsra_n_u32 (uint32x2_t a, uint32x2_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrsraq_n_u32 (uint32x4_t a, uint32x4_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vrsra_n_u64 (uint64x1_t a, uint64x1_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vrsraq_n_u64 (uint64x2_t a, uint64x2_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vrsrad_n_s64 (int64_t a, int64_t b, const int n)Signed rounding shift right and accumulate

Description

A64 Instruction

SRSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vrsrad_n_u64 (uint64_t a, uint64_t b, const int n)Unsigned rounding shift right and accumulate

Description

A64 Instruction

URSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqshl_n_s8 (int8x8_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqshlq_n_s8 (int8x16_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqshl_n_s16 (int16x4_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqshlq_n_s16 (int16x8_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqshl_n_s32 (int32x2_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqshlq_n_s32 (int32x4_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqshl_n_s64 (int64x1_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqshlq_n_s64 (int64x2_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqshl_n_u8 (uint8x8_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqshlq_n_u8 (uint8x16_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqshl_n_u16 (uint16x4_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqshlq_n_u16 (uint16x8_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqshl_n_u32 (uint32x2_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqshlq_n_u32 (uint32x4_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqshl_n_u64 (uint64x1_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqshlq_n_u64 (uint64x2_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8_t vqshlb_n_s8 (int8_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Bd,Bn,#n
+

Argument Preparation

a → Bn 

+0 << n << 7

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16_t vqshlh_n_s16 (int16_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Hd,Hn,#n
+

Argument Preparation

a → Hn 

+0 << n << 15

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32_t vqshls_n_s32 (int32_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Sd,Sn,#n
+

Argument Preparation

a → Sn 

+0 << n << 31

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64_t vqshld_n_s64 (int64_t a, const int n)Signed saturating shift left

Description

A64 Instruction

SQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint8_t vqshlb_n_u8 (uint8_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Bd,Bn,#n
+

Argument Preparation

a → Bn 

+0 << n << 7

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16_t vqshlh_n_u16 (uint16_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Hd,Hn,#n
+

Argument Preparation

a → Hn 

+0 << n << 15

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32_t vqshls_n_u32 (uint32_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Sd,Sn,#n
+

Argument Preparation

a → Sn 

+0 << n << 31

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64_t vqshld_n_u64 (uint64_t a, const int n)Unsigned saturating shift left

Description

A64 Instruction

UQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqshlu_n_s8 (int8x8_t a, const int n)Signed saturating shift left unsigned

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

A64 Instruction

SQSHLU Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqshluq_n_s8 (int8x16_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqshlu_n_s16 (int16x4_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqshluq_n_s16 (int16x8_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqshlu_n_s32 (int32x2_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqshluq_n_s32 (int32x4_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqshlu_n_s64 (int64x1_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqshluq_n_s64 (int64x2_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8_t vqshlub_n_s8 (int8_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Bd,Bn,#n
+

Argument Preparation

a → Bn 

+0 << n << 7

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint16_t vqshluh_n_s16 (int16_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Hd,Hn,#n
+

Argument Preparation

a → Hn 

+0 << n << 15

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint32_t vqshlus_n_s32 (int32_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Sd,Sn,#n
+

Argument Preparation

a → Sn 

+0 << n << 31

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

uint64_t vqshlud_n_s64 (int64_t a, const int n)Signed saturating shift left unsigned

Description

A64 Instruction

SQSHLU Dd,Dn,#n
+

Argument Preparation

a → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vshrn_n_s16 (int16x8_t a, const int n)Shift right narrow

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

A64 Instruction

SHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vshrn_n_s32 (int32x4_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vshrn_n_s64 (int64x2_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vshrn_n_u16 (uint16x8_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vshrn_n_u32 (uint32x4_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vshrn_n_u64 (uint64x2_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)Shift right narrow

Description

A64 Instruction

SHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x8_t vqshrun_n_s16 (int16x8_t a, const int n)Signed saturating shift right unsigned narrow

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

A64 Instruction

SQSHRUN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqshrun_n_s32 (int32x4_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqshrun_n_s64 (int64x2_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8_t vqshrunh_n_s16 (int16_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN Bd,Hn,#n
+

Argument Preparation

a → Hn 

+1 << n << 8

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16_t vqshruns_n_s32 (int32_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN Hd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 16

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32_t vqshrund_n_s64 (int64_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN Sd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vqshrun_high_n_s16 (uint8x8_t r, int16x8_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vqshrun_high_n_s32 (uint16x4_t r, int32x4_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vqshrun_high_n_s64 (uint32x2_t r, int64x2_t a, const int n)Signed saturating shift right unsigned narrow

Description

A64 Instruction

SQSHRUN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x8_t vqrshrun_n_s16 (int16x8_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

A64 Instruction

SQRSHRUN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqrshrun_n_s32 (int32x4_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqrshrun_n_s64 (int64x2_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8_t vqrshrunh_n_s16 (int16_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN Bd,Hn,#n
+

Argument Preparation

a → Hn 

+1 << n << 8

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16_t vqrshruns_n_s32 (int32_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN Hd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 16

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32_t vqrshrund_n_s64 (int64_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN Sd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vqrshrun_high_n_s16 (uint8x8_t r, int16x8_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vqrshrun_high_n_s32 (uint16x4_t r, int32x4_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vqrshrun_high_n_s64 (uint32x2_t r, int64x2_t a, const int n)Signed saturating rounded shift right unsigned narrow

Description

A64 Instruction

SQRSHRUN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vqshrn_n_s16 (int16x8_t a, const int n)Signed saturating shift right narrow

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

A64 Instruction

SQSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vqshrn_n_s32 (int32x4_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vqshrn_n_s64 (int64x2_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqshrn_n_u16 (uint16x8_t a, const int n)Unsigned saturating shift right narrow

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

A64 Instruction

UQSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqshrn_n_u32 (uint32x4_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqshrn_n_u64 (uint64x2_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8_t vqshrnh_n_s16 (int16_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 

+1 << n << 8

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16_t vqshrns_n_s32 (int32_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 16

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int32_t vqshrnd_n_s64 (int64_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8_t vqshrnh_n_u16 (uint16_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 

+1 << n << 8

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16_t vqshrns_n_u32 (uint32_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 16

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32_t vqshrnd_n_u64 (uint64_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x16_t vqshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vqshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vqshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)Signed saturating shift right narrow

Description

A64 Instruction

SQSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vqshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vqshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vqshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)Unsigned saturating shift right narrow

Description

A64 Instruction

UQSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vrshrn_n_s16 (int16x8_t a, const int n)Rounding shift right narrow

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

A64 Instruction

RSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vrshrn_n_s32 (int32x4_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vrshrn_n_s64 (int64x2_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrshrn_n_u16 (uint16x8_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrshrn_n_u32 (uint32x4_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrshrn_n_u64 (uint64x2_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vrshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vrshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vrshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vrshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vrshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vrshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)Rounding shift right narrow

Description

A64 Instruction

RSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → 32(Vd) 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vqrshrn_n_s16 (int16x8_t a, const int n)Signed saturating rounded shift right narrow

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

A64 Instruction

SQRSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vqrshrn_n_s32 (int32x4_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vqrshrn_n_s64 (int64x2_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqrshrn_n_u16 (uint16x8_t a, const int n)Unsigned saturating rounded shift right narrow

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

A64 Instruction

UQRSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqrshrn_n_u32 (uint32x4_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqrshrn_n_u64 (uint64x2_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8_t vqrshrnh_n_s16 (int16_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 

+1 << n << 8

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16_t vqrshrns_n_s32 (int32_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 16

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int32_t vqrshrnd_n_s64 (int64_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8_t vqrshrnh_n_u16 (uint16_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 

+1 << n << 8

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16_t vqrshrns_n_u32 (uint32_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 16

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32_t vqrshrnd_n_u64 (uint64_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x16_t vqrshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vqrshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vqrshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)Signed saturating rounded shift right narrow

Description

A64 Instruction

SQRSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vqrshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vqrshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vqrshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)Unsigned saturating rounded shift right narrow

Description

A64 Instruction

UQRSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vshll_n_s8 (int8x8_t a, const int n)Signed shift left long

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

A64 Instruction

SSHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vshll_n_s16 (int16x4_t a, const int n)Signed shift left long

Description

A64 Instruction

SSHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vshll_n_s32 (int32x2_t a, const int n)Signed shift left long

Description

A64 Instruction

SSHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vshll_n_u8 (uint8x8_t a, const int n)Unsigned shift left long

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

USHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+0 << n << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vshll_n_u16 (uint16x4_t a, const int n)Unsigned shift left long

Description

A64 Instruction

USHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+0 << n << 15

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vshll_n_u32 (uint32x2_t a, const int n)Unsigned shift left long

Description

A64 Instruction

USHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+0 << n << 31

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vshll_high_n_s8 (int8x16_t a, const int n)Signed shift left long

Description

A64 Instruction

SSHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vshll_high_n_s16 (int16x8_t a, const int n)Signed shift left long

Description

A64 Instruction

SSHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vshll_high_n_s32 (int32x4_t a, const int n)Signed shift left long

Description

A64 Instruction

SSHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vshll_high_n_u8 (uint8x16_t a, const int n)Unsigned shift left long

Description

A64 Instruction

USHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+0 << n << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vshll_high_n_u16 (uint16x8_t a, const int n)Unsigned shift left long

Description

A64 Instruction

USHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+0 << n << 15

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vshll_high_n_u32 (uint32x4_t a, const int n)Unsigned shift left long

Description

A64 Instruction

USHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+0 << n << 31

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vshll_n_s8 (int8x8_t a, const int n)Shift left long

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

SHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+8 << n << 8

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vshll_n_s16 (int16x4_t a, const int n)Shift left long

Description

A64 Instruction

SHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+16 << n << 16

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vshll_n_s32 (int32x2_t a, const int n)Shift left long

Description

A64 Instruction

SHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+32 << n << 32

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vshll_n_u8 (uint8x8_t a, const int n)Shift left long

Description

A64 Instruction

SHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 

+8 << n << 8

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vshll_n_u16 (uint16x4_t a, const int n)Shift left long

Description

A64 Instruction

SHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 

+16 << n << 16

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vshll_n_u32 (uint32x2_t a, const int n)Shift left long

Description

A64 Instruction

SHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+32 << n << 32

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vshll_high_n_s8 (int8x16_t a, const int n)Shift left long

Description

A64 Instruction

SHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+8 << n << 8

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vshll_high_n_s16 (int16x8_t a, const int n)Shift left long

Description

A64 Instruction

SHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+16 << n << 16

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vshll_high_n_s32 (int32x4_t a, const int n)Shift left long

Description

A64 Instruction

SHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+32 << n << 32

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vshll_high_n_u8 (uint8x16_t a, const int n)Shift left long

Description

A64 Instruction

SHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 

+8 << n << 8

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vshll_high_n_u16 (uint16x8_t a, const int n)Shift left long

Description

A64 Instruction

SHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 

+16 << n << 16

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vshll_high_n_u32 (uint32x4_t a, const int n)Shift left long

Description

A64 Instruction

SHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+32 << n << 32

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vsri_n_s8 (int8x8_t a, int8x8_t b, const int n)Shift right and insert

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

A64 Instruction

SRI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vsriq_n_s8 (int8x16_t a, int8x16_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vsri_n_s16 (int16x4_t a, int16x4_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsriq_n_s16 (int16x8_t a, int16x8_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vsri_n_s32 (int32x2_t a, int32x2_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsriq_n_s32 (int32x4_t a, int32x4_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vsri_n_s64 (int64x1_t a, int64x1_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsriq_n_s64 (int64x2_t a, int64x2_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vsri_n_u8 (uint8x8_t a, uint8x8_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vsriq_n_u8 (uint8x16_t a, uint8x16_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vsri_n_u16 (uint16x4_t a, uint16x4_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsriq_n_u16 (uint16x8_t a, uint16x8_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vsri_n_u32 (uint32x2_t a, uint32x2_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsriq_n_u32 (uint32x4_t a, uint32x4_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vsri_n_u64 (uint64x1_t a, uint64x1_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsriq_n_u64 (uint64x2_t a, uint64x2_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vsri_n_p64 (poly64x1_t a, poly64x1_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vsriq_n_p64 (poly64x2_t a, poly64x2_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A32/A64

poly8x8_t vsri_n_p8 (poly8x8_t a, poly8x8_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+1 << n << 8

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vsriq_n_p8 (poly8x16_t a, poly8x16_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+1 << n << 8

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vsri_n_p16 (poly16x4_t a, poly16x4_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+1 << n << 16

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vsriq_n_p16 (poly16x8_t a, poly16x8_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+1 << n << 16

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vsrid_n_s64 (int64_t a, int64_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A64

uint64_t vsrid_n_u64 (uint64_t a, uint64_t b, const int n)Shift right and insert

Description

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A64

int8x8_t vsli_n_s8 (int8x8_t a, int8x8_t b, const int n)Shift left and insert

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

A64 Instruction

SLI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vsliq_n_s8 (int8x16_t a, int8x16_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vsli_n_s16 (int16x4_t a, int16x4_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsliq_n_s16 (int16x8_t a, int16x8_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vsli_n_s32 (int32x2_t a, int32x2_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsliq_n_s32 (int32x4_t a, int32x4_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vsli_n_s64 (int64x1_t a, int64x1_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsliq_n_s64 (int64x2_t a, int64x2_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vsli_n_u8 (uint8x8_t a, uint8x8_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vsliq_n_u8 (uint8x16_t a, uint8x16_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vsli_n_u16 (uint16x4_t a, uint16x4_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsliq_n_u16 (uint16x8_t a, uint16x8_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vsli_n_u32 (uint32x2_t a, uint32x2_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+0 << n << 31

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsliq_n_u32 (uint32x4_t a, uint32x4_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+0 << n << 31

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vsli_n_u64 (uint64x1_t a, uint64x1_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsliq_n_u64 (uint64x2_t a, uint64x2_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vsli_n_p64 (poly64x1_t a, poly64x1_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vsliq_n_p64 (poly64x2_t a, poly64x2_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+0 << n << 63

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A32/A64

poly8x8_t vsli_n_p8 (poly8x8_t a, poly8x8_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vsliq_n_p8 (poly8x16_t a, poly8x16_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vsli_n_p16 (poly16x4_t a, poly16x4_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+0 << n << 15

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vsliq_n_p16 (poly16x8_t a, poly16x8_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+0 << n << 15

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

v7/A32/A64

int64_t vslid_n_s64 (int64_t a, int64_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A64

uint64_t vslid_n_u64 (uint64_t a, uint64_t b, const int n)Shift left and insert

Description

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 

+b → Dn 

+0 << n << 63

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;

Supported architectures

A64

int32x2_t vcvt_s32_f32 (float32x2_t a)Floating-point convert to signed integer, rounding toward zero

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTZS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vcvtq_s32_f32 (float32x4_t a)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcvt_u32_f32 (float32x2_t a)Floating-point convert to unsigned integer, rounding toward zero

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTZU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcvtq_u32_f32 (float32x4_t a)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vcvtn_s32_f32 (float32x2_t a)Floating-point convert to signed integer, rounding to nearest with ties to even

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTNS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x4_t vcvtnq_s32_f32 (float32x4_t a)Floating-point convert to signed integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x2_t vcvtn_u32_f32 (float32x2_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to even

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTNU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vcvtnq_u32_f32 (float32x4_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x2_t vcvtm_s32_f32 (float32x2_t a)Floating-point convert to signed integer, rounding toward minus infinity

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTMS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x4_t vcvtmq_s32_f32 (float32x4_t a)Floating-point convert to signed integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x2_t vcvtm_u32_f32 (float32x2_t a)Floating-point convert to unsigned integer, rounding toward minus infinity

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTMU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vcvtmq_u32_f32 (float32x4_t a)Floating-point convert to unsigned integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x2_t vcvtp_s32_f32 (float32x2_t a)Floating-point convert to signed integer, rounding toward plus infinity

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTPS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x4_t vcvtpq_s32_f32 (float32x4_t a)Floating-point convert to signed integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x2_t vcvtp_u32_f32 (float32x2_t a)Floating-point convert to unsigned integer, rounding toward plus infinity

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTPU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vcvtpq_u32_f32 (float32x4_t a)Floating-point convert to unsigned integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x2_t vcvta_s32_f32 (float32x2_t a)Floating-point convert to signed integer, rounding to nearest with ties to away

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTAS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32x4_t vcvtaq_s32_f32 (float32x4_t a)Floating-point convert to signed integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x2_t vcvta_u32_f32 (float32x2_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to away

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

A64 Instruction

FCVTAU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vcvtaq_u32_f32 (float32x4_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A32/A64

int32_t vcvts_s32_f32 (float32_t a)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint32_t vcvts_u32_f32 (float32_t a)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int32_t vcvtns_s32_f32 (float32_t a)Floating-point convert to signed integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNS Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint32_t vcvtns_u32_f32 (float32_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNU Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int32_t vcvtms_s32_f32 (float32_t a)Floating-point convert to signed integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMS Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint32_t vcvtms_u32_f32 (float32_t a)Floating-point convert to unsigned integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMU Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int32_t vcvtps_s32_f32 (float32_t a)Floating-point convert to signed integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPS Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint32_t vcvtps_u32_f32 (float32_t a)Floating-point convert to unsigned integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPU Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int32_t vcvtas_s32_f32 (float32_t a)Floating-point convert to signed integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAS Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint32_t vcvtas_u32_f32 (float32_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAU Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x1_t vcvt_s64_f64 (float64x1_t a)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x2_t vcvtq_s64_f64 (float64x2_t a)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcvt_u64_f64 (float64x1_t a)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcvtq_u64_f64 (float64x2_t a)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x1_t vcvtn_s64_f64 (float64x1_t a)Floating-point convert to signed integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x2_t vcvtnq_s64_f64 (float64x2_t a)Floating-point convert to signed integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcvtn_u64_f64 (float64x1_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcvtnq_u64_f64 (float64x2_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x1_t vcvtm_s64_f64 (float64x1_t a)Floating-point convert to signed integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x2_t vcvtmq_s64_f64 (float64x2_t a)Floating-point convert to signed integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcvtm_u64_f64 (float64x1_t a)Floating-point convert to unsigned integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcvtmq_u64_f64 (float64x2_t a)Floating-point convert to unsigned integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x1_t vcvtp_s64_f64 (float64x1_t a)Floating-point convert to signed integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x2_t vcvtpq_s64_f64 (float64x2_t a)Floating-point convert to signed integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcvtp_u64_f64 (float64x1_t a)Floating-point convert to unsigned integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcvtpq_u64_f64 (float64x2_t a)Floating-point convert to unsigned integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x1_t vcvta_s64_f64 (float64x1_t a)Floating-point convert to signed integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x2_t vcvtaq_s64_f64 (float64x2_t a)Floating-point convert to signed integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcvta_u64_f64 (float64x1_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcvtaq_u64_f64 (float64x2_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64_t vcvtd_s64_f64 (float64_t a)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64_t vcvtd_u64_f64 (float64_t a)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64_t vcvtnd_s64_f64 (float64_t a)Floating-point convert to signed integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64_t vcvtnd_u64_f64 (float64_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to even

Description

A64 Instruction

FCVTNU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64_t vcvtmd_s64_f64 (float64_t a)Floating-point convert to signed integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64_t vcvtmd_u64_f64 (float64_t a)Floating-point convert to unsigned integer, rounding toward minus infinity

Description

A64 Instruction

FCVTMU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64_t vcvtpd_s64_f64 (float64_t a)Floating-point convert to signed integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64_t vcvtpd_u64_f64 (float64_t a)Floating-point convert to unsigned integer, rounding toward plus infinity

Description

A64 Instruction

FCVTPU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64_t vcvtad_s64_f64 (float64_t a)Floating-point convert to signed integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64_t vcvtad_u64_f64 (float64_t a)Floating-point convert to unsigned integer, rounding to nearest with ties to away

Description

A64 Instruction

FCVTAU Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int32x2_t vcvt_n_s32_f32 (float32x2_t a, const int n)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vcvtq_n_s32_f32 (float32x4_t a, const int n)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcvt_n_u32_f32 (float32x2_t a, const int n)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcvtq_n_u32_f32 (float32x4_t a, const int n)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vcvts_n_s32_f32 (float32_t a, const int n)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Sd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint32_t vcvts_n_u32_f32 (float32_t a, const int n)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Sd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x1_t vcvt_n_s64_f64 (float64x1_t a, const int n)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64x2_t vcvtq_n_s64_f64 (float64x2_t a, const int n)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x1_t vcvt_n_u64_f64 (float64x1_t a, const int n)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vcvtq_n_u64_f64 (float64x2_t a, const int n)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

int64_t vcvtd_n_s64_f64 (float64_t a, const int n)Floating-point convert to signed integer, rounding toward zero

Description

A64 Instruction

FCVTZS Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

uint64_t vcvtd_n_u64_f64 (float64_t a, const int n)Floating-point convert to unsigned integer, rounding toward zero

Description

A64 Instruction

FCVTZU Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vcvt_f32_s32 (int32x2_t a)Signed integer convert to floating-point

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

A64 Instruction

SCVTF Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vcvtq_f32_s32 (int32x4_t a)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vcvt_f32_u32 (uint32x2_t a)Unsigned integer convert to floating-point

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

A64 Instruction

UCVTF Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vcvtq_f32_u32 (uint32x4_t a)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32_t vcvts_f32_s32 (int32_t a)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float32_t vcvts_f32_u32 (uint32_t a)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vcvt_f64_s64 (int64x1_t a)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vcvtq_f64_s64 (int64x2_t a)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vcvt_f64_u64 (uint64x1_t a)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vcvtq_f64_u64 (uint64x2_t a)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64_t vcvtd_f64_s64 (int64_t a)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64_t vcvtd_f64_u64 (uint64_t a)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vcvt_n_f32_s32 (int32x2_t a, const int n)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vcvtq_n_f32_s32 (int32x4_t a, const int n)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vcvt_n_f32_u32 (uint32x2_t a, const int n)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 

+1 << n << 32

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vcvtq_n_f32_u32 (uint32x4_t a, const int n)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 

+1 << n << 32

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32_t vcvts_n_f32_s32 (int32_t a, const int n)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Sd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float32_t vcvts_n_f32_u32 (uint32_t a, const int n)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Sd,Sn,#n
+

Argument Preparation

a → Sn 

+1 << n << 32

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vcvt_n_f64_s64 (int64x1_t a, const int n)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vcvtq_n_f64_s64 (int64x2_t a, const int n)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vcvt_n_f64_u64 (uint64x1_t a, const int n)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vcvtq_n_f64_u64 (uint64x2_t a, const int n)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 

+1 << n << 64

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64_t vcvtd_n_f64_s64 (int64_t a, const int n)Signed integer convert to floating-point

Description

A64 Instruction

SCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float64_t vcvtd_n_f64_u64 (uint64_t a, const int n)Unsigned integer convert to floating-point

Description

A64 Instruction

UCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 

+1 << n << 64

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;

Supported architectures

A64

float16x4_t vcvt_f16_f32 (float32x4_t a)Floating-point convert to lower precision narrow

Description

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.

A64 Instruction

FCVTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

float16x8_t vcvt_high_f16_f32 (float16x4_t r, float32x4_t a)Floating-point convert to lower precision narrow

Description

A64 Instruction

FCVTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;

Supported architectures

A64

float32x2_t vcvt_f32_f64 (float64x2_t a)Floating-point convert to lower precision narrow

Description

A64 Instruction

FCVTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;

Supported architectures

A64

float32x4_t vcvt_high_f32_f64 (float32x2_t r, float64x2_t a)Floating-point convert to lower precision narrow

Description

A64 Instruction

FCVTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;

Supported architectures

A64

float32x4_t vcvt_f32_f16 (float16x4_t a)Floating-point convert to higher precision long

Description

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.

A64 Instruction

FCVTL Vd.4S,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vcvt_high_f32_f16 (float16x8_t a)Floating-point convert to higher precision long

Description

A64 Instruction

FCVTL2 Vd.4S,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vcvt_f64_f32 (float32x2_t a)Floating-point convert to higher precision long

Description

A64 Instruction

FCVTL Vd.2D,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vcvt_high_f64_f32 (float32x4_t a)Floating-point convert to higher precision long

Description

A64 Instruction

FCVTL2 Vd.2D,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vcvtx_f32_f64 (float64x2_t a)Floating-point convert to lower precision narrow, rounding to odd

Description

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FCVTXN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD);
+
+Vpart[d, part] = result;

Supported architectures

A64

float32_t vcvtxd_f32_f64 (float64_t a)Floating-point convert to lower precision narrow, rounding to odd

Description

A64 Instruction

FCVTXN Sd,Dn
+

Argument Preparation

a → Dn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD);
+
+Vpart[d, part] = result;

Supported architectures

A64

float32x4_t vcvtx_high_f32_f64 (float32x2_t r, float64x2_t a)Floating-point convert to lower precision narrow, rounding to odd

Description

A64 Instruction

FCVTXN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD);
+
+Vpart[d, part] = result;

Supported architectures

A64

float32x2_t vrnd_f32 (float32x2_t a)Floating-point round to integral, toward zero

Description

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTZ Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndq_f32 (float32x4_t a)Floating-point round to integral, toward zero

Description

A64 Instruction

FRINTZ Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrnd_f64 (float64x1_t a)Floating-point round to integral, toward zero

Description

A64 Instruction

FRINTZ Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrndq_f64 (float64x2_t a)Floating-point round to integral, toward zero

Description

A64 Instruction

FRINTZ Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrndn_f32 (float32x2_t a)Floating-point round to integral, to nearest with ties to even

Description

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTN Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndnq_f32 (float32x4_t a)Floating-point round to integral, to nearest with ties to even

Description

A64 Instruction

FRINTN Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrndn_f64 (float64x1_t a)Floating-point round to integral, to nearest with ties to even

Description

A64 Instruction

FRINTN Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x2_t vrndnq_f64 (float64x2_t a)Floating-point round to integral, to nearest with ties to even

Description

A64 Instruction

FRINTN Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32_t vrndns_f32 (float32_t a)Floating-point round to integral, to nearest with ties to even

Description

A64 Instruction

FRINTN Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x2_t vrndm_f32 (float32x2_t a)Floating-point round to integral, toward minus infinity

Description

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTM Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndmq_f32 (float32x4_t a)Floating-point round to integral, toward minus infinity

Description

A64 Instruction

FRINTM Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrndm_f64 (float64x1_t a)Floating-point round to integral, toward minus infinity

Description

A64 Instruction

FRINTM Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrndmq_f64 (float64x2_t a)Floating-point round to integral, toward minus infinity

Description

A64 Instruction

FRINTM Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrndp_f32 (float32x2_t a)Floating-point round to integral, toward plus infinity

Description

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTP Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndpq_f32 (float32x4_t a)Floating-point round to integral, toward plus infinity

Description

A64 Instruction

FRINTP Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrndp_f64 (float64x1_t a)Floating-point round to integral, toward plus infinity

Description

A64 Instruction

FRINTP Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrndpq_f64 (float64x2_t a)Floating-point round to integral, toward plus infinity

Description

A64 Instruction

FRINTP Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrnda_f32 (float32x2_t a)Floating-point round to integral, to nearest with ties to away

Description

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTA Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndaq_f32 (float32x4_t a)Floating-point round to integral, to nearest with ties to away

Description

A64 Instruction

FRINTA Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrnda_f64 (float64x1_t a)Floating-point round to integral, to nearest with ties to away

Description

A64 Instruction

FRINTA Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrndaq_f64 (float64x2_t a)Floating-point round to integral, to nearest with ties to away

Description

A64 Instruction

FRINTA Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrndi_f32 (float32x2_t a)Floating-point round to integral, using current rounding mode

Description

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTI Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndiq_f32 (float32x4_t a)Floating-point round to integral, using current rounding mode

Description

A64 Instruction

FRINTI Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrndi_f64 (float64x1_t a)Floating-point round to integral, using current rounding mode

Description

A64 Instruction

FRINTI Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrndiq_f64 (float64x2_t a)Floating-point round to integral, using current rounding mode

Description

A64 Instruction

FRINTI Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrndx_f32 (float32x2_t a)Floating-point round to integral exact, using current rounding mode

Description

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

A64 Instruction

FRINTX Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float32x4_t vrndxq_f32 (float32x4_t a)Floating-point round to integral exact, using current rounding mode

Description

A64 Instruction

FRINTX Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A32/A64

float64x1_t vrndx_f64 (float64x1_t a)Floating-point round to integral exact, using current rounding mode

Description

A64 Instruction

FRINTX Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrndxq_f64 (float64x2_t a)Floating-point round to integral exact, using current rounding mode

Description

A64 Instruction

FRINTX Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vmovn_s16 (int16x8_t a)Extract narrow

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

A64 Instruction

XTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vmovn_s32 (int32x4_t a)Extract narrow

Description

A64 Instruction

XTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vmovn_s64 (int64x2_t a)Extract narrow

Description

A64 Instruction

XTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmovn_u16 (uint16x8_t a)Extract narrow

Description

A64 Instruction

XTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmovn_u32 (uint32x4_t a)Extract narrow

Description

A64 Instruction

XTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmovn_u64 (uint64x2_t a)Extract narrow

Description

A64 Instruction

XTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vmovn_high_s16 (int8x8_t r, int16x8_t a)Extract narrow

Description

A64 Instruction

XTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vmovn_high_s32 (int16x4_t r, int32x4_t a)Extract narrow

Description

A64 Instruction

XTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vmovn_high_s64 (int32x2_t r, int64x2_t a)Extract narrow

Description

A64 Instruction

XTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vmovn_high_u16 (uint8x8_t r, uint16x8_t a)Extract narrow

Description

A64 Instruction

XTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vmovn_high_u32 (uint16x4_t r, uint32x4_t a)Extract narrow

Description

A64 Instruction

XTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vmovn_high_u64 (uint32x2_t r, uint64x2_t a)Extract narrow

Description

A64 Instruction

XTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vmovl_s8 (int8x8_t a)Signed shift left long

Description

A64 Instruction

SSHLL Vd.8H,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmovl_s16 (int16x4_t a)Signed shift left long

Description

A64 Instruction

SSHLL Vd.4S,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmovl_s32 (int32x2_t a)Signed shift left long

Description

A64 Instruction

SSHLL Vd.2D,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmovl_u8 (uint8x8_t a)Unsigned shift left long

Description

A64 Instruction

USHLL Vd.8H,Vn.8B,#0
+

Argument Preparation

a → Vn.8B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmovl_u16 (uint16x4_t a)Unsigned shift left long

Description

A64 Instruction

USHLL Vd.4S,Vn.4H,#0
+

Argument Preparation

a → Vn.4H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmovl_u32 (uint32x2_t a)Unsigned shift left long

Description

A64 Instruction

USHLL Vd.2D,Vn.2S,#0
+

Argument Preparation

a → Vn.2S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmovl_high_s8 (int8x16_t a)Signed shift left long

Description

A64 Instruction

SSHLL2 Vd.8H,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmovl_high_s16 (int16x8_t a)Signed shift left long

Description

A64 Instruction

SSHLL2 Vd.4S,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmovl_high_s32 (int32x4_t a)Signed shift left long

Description

A64 Instruction

SSHLL2 Vd.2D,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmovl_high_u8 (uint8x16_t a)Unsigned shift left long

Description

A64 Instruction

USHLL2 Vd.8H,Vn.16B,#0
+

Argument Preparation

a → Vn.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmovl_high_u16 (uint16x8_t a)Unsigned shift left long

Description

A64 Instruction

USHLL2 Vd.4S,Vn.8H,#0
+

Argument Preparation

a → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmovl_high_u32 (uint32x4_t a)Unsigned shift left long

Description

A64 Instruction

USHLL2 Vd.2D,Vn.4S,#0
+

Argument Preparation

a → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqmovn_s16 (int16x8_t a)Signed saturating extract narrow

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

A64 Instruction

SQXTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vqmovn_s32 (int32x4_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vqmovn_s64 (int64x2_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqmovn_u16 (uint16x8_t a)Unsigned saturating extract narrow

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

A64 Instruction

UQXTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqmovn_u32 (uint32x4_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqmovn_u64 (uint64x2_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8_t vqmovnh_s16 (int16_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN Bd,Hn
+

Argument Preparation

a → Hn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16_t vqmovns_s32 (int32_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN Hd,Sn
+

Argument Preparation

a → Sn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int32_t vqmovnd_s64 (int64_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN Sd,Dn
+

Argument Preparation

a → Dn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8_t vqmovnh_u16 (uint16_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN Bd,Hn
+

Argument Preparation

a → Hn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16_t vqmovns_u32 (uint32_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN Hd,Sn
+

Argument Preparation

a → Sn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32_t vqmovnd_u64 (uint64_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN Sd,Dn
+

Argument Preparation

a → Dn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int8x16_t vqmovn_high_s16 (int8x8_t r, int16x8_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vqmovn_high_s32 (int16x4_t r, int32x4_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vqmovn_high_s64 (int32x2_t r, int64x2_t a)Signed saturating extract narrow

Description

A64 Instruction

SQXTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vqmovn_high_u16 (uint8x8_t r, uint16x8_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vqmovn_high_u32 (uint16x4_t r, uint32x4_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vqmovn_high_u64 (uint32x2_t r, uint64x2_t a)Unsigned saturating extract narrow

Description

A64 Instruction

UQXTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x8_t vqmovun_s16 (int16x8_t a)Signed saturating extract unsigned narrow

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

A64 Instruction

SQXTUN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqmovun_s32 (int32x4_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqmovun_s64 (int64x2_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8_t vqmovunh_s16 (int16_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN Bd,Hn
+

Argument Preparation

a → Hn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16_t vqmovuns_s32 (int32_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN Hd,Sn
+

Argument Preparation

a → Sn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32_t vqmovund_s64 (int64_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN Sd,Dn
+

Argument Preparation

a → Dn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vqmovun_high_s16 (uint8x8_t r, int16x8_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 

+a → Vn.8H

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vqmovun_high_s32 (uint16x4_t r, int32x4_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 

+a → Vn.4S

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vqmovun_high_s64 (uint32x2_t r, int64x2_t a)Signed saturating extract unsigned narrow

Description

A64 Instruction

SQXTUN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 

+a → Vn.2D

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;

Supported architectures

A64

int16x4_t vmla_lane_s16 (int16x4_t a, int16x4_t b, int16x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlaq_lane_s16 (int16x8_t a, int16x8_t b, int16x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmla_lane_s32 (int32x2_t a, int32x2_t b, int32x2_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlaq_lane_s32 (int32x4_t a, int32x4_t b, int32x2_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmla_lane_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlaq_lane_u16 (uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmla_lane_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlaq_lane_u32 (uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmla_lane_f32 (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)Undefined

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 1

Results

N/A → result
+

Supported architectures

v7/A32/A64

float32x4_t vmlaq_lane_f32 (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)Undefined

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 1

Results

N/A → result
+

Supported architectures

v7/A32/A64

int16x4_t vmla_laneq_s16 (int16x4_t a, int16x4_t b, int16x8_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vmlaq_laneq_s16 (int16x8_t a, int16x8_t b, int16x8_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

int32x2_t vmla_laneq_s32 (int32x2_t a, int32x2_t b, int32x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlaq_laneq_s32 (int32x4_t a, int32x4_t b, int32x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vmla_laneq_u16 (uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmlaq_laneq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vmla_laneq_u32 (uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlaq_laneq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmla_laneq_f32 (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)Undefined

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 3

Results

N/A → result
+

Supported architectures

A64

float32x4_t vmlaq_laneq_f32 (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)Undefined

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 3

Results

N/A → result
+

Supported architectures

A64

int32x4_t vmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlal_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlal_lane_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlal_lane_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlal_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlal_high_lane_u16 (uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlal_high_lane_u32 (uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlal_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlal_laneq_u16 (uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlal_laneq_u32 (uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlal_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlal_high_laneq_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlal_high_laneq_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmlal_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vqdmlalh_lane_s16 (int32_t a, int16_t b, int16x4_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 

+b → Hn 

+v → Vm.4H 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmlals_lane_s32 (int64_t a, int32_t b, int32x2_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 

+b → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlal_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlal_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqdmlalh_laneq_s16 (int32_t a, int16_t b, int16x8_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 

+b → Hn 

+v → Vm.8H 

+0 << lane << 7

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmlals_laneq_s32 (int64_t a, int32_t b, int32x4_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 

+b → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlal_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vmls_lane_s16 (int16x4_t a, int16x4_t b, int16x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlsq_lane_s16 (int16x8_t a, int16x8_t b, int16x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmls_lane_s32 (int32x2_t a, int32x2_t b, int32x2_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsq_lane_s32 (int32x4_t a, int32x4_t b, int32x2_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmls_lane_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlsq_lane_u16 (uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmls_lane_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsq_lane_u32 (uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmls_lane_f32 (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 1

Results

N/A → result
+

Supported architectures

v7/A32/A64

float32x4_t vmlsq_lane_f32 (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 1

Results

N/A → result
+

Supported architectures

v7/A32/A64

int16x4_t vmls_laneq_s16 (int16x4_t a, int16x4_t b, int16x8_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vmlsq_laneq_s16 (int16x8_t a, int16x8_t b, int16x8_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

int32x2_t vmls_laneq_s32 (int32x2_t a, int32x2_t b, int32x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlsq_laneq_s32 (int32x4_t a, int32x4_t b, int32x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vmls_laneq_u16 (uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmlsq_laneq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vmls_laneq_u32 (uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlsq_laneq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmls_laneq_f32 (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 3

Results

N/A → result
+

Supported architectures

A64

float32x4_t vmlsq_laneq_f32 (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 3

Results

N/A → result
+

Supported architectures

A64

int32x4_t vmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsl_lane_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlsl_lane_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlsl_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlsl_high_lane_u16 (uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlsl_high_lane_u32 (uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlsl_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlsl_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlsl_laneq_u16 (uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlsl_laneq_u32 (uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlsl_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlsl_high_laneq_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlsl_high_laneq_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vqdmlslh_lane_s16 (int32_t a, int16_t b, int16x4_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 

+b → Hn 

+v → Vm.4H 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmlsls_lane_s32 (int64_t a, int32_t b, int32x2_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 

+b → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlsl_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlsl_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqdmlslh_laneq_s16 (int32_t a, int16_t b, int16x8_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 

+b → Hn 

+v → Vm.8H 

+0 << lane << 7

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmlsls_laneq_s32 (int64_t a, int32_t b, int32x4_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 

+b → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlsl_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vmul_n_s16 (int16x4_t a, int16_t b)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmulq_n_s16 (int16x8_t a, int16_t b)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmul_n_s32 (int32x2_t a, int32_t b)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmulq_n_s32 (int32x4_t a, int32_t b)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmul_n_u16 (uint16x4_t a, uint16_t b)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmulq_n_u16 (uint16x8_t a, uint16_t b)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmul_n_u32 (uint32x2_t a, uint32_t b)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmulq_n_u32 (uint32x4_t a, uint32_t b)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmul_n_f32 (float32x2_t a, float32_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vmulq_n_f32 (float32x4_t a, float32_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmul_n_f64 (float64x1_t a, float64_t b)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Vm.D[0]
+

Argument Preparation

a → Dn 

+b → Vm.D[0]

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulq_n_f64 (float64x2_t a, float64_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[0]
+

Argument Preparation

a → Vn.2D 

+b → Vm.D[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int16x4_t vmul_lane_s16 (int16x4_t a, int16x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmulq_lane_s16 (int16x8_t a, int16x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmul_lane_s32 (int32x2_t a, int32x2_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmulq_lane_s32 (int32x4_t a, int32x2_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmul_lane_u16 (uint16x4_t a, uint16x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmulq_lane_u16 (uint16x8_t a, uint16x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmul_lane_u32 (uint32x2_t a, uint32x2_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmulq_lane_u32 (uint32x4_t a, uint32x2_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmul_lane_f32 (float32x2_t a, float32x2_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vmulq_lane_f32 (float32x4_t a, float32x2_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmul_lane_f64 (float64x1_t a, float64x1_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulq_lane_f64 (float64x2_t a, float64x1_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 

+v → Vm.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmuls_lane_f32 (float32_t a, float32x2_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vmuld_lane_f64 (float64_t a, float64x1_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Vm.S[lane]
+

Argument Preparation

a → Dn 

+v → Vm.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int16x4_t vmul_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vmulq_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

int32x2_t vmul_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmulq_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vmul_laneq_u16 (uint16x4_t a, uint16x8_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vmulq_laneq_u16 (uint16x8_t a, uint16x8_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vmul_laneq_u32 (uint32x2_t a, uint32x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmulq_laneq_u32 (uint32x4_t a, uint32x4_t v, const int lane)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;

Supported architectures

A64

float32x2_t vmul_laneq_f32 (float32x2_t a, float32x4_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vmulq_laneq_f32 (float32x4_t a, float32x4_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vmul_laneq_f64 (float64x1_t a, float64x2_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vmulq_laneq_f64 (float64x2_t a, float64x2_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 

+v → Vm.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmuls_laneq_f32 (float32_t a, float32x4_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vmuld_laneq_f64 (float64_t a, float64x2_t v, const int lane)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 

+v → Vm.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmull_n_s16 (int16x4_t a, int16_t b)Signed multiply long

Description

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmull_n_s32 (int32x2_t a, int32_t b)Signed multiply long

Description

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmull_n_u16 (uint16x4_t a, uint16_t b)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmull_n_u32 (uint32x2_t a, uint32_t b)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmull_high_n_s16 (int16x8_t a, int16_t b)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmull_high_n_s32 (int32x4_t a, int32_t b)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmull_high_n_u16 (uint16x8_t a, uint16_t b)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmull_high_n_u32 (uint32x4_t a, uint32_t b)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmull_lane_s16 (int16x4_t a, int16x4_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmull_lane_s32 (int32x2_t a, int32x2_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmull_lane_u16 (uint16x4_t a, uint16x4_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmull_lane_u32 (uint32x2_t a, uint32x2_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmull_high_lane_s16 (int16x8_t a, int16x4_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmull_high_lane_s32 (int32x4_t a, int32x2_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmull_high_lane_u16 (uint16x8_t a, uint16x4_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmull_high_lane_u32 (uint32x4_t a, uint32x2_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmull_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmull_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmull_laneq_u16 (uint16x4_t a, uint16x8_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmull_laneq_u32 (uint32x2_t a, uint32x4_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vmull_high_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmull_high_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)Signed multiply long

Description

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmull_high_laneq_u16 (uint16x8_t a, uint16x8_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmull_high_laneq_u32 (uint32x4_t a, uint32x4_t v, const int lane)Unsigned multiply long

Description

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_n_s16 (int16x4_t a, int16_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmull_n_s32 (int32x2_t a, int32_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqdmull_high_n_s16 (int16x8_t a, int16_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmull_high_n_s32 (int32x4_t a, int32_t b)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_lane_s16 (int16x4_t a, int16x4_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmull_lane_s32 (int32x2_t a, int32x2_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32_t vqdmullh_lane_s16 (int16_t a, int16x4_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 

+v → Vm.4H 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmulls_lane_s32 (int32_t a, int32x2_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_high_lane_s16 (int16x8_t a, int16x4_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmull_high_lane_s32 (int32x4_t a, int32x2_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmull_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqdmullh_laneq_s16 (int16_t a, int16x8_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 

+v → Vm.8H 

+0 << lane << 7

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqdmulls_laneq_s32 (int32_t a, int32x4_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmull_high_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmull_high_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)Signed saturating doubling multiply long

Description

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vqdmulh_n_s16 (int16x4_t a, int16_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqdmulhq_n_s16 (int16x8_t a, int16_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqdmulh_n_s32 (int32x2_t a, int32_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqdmulhq_n_s32 (int32x4_t a, int32_t b)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqdmulh_lane_s16 (int16x4_t a, int16x4_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqdmulhq_lane_s16 (int16x8_t a, int16x4_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqdmulh_lane_s32 (int32x2_t a, int32x2_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqdmulhq_lane_s32 (int32x4_t a, int32x2_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16_t vqdmulhh_lane_s16 (int16_t a, int16x4_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 

+v → Vm.4H 

+0 << lane << 3

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqdmulhs_lane_s32 (int32_t a, int32x2_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Sd,Sn,Vm.H[lane]
+

Argument Preparation

a → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vqdmulh_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x8_t vqdmulhq_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x2_t vqdmulh_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmulhq_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16_t vqdmulhh_laneq_s16 (int16_t a, int16x8_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 

+v → Vm.8H 

+0 << lane << 7

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqdmulhs_laneq_s32 (int32_t a, int32x4_t v, const int lane)Signed saturating doubling multiply returning high half

Description

A64 Instruction

SQDMULH Sd,Sn,Vm.H[lane]
+

Argument Preparation

a → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vqrdmulh_n_s16 (int16x4_t a, int16_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 

+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqrdmulhq_n_s16 (int16x8_t a, int16_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 

+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqrdmulh_n_s32 (int32x2_t a, int32_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 

+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqrdmulhq_n_s32 (int32x4_t a, int32_t b)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 

+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqrdmulh_lane_s16 (int16x4_t a, int16x4_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqrdmulhq_lane_s16 (int16x8_t a, int16x4_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqrdmulh_lane_s32 (int32x2_t a, int32x2_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqrdmulhq_lane_s32 (int32x4_t a, int32x2_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16_t vqrdmulhh_lane_s16 (int16_t a, int16x4_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 

+v → Vm.4H 

+0 << lane << 3

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqrdmulhs_lane_s32 (int32_t a, int32x2_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vqrdmulh_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x8_t vqrdmulhq_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 

+v → Vm.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x2_t vqrdmulh_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqrdmulhq_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 

+v → Vm.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16_t vqrdmulhh_laneq_s16 (int16_t a, int16x8_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 

+v → Vm.8H 

+0 << lane << 7

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqrdmulhs_laneq_s32 (int32_t a, int32x4_t v, const int lane)Signed saturating rounding doubling multiply returning high half

Description

A64 Instruction

SQRDMULH Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 

+v → Vm.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmla_n_f32 (float32x2_t a, float32x2_t b, float32_t c)Undefined

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c) for i = 0 to 1
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

float32x4_t vmlaq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)Undefined

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c) for i = 0 to 3
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

int32x4_t vmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlal_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlal_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlal_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlal_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlal_n_s16 (int32x4_t a, int16x4_t b, int16_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmlal_n_s32 (int64x2_t a, int32x2_t b, int32_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqdmlal_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlal_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)Signed saturating doubling multiply-add long

Description

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16x4_t vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmls_n_f32 (float32x2_t a, float32x2_t b, float32_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c) for i = 0 to 1
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

float32x4_t vmlsq_n_f32 (float32x4_t a, float32x4_t b, float32_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c) for i = 0 to 3
+

Argument Preparation

a → N/A 

+b → N/A 

+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

int32x4_t vmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsl_n_u16 (uint32x4_t a, uint16x4_t b, uint16_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlsl_n_u32 (uint64x2_t a, uint32x2_t b, uint32_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vmlsl_high_n_u16 (uint32x4_t a, uint16x8_t b, uint16_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vmlsl_high_n_u32 (uint64x2_t a, uint32x4_t b, uint32_t c)Unsigned multiply-subtract long

Description

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vqdmlsl_n_s16 (int32x4_t a, int16x4_t b, int16_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqdmlsl_n_s32 (int64x2_t a, int32x2_t b, int32_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqdmlsl_high_n_s16 (int32x4_t a, int16x8_t b, int16_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H 

+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqdmlsl_high_n_s32 (int64x2_t a, int32x4_t b, int32_t c)Signed saturating doubling multiply-subtract long

Description

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S 

+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vabs_s8 (int8x8_t a)Absolute value

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ABS Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vabsq_s8 (int8x16_t a)Absolute value

Description

A64 Instruction

ABS Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vabs_s16 (int16x4_t a)Absolute value

Description

A64 Instruction

ABS Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vabsq_s16 (int16x8_t a)Absolute value

Description

A64 Instruction

ABS Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vabs_s32 (int32x2_t a)Absolute value

Description

A64 Instruction

ABS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vabsq_s32 (int32x4_t a)Absolute value

Description

A64 Instruction

ABS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vabs_f32 (float32x2_t a)Floating-point absolute value

Description

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FABS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vabsq_f32 (float32x4_t a)Floating-point absolute value

Description

A64 Instruction

FABS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vabs_s64 (int64x1_t a)Absolute value

Description

A64 Instruction

ABS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64_t vabsd_s64 (int64_t a)Absolute value

Description

A64 Instruction

ABS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vabsq_s64 (int64x2_t a)Absolute value

Description

A64 Instruction

ABS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

float64x1_t vabs_f64 (float64x1_t a)Floating-point absolute value

Description

A64 Instruction

FABS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

A64

float64x2_t vabsq_f64 (float64x2_t a)Floating-point absolute value

Description

A64 Instruction

FABS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqabs_s8 (int8x8_t a)Signed saturating absolute value

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

A64 Instruction

SQABS Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqabsq_s8 (int8x16_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqabs_s16 (int16x4_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqabsq_s16 (int16x8_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqabs_s32 (int32x2_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqabsq_s32 (int32x4_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqabs_s64 (int64x1_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqabsq_s64 (int64x2_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8_t vqabsb_s8 (int8_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Bd,Bn
+

Argument Preparation

a → Bn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16_t vqabsh_s16 (int16_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Hd,Hn
+

Argument Preparation

a → Hn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqabss_s32 (int32_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqabsd_s64 (int64_t a)Signed saturating absolute value

Description

A64 Instruction

SQABS Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vneg_s8 (int8x8_t a)Negate

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

NEG Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vnegq_s8 (int8x16_t a)Negate

Description

A64 Instruction

NEG Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vneg_s16 (int16x4_t a)Negate

Description

A64 Instruction

NEG Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vnegq_s16 (int16x8_t a)Negate

Description

A64 Instruction

NEG Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vneg_s32 (int32x2_t a)Negate

Description

A64 Instruction

NEG Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vnegq_s32 (int32x4_t a)Negate

Description

A64 Instruction

NEG Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vneg_f32 (float32x2_t a)Floating-point negate

Description

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FNEG Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vnegq_f32 (float32x4_t a)Floating-point negate

Description

A64 Instruction

FNEG Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vneg_s64 (int64x1_t a)Negate

Description

A64 Instruction

NEG Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64_t vnegd_s64 (int64_t a)Negate

Description

A64 Instruction

NEG Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vnegq_s64 (int64x2_t a)Negate

Description

A64 Instruction

NEG Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

float64x1_t vneg_f64 (float64x1_t a)Floating-point negate

Description

A64 Instruction

FNEG Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

A64

float64x2_t vnegq_f64 (float64x2_t a)Floating-point negate

Description

A64 Instruction

FNEG Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqneg_s8 (int8x8_t a)Signed saturating negate

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

A64 Instruction

SQNEG Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqnegq_s8 (int8x16_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqneg_s16 (int16x4_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqnegq_s16 (int16x8_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqneg_s32 (int32x2_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqnegq_s32 (int32x4_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqneg_s64 (int64x1_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64x2_t vqnegq_s64 (int64x2_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8_t vqnegb_s8 (int8_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Bd,Bn
+

Argument Preparation

a → Bn

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int16_t vqnegh_s16 (int16_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Hd,Hn
+

Argument Preparation

a → Hn

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int32_t vqnegs_s32 (int32_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int64_t vqnegd_s64 (int64_t a)Signed saturating negate

Description

A64 Instruction

SQNEG Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;

Supported architectures

A64

int8x8_t vcls_s8 (int8x8_t a)Count leading sign bits

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

A64 Instruction

CLS Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vclsq_s8 (int8x16_t a)Count leading sign bits

Description

A64 Instruction

CLS Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vcls_s16 (int16x4_t a)Count leading sign bits

Description

A64 Instruction

CLS Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vclsq_s16 (int16x8_t a)Count leading sign bits

Description

A64 Instruction

CLS Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vcls_s32 (int32x2_t a)Count leading sign bits

Description

A64 Instruction

CLS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vclsq_s32 (int32x4_t a)Count leading sign bits

Description

A64 Instruction

CLS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vclz_s8 (int8x8_t a)Count leading zero bits

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

CLZ Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vclzq_s8 (int8x16_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vclz_s16 (int16x4_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vclzq_s16 (int16x8_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vclz_s32 (int32x2_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vclzq_s32 (int32x4_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vclz_u8 (uint8x8_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vclzq_u8 (uint8x16_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vclz_u16 (uint16x4_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vclzq_u16 (uint16x8_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vclz_u32 (uint32x2_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vclzq_u32 (uint32x4_t a)Count leading zero bits

Description

A64 Instruction

CLZ Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vcnt_s8 (int8x8_t a)Population count per byte

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

CNT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vcntq_s8 (int8x16_t a)Population count per byte

Description

A64 Instruction

CNT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vcnt_u8 (uint8x8_t a)Population count per byte

Description

A64 Instruction

CNT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcntq_u8 (uint8x16_t a)Population count per byte

Description

A64 Instruction

CNT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vcnt_p8 (poly8x8_t a)Population count per byte

Description

A64 Instruction

CNT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vcntq_p8 (poly8x16_t a)Population count per byte

Description

A64 Instruction

CNT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrecpe_u32 (uint32x2_t a)Unsigned reciprocal estimate

Description

Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

URECPE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRecipEstimate(element);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrecpeq_u32 (uint32x4_t a)Unsigned reciprocal estimate

Description

A64 Instruction

URECPE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRecipEstimate(element);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vrecpe_f32 (float32x2_t a)Floating-point reciprocal estimate

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FRECPE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vrecpeq_f32 (float32x4_t a)Floating-point reciprocal estimate

Description

A64 Instruction

FRECPE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vrecpe_f64 (float64x1_t a)Floating-point reciprocal estimate

Description

A64 Instruction

FRECPE Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrecpeq_f64 (float64x2_t a)Floating-point reciprocal estimate

Description

A64 Instruction

FRECPE Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vrecpes_f32 (float32_t a)Floating-point reciprocal estimate

Description

A64 Instruction

FRECPE Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vrecped_f64 (float64_t a)Floating-point reciprocal estimate

Description

A64 Instruction

FRECPE Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrecps_f32 (float32x2_t a, float32x2_t b)Floating-point reciprocal step

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FRECPS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vrecpsq_f32 (float32x4_t a, float32x4_t b)Floating-point reciprocal step

Description

A64 Instruction

FRECPS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vrecps_f64 (float64x1_t a, float64x1_t b)Floating-point reciprocal step

Description

A64 Instruction

FRECPS Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrecpsq_f64 (float64x2_t a, float64x2_t b)Floating-point reciprocal step

Description

A64 Instruction

FRECPS Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float32_t vrecpss_f32 (float32_t a, float32_t b)Floating-point reciprocal step

Description

A64 Instruction

FRECPS Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float64_t vrecpsd_f64 (float64_t a, float64_t b)Floating-point reciprocal step

Description

A64 Instruction

FRECPS Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vsqrt_f32 (float32x2_t a)Floating-point square root

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FSQRT Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vsqrtq_f32 (float32x4_t a)Floating-point square root

Description

A64 Instruction

FSQRT Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vsqrt_f64 (float64x1_t a)Floating-point square root

Description

A64 Instruction

FSQRT Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vsqrtq_f64 (float64x2_t a)Floating-point square root

Description

A64 Instruction

FSQRT Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vrsqrte_u32 (uint32x2_t a)Unsigned reciprocal square root estimate

Description

Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

A64 Instruction

URSQRTE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRSqrtEstimate(element);
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrsqrteq_u32 (uint32x4_t a)Unsigned reciprocal square root estimate

Description

A64 Instruction

URSQRTE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRSqrtEstimate(element);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vrsqrte_f32 (float32x2_t a)Floating-point reciprocal square root estimate

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FRSQRTE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vrsqrteq_f32 (float32x4_t a)Floating-point reciprocal square root estimate

Description

A64 Instruction

FRSQRTE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vrsqrte_f64 (float64x1_t a)Floating-point reciprocal square root estimate

Description

A64 Instruction

FRSQRTE Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrsqrteq_f64 (float64x2_t a)Floating-point reciprocal square root estimate

Description

A64 Instruction

FRSQRTE Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vrsqrtes_f32 (float32_t a)Floating-point reciprocal square root estimate

Description

A64 Instruction

FRSQRTE Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vrsqrted_f64 (float64_t a)Floating-point reciprocal square root estimate

Description

A64 Instruction

FRSQRTE Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vrsqrts_f32 (float32x2_t a, float32x2_t b)Floating-point reciprocal square root step

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FRSQRTS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vrsqrtsq_f32 (float32x4_t a, float32x4_t b)Floating-point reciprocal square root step

Description

A64 Instruction

FRSQRTS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vrsqrts_f64 (float64x1_t a, float64x1_t b)Floating-point reciprocal square root step

Description

A64 Instruction

FRSQRTS Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vrsqrtsq_f64 (float64x2_t a, float64x2_t b)Floating-point reciprocal square root step

Description

A64 Instruction

FRSQRTS Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float32_t vrsqrtss_f32 (float32_t a, float32_t b)Floating-point reciprocal square root step

Description

A64 Instruction

FRSQRTS Sd,Sn,Sm
+

Argument Preparation

a → Sn 

+b → Sm

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

float64_t vrsqrtsd_f64 (float64_t a, float64_t b)Floating-point reciprocal square root step

Description

A64 Instruction

FRSQRTS Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vmvn_s8 (int8x8_t a)Bitwise NOT

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

int8x16_t vmvnq_s8 (int8x16_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

int16x4_t vmvn_s16 (int16x4_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

int16x8_t vmvnq_s16 (int16x8_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

int32x2_t vmvn_s32 (int32x2_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

int32x4_t vmvnq_s32 (int32x4_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

uint8x8_t vmvn_u8 (uint8x8_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

uint8x16_t vmvnq_u8 (uint8x16_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

uint16x4_t vmvn_u16 (uint16x4_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

uint16x8_t vmvnq_u16 (uint16x8_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

uint32x2_t vmvn_u32 (uint32x2_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

uint32x4_t vmvnq_u32 (uint32x4_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

poly8x8_t vmvn_p8 (poly8x8_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

poly8x16_t vmvnq_p8 (poly8x16_t a)Bitwise NOT

Description

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

int8x8_t vand_s8 (int8x8_t a, int8x8_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vandq_s8 (int8x16_t a, int8x16_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vand_s16 (int16x4_t a, int16x4_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vandq_s16 (int16x8_t a, int16x8_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vand_s32 (int32x2_t a, int32x2_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vandq_s32 (int32x4_t a, int32x4_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vand_s64 (int64x1_t a, int64x1_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Dd,Dn,Dm
+

Argument Preparation

a → Dn 

+b → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vandq_s64 (int64x2_t a, int64x2_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vand_u8 (uint8x8_t a, uint8x8_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vandq_u8 (uint8x16_t a, uint8x16_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vand_u16 (uint16x4_t a, uint16x4_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vandq_u16 (uint16x8_t a, uint16x8_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vand_u32 (uint32x2_t a, uint32x2_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vandq_u32 (uint32x4_t a, uint32x4_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vand_u64 (uint64x1_t a, uint64x1_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vandq_u64 (uint64x2_t a, uint64x2_t b)Bitwise AND

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vorr_s8 (int8x8_t a, int8x8_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vorrq_s8 (int8x16_t a, int8x16_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vorr_s16 (int16x4_t a, int16x4_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vorrq_s16 (int16x8_t a, int16x8_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vorr_s32 (int32x2_t a, int32x2_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vorrq_s32 (int32x4_t a, int32x4_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vorr_s64 (int64x1_t a, int64x1_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vorrq_s64 (int64x2_t a, int64x2_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vorr_u8 (uint8x8_t a, uint8x8_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vorrq_u8 (uint8x16_t a, uint8x16_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vorr_u16 (uint16x4_t a, uint16x4_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vorrq_u16 (uint16x8_t a, uint16x8_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vorr_u32 (uint32x2_t a, uint32x2_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vorrq_u32 (uint32x4_t a, uint32x4_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vorr_u64 (uint64x1_t a, uint64x1_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vorrq_u64 (uint64x2_t a, uint64x2_t b)Bitwise inclusive OR

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t veor_s8 (int8x8_t a, int8x8_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int8x16_t veorq_s8 (int8x16_t a, int8x16_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int16x4_t veor_s16 (int16x4_t a, int16x4_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int16x8_t veorq_s16 (int16x8_t a, int16x8_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int32x2_t veor_s32 (int32x2_t a, int32x2_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int32x4_t veorq_s32 (int32x4_t a, int32x4_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int64x1_t veor_s64 (int64x1_t a, int64x1_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int64x2_t veorq_s64 (int64x2_t a, int64x2_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint8x8_t veor_u8 (uint8x8_t a, uint8x8_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint8x16_t veorq_u8 (uint8x16_t a, uint8x16_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint16x4_t veor_u16 (uint16x4_t a, uint16x4_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint16x8_t veorq_u16 (uint16x8_t a, uint16x8_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint32x2_t veor_u32 (uint32x2_t a, uint32x2_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint32x4_t veorq_u32 (uint32x4_t a, uint32x4_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint64x1_t veor_u64 (uint64x1_t a, uint64x1_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint64x2_t veorq_u64 (uint64x2_t a, uint64x2_t b)Bitwise exclusive OR

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int8x8_t vbic_s8 (int8x8_t a, int8x8_t b)Bitwise bit clear

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vbicq_s8 (int8x16_t a, int8x16_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vbic_s16 (int16x4_t a, int16x4_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vbicq_s16 (int16x8_t a, int16x8_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vbic_s32 (int32x2_t a, int32x2_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vbicq_s32 (int32x4_t a, int32x4_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vbic_s64 (int64x1_t a, int64x1_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vbicq_s64 (int64x2_t a, int64x2_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vbic_u8 (uint8x8_t a, uint8x8_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vbicq_u8 (uint8x16_t a, uint8x16_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vbic_u16 (uint16x4_t a, uint16x4_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vbicq_u16 (uint16x8_t a, uint16x8_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vbic_u32 (uint32x2_t a, uint32x2_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vbicq_u32 (uint32x4_t a, uint32x4_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vbic_u64 (uint64x1_t a, uint64x1_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vbicq_u64 (uint64x2_t a, uint64x2_t b)Bitwise bit clear

Description

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vorn_s8 (int8x8_t a, int8x8_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vornq_s8 (int8x16_t a, int8x16_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vorn_s16 (int16x4_t a, int16x4_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vornq_s16 (int16x8_t a, int16x8_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vorn_s32 (int32x2_t a, int32x2_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vornq_s32 (int32x4_t a, int32x4_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vorn_s64 (int64x1_t a, int64x1_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vornq_s64 (int64x2_t a, int64x2_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vorn_u8 (uint8x8_t a, uint8x8_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vornq_u8 (uint8x16_t a, uint8x16_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vorn_u16 (uint16x4_t a, uint16x4_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vornq_u16 (uint16x8_t a, uint16x8_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vorn_u32 (uint32x2_t a, uint32x2_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vornq_u32 (uint32x4_t a, uint32x4_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vorn_u64 (uint64x1_t a, uint64x1_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vornq_u64 (uint64x2_t a, uint64x2_t b)Bitwise inclusive OR NOT

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vbsl_s8 (uint8x8_t a, int8x8_t b, int8x8_t c)Bitwise select

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int8x16_t vbslq_s8 (uint8x16_t a, int8x16_t b, int8x16_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int16x4_t vbsl_s16 (uint16x4_t a, int16x4_t b, int16x4_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int16x8_t vbslq_s16 (uint16x8_t a, int16x8_t b, int16x8_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int32x2_t vbsl_s32 (uint32x2_t a, int32x2_t b, int32x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int32x4_t vbslq_s32 (uint32x4_t a, int32x4_t b, int32x4_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int64x1_t vbsl_s64 (uint64x1_t a, int64x1_t b, int64x1_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int64x2_t vbslq_s64 (uint64x2_t a, int64x2_t b, int64x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint8x8_t vbsl_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint8x16_t vbslq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint16x4_t vbsl_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint16x8_t vbslq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint32x2_t vbsl_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint32x4_t vbslq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint64x1_t vbsl_u64 (uint64x1_t a, uint64x1_t b, uint64x1_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint64x2_t vbslq_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly64x1_t vbsl_p64 (poly64x1_t a, poly64x1_t b, poly64x1_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

A32/A64

poly64x2_t vbslq_p64 (poly64x2_t a, poly64x2_t b, poly64x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

A32/A64

float32x2_t vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

float32x4_t vbslq_f32 (uint32x4_t a, float32x4_t b, float32x4_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly8x8_t vbsl_p8 (uint8x8_t a, poly8x8_t b, poly8x8_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly8x16_t vbslq_p8 (uint8x16_t a, poly8x16_t b, poly8x16_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly16x4_t vbsl_p16 (uint16x4_t a, poly16x4_t b, poly16x4_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly16x8_t vbslq_p16 (uint16x8_t a, poly16x8_t b, poly16x8_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

float64x1_t vbsl_f64 (uint64x1_t a, float64x1_t b, float64x1_t c)Bitwise select

Description

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 

+b → Vn.8B 

+c → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

A64

float64x2_t vbslq_f64 (uint64x2_t a, float64x2_t b, float64x2_t c)Bitwise select

Description

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 

+b → Vn.16B 

+c → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

A64

int8x8_t vcopy_lane_s8 (int8x8_t a, const int lane1, int8x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 

+0 << lane1 << 7 

+b → Vn.8B 

+0 << lane2 << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x16_t vcopyq_lane_s8 (int8x16_t a, const int lane1, int8x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 

+0 << lane1 << 15 

+b → Vn.8B 

+0 << lane2 << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int16x4_t vcopy_lane_s16 (int16x4_t a, const int lane1, int16x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 

+0 << lane1 << 3 

+b → Vn.4H 

+0 << lane2 << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int16x8_t vcopyq_lane_s16 (int16x8_t a, const int lane1, int16x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 

+0 << lane1 << 7 

+b → Vn.4H 

+0 << lane2 << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int32x2_t vcopy_lane_s32 (int32x2_t a, const int lane1, int32x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 

+0 << lane1 << 1 

+b → Vn.2S 

+0 << lane2 << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int32x4_t vcopyq_lane_s32 (int32x4_t a, const int lane1, int32x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 

+0 << lane1 << 3 

+b → Vn.2S 

+0 << lane2 << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int64x1_t vcopy_lane_s64 (int64x1_t a, const int lane1, int64x1_t b, const int lane2)Duplicate general-purpose register to vector

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.1D 

+0 << lane2 << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int64x2_t vcopyq_lane_s64 (int64x2_t a, const int lane1, int64x1_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.1D 

+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x8_t vcopy_lane_u8 (uint8x8_t a, const int lane1, uint8x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 

+0 << lane1 << 7 

+b → Vn.8B 

+0 << lane2 << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x16_t vcopyq_lane_u8 (uint8x16_t a, const int lane1, uint8x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 

+0 << lane1 << 15 

+b → Vn.8B 

+0 << lane2 << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16x4_t vcopy_lane_u16 (uint16x4_t a, const int lane1, uint16x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 

+0 << lane1 << 3 

+b → Vn.4H 

+0 << lane2 << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16x8_t vcopyq_lane_u16 (uint16x8_t a, const int lane1, uint16x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 

+0 << lane1 << 7 

+b → Vn.4H 

+0 << lane2 << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32x2_t vcopy_lane_u32 (uint32x2_t a, const int lane1, uint32x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 

+0 << lane1 << 1 

+b → Vn.2S 

+0 << lane2 << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32x4_t vcopyq_lane_u32 (uint32x4_t a, const int lane1, uint32x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 

+0 << lane1 << 3 

+b → Vn.2S 

+0 << lane2 << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64x1_t vcopy_lane_u64 (uint64x1_t a, const int lane1, uint64x1_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.1D 

+0 << lane2 << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64x2_t vcopyq_lane_u64 (uint64x2_t a, const int lane1, uint64x1_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.1D 

+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly64x1_t vcopy_lane_p64 (poly64x1_t a, const int lane1, poly64x1_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.1D 

+0 << lane2 << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vcopyq_lane_p64 (poly64x2_t a, const int lane1, poly64x1_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.1D 

+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float32x2_t vcopy_lane_f32 (float32x2_t a, const int lane1, float32x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 

+0 << lane1 << 1 

+b → Vn.2S 

+0 << lane2 << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

float32x4_t vcopyq_lane_f32 (float32x4_t a, const int lane1, float32x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 

+0 << lane1 << 3 

+b → Vn.2S 

+0 << lane2 << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x1_t vcopy_lane_f64 (float64x1_t a, const int lane1, float64x1_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.1D 

+0 << lane2 << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x2_t vcopyq_lane_f64 (float64x2_t a, const int lane1, float64x1_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.1D 

+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8x8_t vcopy_lane_p8 (poly8x8_t a, const int lane1, poly8x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 

+0 << lane1 << 7 

+b → Vn.8B 

+0 << lane2 << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8x16_t vcopyq_lane_p8 (poly8x16_t a, const int lane1, poly8x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 

+0 << lane1 << 15 

+b → Vn.8B 

+0 << lane2 << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16x4_t vcopy_lane_p16 (poly16x4_t a, const int lane1, poly16x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 

+0 << lane1 << 3 

+b → Vn.4H 

+0 << lane2 << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16x8_t vcopyq_lane_p16 (poly16x8_t a, const int lane1, poly16x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 

+0 << lane1 << 7 

+b → Vn.4H 

+0 << lane2 << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vcopy_laneq_s8 (int8x8_t a, const int lane1, int8x16_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 

+0 << lane1 << 7 

+b → Vn.16B 

+0 << lane2 << 15

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x16_t vcopyq_laneq_s8 (int8x16_t a, const int lane1, int8x16_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 

+0 << lane1 << 15 

+b → Vn.16B 

+0 << lane2 << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int16x4_t vcopy_laneq_s16 (int16x4_t a, const int lane1, int16x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 

+0 << lane1 << 3 

+b → Vn.8H 

+0 << lane2 << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int16x8_t vcopyq_laneq_s16 (int16x8_t a, const int lane1, int16x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 

+0 << lane1 << 7 

+b → Vn.8H 

+0 << lane2 << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int32x2_t vcopy_laneq_s32 (int32x2_t a, const int lane1, int32x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 

+0 << lane1 << 1 

+b → Vn.4S 

+0 << lane2 << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int32x4_t vcopyq_laneq_s32 (int32x4_t a, const int lane1, int32x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 

+0 << lane1 << 3 

+b → Vn.4S 

+0 << lane2 << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int64x1_t vcopy_laneq_s64 (int64x1_t a, const int lane1, int64x2_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.2D 

+0 << lane2 << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int64x2_t vcopyq_laneq_s64 (int64x2_t a, const int lane1, int64x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.2D 

+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x8_t vcopy_laneq_u8 (uint8x8_t a, const int lane1, uint8x16_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 

+0 << lane1 << 7 

+b → Vn.16B 

+0 << lane2 << 15

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x16_t vcopyq_laneq_u8 (uint8x16_t a, const int lane1, uint8x16_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 

+0 << lane1 << 15 

+b → Vn.16B 

+0 << lane2 << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16x4_t vcopy_laneq_u16 (uint16x4_t a, const int lane1, uint16x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 

+0 << lane1 << 3 

+b → Vn.8H 

+0 << lane2 << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16x8_t vcopyq_laneq_u16 (uint16x8_t a, const int lane1, uint16x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 

+0 << lane1 << 7 

+b → Vn.8H 

+0 << lane2 << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32x2_t vcopy_laneq_u32 (uint32x2_t a, const int lane1, uint32x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 

+0 << lane1 << 1 

+b → Vn.4S 

+0 << lane2 << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32x4_t vcopyq_laneq_u32 (uint32x4_t a, const int lane1, uint32x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 

+0 << lane1 << 3 

+b → Vn.4S 

+0 << lane2 << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64x1_t vcopy_laneq_u64 (uint64x1_t a, const int lane1, uint64x2_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.2D 

+0 << lane2 << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64x2_t vcopyq_laneq_u64 (uint64x2_t a, const int lane1, uint64x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.2D 

+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly64x1_t vcopy_laneq_p64 (poly64x1_t a, const int lane1, poly64x2_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.2D 

+0 << lane2 << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vcopyq_laneq_p64 (poly64x2_t a, const int lane1, poly64x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.2D 

+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float32x2_t vcopy_laneq_f32 (float32x2_t a, const int lane1, float32x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 

+0 << lane1 << 1 

+b → Vn.4S 

+0 << lane2 << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

float32x4_t vcopyq_laneq_f32 (float32x4_t a, const int lane1, float32x4_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 

+0 << lane1 << 3 

+b → Vn.4S 

+0 << lane2 << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x1_t vcopy_laneq_f64 (float64x1_t a, const int lane1, float64x2_t b, const int lane2)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 

+0 << lane1 << 0 

+b → Vn.2D 

+0 << lane2 << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x2_t vcopyq_laneq_f64 (float64x2_t a, const int lane1, float64x2_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 

+0 << lane1 << 1 

+b → Vn.2D 

+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8x8_t vcopy_laneq_p8 (poly8x8_t a, const int lane1, poly8x16_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 

+0 << lane1 << 7 

+b → Vn.16B 

+0 << lane2 << 15

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8x16_t vcopyq_laneq_p8 (poly8x16_t a, const int lane1, poly8x16_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 

+0 << lane1 << 15 

+b → Vn.16B 

+0 << lane2 << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16x4_t vcopy_laneq_p16 (poly16x4_t a, const int lane1, poly16x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 

+0 << lane1 << 3 

+b → Vn.8H 

+0 << lane2 << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16x8_t vcopyq_laneq_p16 (poly16x8_t a, const int lane1, poly16x8_t b, const int lane2)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 

+0 << lane1 << 7 

+b → Vn.8H 

+0 << lane2 << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vrbit_s8 (int8x8_t a)Reverse bit order

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

RBIT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;

Supported architectures

A64

int8x16_t vrbitq_s8 (int8x16_t a)Reverse bit order

Description

A64 Instruction

RBIT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vrbit_u8 (uint8x8_t a)Reverse bit order

Description

A64 Instruction

RBIT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vrbitq_u8 (uint8x16_t a)Reverse bit order

Description

A64 Instruction

RBIT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vrbit_p8 (poly8x8_t a)Reverse bit order

Description

A64 Instruction

RBIT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vrbitq_p8 (poly8x16_t a)Reverse bit order

Description

A64 Instruction

RBIT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;

Supported architectures

A64

int8x8_t vcreate_s8 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vcreate_s16 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vcreate_s32 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vcreate_s64 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vcreate_u8 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vcreate_u16 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vcreate_u32 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vcreate_u64 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vcreate_p64 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float16x4_t vcreate_f16 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vcreate_f32 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vcreate_p8 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vcreate_p16 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vcreate_f64 (uint64_t a)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vdup_n_s8 (int8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vdupq_n_s8 (int8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vdup_n_s16 (int16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vdupq_n_s16 (int16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vdup_n_s32 (int32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vdupq_n_s32 (int32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vdup_n_s64 (int64_t value)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vdupq_n_s64 (int64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vdup_n_u8 (uint8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vdupq_n_u8 (uint8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vdup_n_u16 (uint16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vdupq_n_u16 (uint16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vdup_n_u32 (uint32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vdupq_n_u32 (uint32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vdup_n_u64 (uint64_t value)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vdupq_n_u64 (uint64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vdup_n_p64 (poly64_t value)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vdupq_n_p64 (poly64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float32x2_t vdup_n_f32 (float32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vdupq_n_f32 (float32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vdup_n_p8 (poly8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vdupq_n_p8 (poly8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vdup_n_p16 (poly16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vdupq_n_p16 (poly16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vdup_n_f64 (float64_t value)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x2_t vdupq_n_f64 (float64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vmov_n_s8 (int8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmovq_n_s8 (int8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmov_n_s16 (int16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmovq_n_s16 (int16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmov_n_s32 (int32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmovq_n_s32 (int32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vmov_n_s64 (int64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,rn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmovq_n_s64 (int64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmov_n_u8 (uint8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmovq_n_u8 (uint8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmov_n_u16 (uint16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmovq_n_u16 (uint16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmov_n_u32 (uint32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmovq_n_u32 (uint32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vmov_n_u64 (uint64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,rn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmovq_n_u64 (uint64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmov_n_f32 (float32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vmovq_n_f32 (float32_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vmov_n_p8 (poly8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vmovq_n_p8 (poly8_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vmov_n_p16 (poly16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vmovq_n_p16 (poly16_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmov_n_f64 (float64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,rn
+

Argument Preparation

value → rn

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x2_t vmovq_n_f64 (float64_t value)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vdup_lane_s8 (int8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vdupq_lane_s8 (int8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vdup_lane_s16 (int16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vdupq_lane_s16 (int16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vdup_lane_s32 (int32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vdupq_lane_s32 (int32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vdup_lane_s64 (int64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vdupq_lane_s64 (int64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vdup_lane_u8 (uint8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vdupq_lane_u8 (uint8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vdup_lane_u16 (uint16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vdupq_lane_u16 (uint16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vdup_lane_u32 (uint32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vdupq_lane_u32 (uint32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vdup_lane_u64 (uint64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vdupq_lane_u64 (uint64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vdup_lane_p64 (poly64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vdupq_lane_p64 (poly64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float32x2_t vdup_lane_f32 (float32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vdupq_lane_f32 (float32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vdup_lane_p8 (poly8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vdupq_lane_p8 (poly8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vdup_lane_p16 (poly16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vdupq_lane_p16 (poly16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vdup_lane_f64 (float64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x2_t vdupq_lane_f64 (float64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vdup_laneq_s8 (int8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x16_t vdupq_laneq_s8 (int8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int16x4_t vdup_laneq_s16 (int16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int16x8_t vdupq_laneq_s16 (int16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int32x2_t vdup_laneq_s32 (int32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int32x4_t vdupq_laneq_s32 (int32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int64x1_t vdup_laneq_s64 (int64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int64x2_t vdupq_laneq_s64 (int64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x8_t vdup_laneq_u8 (uint8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x16_t vdupq_laneq_u8 (uint8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16x4_t vdup_laneq_u16 (uint16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16x8_t vdupq_laneq_u16 (uint16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32x2_t vdup_laneq_u32 (uint32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32x4_t vdupq_laneq_u32 (uint32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64x1_t vdup_laneq_u64 (uint64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64x2_t vdupq_laneq_u64 (uint64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly64x1_t vdup_laneq_p64 (poly64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

poly64x2_t vdupq_laneq_p64 (poly64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float32x2_t vdup_laneq_f32 (float32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float32x4_t vdupq_laneq_f32 (float32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8x8_t vdup_laneq_p8 (poly8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8x16_t vdupq_laneq_p8 (poly8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16x4_t vdup_laneq_p16 (poly16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16x8_t vdupq_laneq_p16 (poly16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x1_t vdup_laneq_f64 (float64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64x2_t vdupq_laneq_f64 (float64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x16_t vcombine_s8 (int8x8_t low, int8x8_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.8B 

+high → Vm.8B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vcombine_s16 (int16x4_t low, int16x4_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 

+high → Vm.4H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vcombine_s32 (int32x2_t low, int32x2_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.2S 

+high → Vm.2S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vcombine_s64 (int64x1_t low, int64x1_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 

+high → Vm.1D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vcombine_u8 (uint8x8_t low, uint8x8_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.8B 

+high → Vm.8B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vcombine_u16 (uint16x4_t low, uint16x4_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 

+high → Vm.4H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vcombine_u32 (uint32x2_t low, uint32x2_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.2S 

+high → Vm.2S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vcombine_u64 (uint64x1_t low, uint64x1_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 

+high → Vm.1D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x2_t vcombine_p64 (poly64x1_t low, poly64x1_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 

+high → Vm.1D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float16x8_t vcombine_f16 (float16x4_t low, float16x4_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 

+high → Vm.4H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vcombine_f32 (float32x2_t low, float32x2_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.2S 

+high → Vm.2S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vcombine_p8 (poly8x8_t low, poly8x8_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.8B 

+high → Vm.8B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vcombine_p16 (poly16x4_t low, poly16x4_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 

+high → Vm.4H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x2_t vcombine_f64 (float64x1_t low, float64x1_t high)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 

+high → Vm.1D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vget_high_s8 (int8x16_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.16B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vget_high_s16 (int16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vget_high_s32 (int32x4_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.4S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vget_high_s64 (int64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vget_high_u8 (uint8x16_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.16B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vget_high_u16 (uint16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vget_high_u32 (uint32x4_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.4S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vget_high_u64 (uint64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vget_high_p64 (poly64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float16x4_t vget_high_f16 (float16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float32x2_t vget_high_f32 (float32x4_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.4S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vget_high_p8 (poly8x16_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.16B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vget_high_p16 (poly16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vget_high_f64 (float64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vget_low_s8 (int8x16_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.16B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vget_low_s16 (int16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vget_low_s32 (int32x4_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.4S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vget_low_s64 (int64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vget_low_u8 (uint8x16_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.16B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vget_low_u16 (uint16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vget_low_u32 (uint32x4_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.4S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vget_low_u64 (uint64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vget_low_p64 (poly64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

float16x4_t vget_low_f16 (float16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float32x2_t vget_low_f32 (float32x4_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.4S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vget_low_p8 (poly8x16_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.16B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vget_low_p16 (poly16x8_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vget_low_f64 (float64x2_t a)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8_t vdupb_lane_s8 (int8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int16_t vduph_lane_s16 (int16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int32_t vdups_lane_s32 (int32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int64_t vdupd_lane_s64 (int64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8_t vdupb_lane_u8 (uint8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16_t vduph_lane_u16 (uint16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32_t vdups_lane_u32 (uint32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64_t vdupd_lane_u64 (uint64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float32_t vdups_lane_f32 (float32x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64_t vdupd_lane_f64 (float64x1_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8_t vdupb_lane_p8 (poly8x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 

+0 << lane << 7

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16_t vduph_lane_p16 (poly16x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 

+0 << lane << 3

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8_t vdupb_laneq_s8 (int8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int16_t vduph_laneq_s16 (int16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int32_t vdups_laneq_s32 (int32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int64_t vdupd_laneq_s64 (int64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8_t vdupb_laneq_u8 (uint8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint16_t vduph_laneq_u16 (uint16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint32_t vdups_laneq_u32 (uint32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint64_t vdupd_laneq_u64 (uint64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float32_t vdups_laneq_f32 (float32x4_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

float64_t vdupd_laneq_f64 (float64x2_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly8_t vdupb_laneq_p8 (poly8x16_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 

+0 << lane << 15

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

poly16_t vduph_laneq_p16 (poly16x8_t vec, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 

+0 << lane << 7

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

int8x8_t vld1_s8 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

A64 Instruction

LD1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16_t vld1q_s8 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4_t vld1_s16 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8_t vld1q_s16 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2_t vld1_s32 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4_t vld1q_s32 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1_t vld1_s64 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x2_t vld1q_s64 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8_t vld1_u8 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16_t vld1q_u8 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4_t vld1_u16 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8_t vld1q_u16 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2_t vld1_u32 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4_t vld1q_u32 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1_t vld1_u64 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x2_t vld1q_u64 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1_t vld1_p64 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

poly64x2_t vld1q_p64 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

float16x4_t vld1_f16 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8_t vld1q_f16 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2_t vld1_f32 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4_t vld1q_f32 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8_t vld1_p8 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16_t vld1q_p8 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4_t vld1_p16 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8_t vld1q_p16 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float64x1_t vld1_f64 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2_t vld1q_f64 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8_t vld1_lane_s8 (int8_t const * ptr, int8x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8B 

+0 << lane << 7

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16_t vld1q_lane_s8 (int8_t const * ptr, int8x16_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.16B 

+0 << lane << 15

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4_t vld1_lane_s16 (int16_t const * ptr, int16x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4H 

+0 << lane << 3

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8_t vld1q_lane_s16 (int16_t const * ptr, int16x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8H 

+0 << lane << 7

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2_t vld1_lane_s32 (int32_t const * ptr, int32x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2S 

+0 << lane << 1

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4_t vld1q_lane_s32 (int32_t const * ptr, int32x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4S 

+0 << lane << 3

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1_t vld1_lane_s64 (int64_t const * ptr, int64x1_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.1D 

+0 << lane << 0

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x2_t vld1q_lane_s64 (int64_t const * ptr, int64x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2D 

+0 << lane << 1

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8_t vld1_lane_u8 (uint8_t const * ptr, uint8x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8B 

+0 << lane << 7

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16_t vld1q_lane_u8 (uint8_t const * ptr, uint8x16_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.16B 

+0 << lane << 15

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4_t vld1_lane_u16 (uint16_t const * ptr, uint16x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4H 

+0 << lane << 3

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8_t vld1q_lane_u16 (uint16_t const * ptr, uint16x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8H 

+0 << lane << 7

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2_t vld1_lane_u32 (uint32_t const * ptr, uint32x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2S 

+0 << lane << 1

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4_t vld1q_lane_u32 (uint32_t const * ptr, uint32x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4S 

+0 << lane << 3

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1_t vld1_lane_u64 (uint64_t const * ptr, uint64x1_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.1D 

+0 << lane << 0

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x2_t vld1q_lane_u64 (uint64_t const * ptr, uint64x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2D 

+0 << lane << 1

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1_t vld1_lane_p64 (poly64_t const * ptr, poly64x1_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.1D 

+0 << lane << 0

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

poly64x2_t vld1q_lane_p64 (poly64_t const * ptr, poly64x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2D 

+0 << lane << 1

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

float16x4_t vld1_lane_f16 (float16_t const * ptr, float16x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4H 

+0 << lane << 3

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8_t vld1q_lane_f16 (float16_t const * ptr, float16x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8H 

+0 << lane << 7

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2_t vld1_lane_f32 (float32_t const * ptr, float32x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2S 

+0 << lane << 1

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4_t vld1q_lane_f32 (float32_t const * ptr, float32x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4S 

+0 << lane << 3

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8_t vld1_lane_p8 (poly8_t const * ptr, poly8x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8B 

+0 << lane << 7

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16_t vld1q_lane_p8 (poly8_t const * ptr, poly8x16_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.16B 

+0 << lane << 15

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4_t vld1_lane_p16 (poly16_t const * ptr, poly16x4_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.4H 

+0 << lane << 3

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8_t vld1q_lane_p16 (poly16_t const * ptr, poly16x8_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.8H 

+0 << lane << 7

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float64x1_t vld1_lane_f64 (float64_t const * ptr, float64x1_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.1D 

+0 << lane << 0

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2_t vld1q_lane_f64 (float64_t const * ptr, float64x2_t src, const int lane)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src → Vt.2D 

+0 << lane << 1

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8_t vld1_dup_s8 (int8_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

A64 Instruction

LD1R {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16_t vld1q_dup_s8 (int8_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4_t vld1_dup_s16 (int16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8_t vld1q_dup_s16 (int16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2_t vld1_dup_s32 (int32_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4_t vld1q_dup_s32 (int32_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1_t vld1_dup_s64 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x2_t vld1q_dup_s64 (int64_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8_t vld1_dup_u8 (uint8_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16_t vld1q_dup_u8 (uint8_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4_t vld1_dup_u16 (uint16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8_t vld1q_dup_u16 (uint16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2_t vld1_dup_u32 (uint32_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4_t vld1q_dup_u32 (uint32_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1_t vld1_dup_u64 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x2_t vld1q_dup_u64 (uint64_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1_t vld1_dup_p64 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

poly64x2_t vld1q_dup_p64 (poly64_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

float16x4_t vld1_dup_f16 (float16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8_t vld1q_dup_f16 (float16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2_t vld1_dup_f32 (float32_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4_t vld1q_dup_f32 (float32_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4S → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8_t vld1_dup_p8 (poly8_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16_t vld1q_dup_p8 (poly8_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.16B → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4_t vld1_dup_p16 (poly16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.4H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8_t vld1q_dup_p16 (poly16_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.8H → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float64x1_t vld1_dup_f64 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.1D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2_t vld1q_dup_f64 (float64_t const * ptr)Load one single-element structure and replicate to all lanes (of one register)

Description

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt.2D → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1_s8 (int8_t * ptr, int8x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s8 (int8_t * ptr, int8x16_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s16 (int16_t * ptr, int16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s16 (int16_t * ptr, int16x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s32 (int32_t * ptr, int32x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s32 (int32_t * ptr, int32x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s64 (int64_t * ptr, int64x1_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s64 (int64_t * ptr, int64x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u8 (uint8_t * ptr, uint8x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u8 (uint8_t * ptr, uint8x16_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u16 (uint16_t * ptr, uint16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u16 (uint16_t * ptr, uint16x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u32 (uint32_t * ptr, uint32x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u32 (uint32_t * ptr, uint32x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u64 (uint64_t * ptr, uint64x1_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u64 (uint64_t * ptr, uint64x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p64 (poly64_t * ptr, poly64x1_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1q_p64 (poly64_t * ptr, poly64x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1_f16 (float16_t * ptr, float16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f16 (float16_t * ptr, float16x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f32 (float32_t * ptr, float32x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f32 (float32_t * ptr, float32x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p8 (poly8_t * ptr, poly8x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p8 (poly8_t * ptr, poly8x16_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p16 (poly16_t * ptr, poly16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p16 (poly16_t * ptr, poly16x8_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f64 (float64_t * ptr, float64x1_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1q_f64 (float64_t * ptr, float64x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1_lane_s8 (int8_t * ptr, int8x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_s8 (int8_t * ptr, int8x16_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_s16 (int16_t * ptr, int16x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_s16 (int16_t * ptr, int16x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_s32 (int32_t * ptr, int32x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_s32 (int32_t * ptr, int32x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_s64 (int64_t * ptr, int64x1_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_s64 (int64_t * ptr, int64x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_u8 (uint8_t * ptr, uint8x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_u8 (uint8_t * ptr, uint8x16_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_u16 (uint16_t * ptr, uint16x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_u16 (uint16_t * ptr, uint16x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_u32 (uint32_t * ptr, uint32x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_u32 (uint32_t * ptr, uint32x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_u64 (uint64_t * ptr, uint64x1_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_u64 (uint64_t * ptr, uint64x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_p64 (poly64_t * ptr, poly64x1_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1q_lane_p64 (poly64_t * ptr, poly64x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1_lane_f16 (float16_t * ptr, float16x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_f16 (float16_t * ptr, float16x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_f32 (float32_t * ptr, float32x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_f32 (float32_t * ptr, float32x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_p8 (poly8_t * ptr, poly8x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_p8 (poly8_t * ptr, poly8x16_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_p16 (poly16_t * ptr, poly16x4_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_lane_p16 (poly16_t * ptr, poly16x8_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_lane_f64 (float64_t * ptr, float64x1_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1q_lane_f64 (float64_t * ptr, float64x2_t val, const int lane)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x2_t vld2_s8 (int8_t const * ptr)Load single 2-element structure to one lane of two registers

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

A64 Instruction

LD2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x2_t vld2q_s8 (int8_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x2_t vld2_s16 (int16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x2_t vld2q_s16 (int16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x2_t vld2_s32 (int32_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x2_t vld2q_s32 (int32_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x2_t vld2_u8 (uint8_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x2_t vld2q_u8 (uint8_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x2_t vld2_u16 (uint16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x2_t vld2q_u16 (uint16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x2_t vld2_u32 (uint32_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x2_t vld2q_u32 (uint32_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x2_t vld2_f16 (float16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x2_t vld2q_f16 (float16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x2_t vld2_f32 (float32_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x2_t vld2q_f32 (float32_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x2_t vld2_p8 (poly8_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x2_t vld2q_p8 (poly8_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x2_t vld2_p16 (poly16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x2_t vld2q_p16 (poly16_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x2_t vld2_s64 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x2_t vld2_u64 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x2_t vld2_p64 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x2_t vld2q_s64 (int64_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x2_t vld2q_u64 (uint64_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x2_t vld2q_p64 (poly64_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x2_t vld2_f64 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x2_t vld2q_f64 (float64_t const * ptr)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x3_t vld3_s8 (int8_t const * ptr)Load single 3-element structure to one lane of three registers

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

A64 Instruction

LD3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x3_t vld3q_s8 (int8_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x3_t vld3_s16 (int16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x3_t vld3q_s16 (int16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x3_t vld3_s32 (int32_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x3_t vld3q_s32 (int32_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x3_t vld3_u8 (uint8_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x3_t vld3q_u8 (uint8_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x3_t vld3_u16 (uint16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x3_t vld3q_u16 (uint16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x3_t vld3_u32 (uint32_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x3_t vld3q_u32 (uint32_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x3_t vld3_f16 (float16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x3_t vld3q_f16 (float16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x3_t vld3_f32 (float32_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x3_t vld3q_f32 (float32_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x3_t vld3_p8 (poly8_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x3_t vld3q_p8 (poly8_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x3_t vld3_p16 (poly16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x3_t vld3q_p16 (poly16_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x3_t vld3_s64 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x3_t vld3_u64 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x3_t vld3_p64 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x3_t vld3q_s64 (int64_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x3_t vld3q_u64 (uint64_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x3_t vld3q_p64 (poly64_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x3_t vld3_f64 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x3_t vld3q_f64 (float64_t const * ptr)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x4_t vld4_s8 (int8_t const * ptr)Load single 4-element structure to one lane of four registers

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

A64 Instruction

LD4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x4_t vld4q_s8 (int8_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x4_t vld4_s16 (int16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x4_t vld4q_s16 (int16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x4_t vld4_s32 (int32_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x4_t vld4q_s32 (int32_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x4_t vld4_u8 (uint8_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x4_t vld4q_u8 (uint8_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x4_t vld4_u16 (uint16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x4_t vld4q_u16 (uint16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x4_t vld4_u32 (uint32_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x4_t vld4q_u32 (uint32_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x4_t vld4_f16 (float16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x4_t vld4q_f16 (float16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x4_t vld4_f32 (float32_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x4_t vld4q_f32 (float32_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x4_t vld4_p8 (poly8_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x4_t vld4q_p8 (poly8_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x4_t vld4_p16 (poly16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x4_t vld4q_p16 (poly16_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x4_t vld4_s64 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x4_t vld4_u64 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x4_t vld4_p64 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x4_t vld4q_s64 (int64_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x4_t vld4q_u64 (uint64_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x4_t vld4q_p64 (poly64_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x4_t vld4_f64 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x4_t vld4q_f64 (float64_t const * ptr)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x2_t vld2_dup_s8 (int8_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

A64 Instruction

LD2R {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x2_t vld2q_dup_s8 (int8_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x2_t vld2_dup_s16 (int16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x2_t vld2q_dup_s16 (int16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x2_t vld2_dup_s32 (int32_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x2_t vld2q_dup_s32 (int32_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x2_t vld2_dup_u8 (uint8_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x2_t vld2q_dup_u8 (uint8_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x2_t vld2_dup_u16 (uint16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x2_t vld2q_dup_u16 (uint16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x2_t vld2_dup_u32 (uint32_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x2_t vld2q_dup_u32 (uint32_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x2_t vld2_dup_f16 (float16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x2_t vld2q_dup_f16 (float16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x2_t vld2_dup_f32 (float32_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x2_t vld2q_dup_f32 (float32_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x2_t vld2_dup_p8 (poly8_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x2_t vld2q_dup_p8 (poly8_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x2_t vld2_dup_p16 (poly16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x2_t vld2q_dup_p16 (poly16_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x2_t vld2_dup_s64 (int64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x2_t vld2_dup_u64 (uint64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x2_t vld2_dup_p64 (poly64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x2_t vld2q_dup_s64 (int64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x2_t vld2q_dup_u64 (uint64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x2_t vld2q_dup_p64 (poly64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x2_t vld2_dup_f64 (float64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x2_t vld2q_dup_f64 (float64_t const * ptr)Load single 2-element structure and replicate to all lanes of two registers

Description

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x3_t vld3_dup_s8 (int8_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

A64 Instruction

LD3R {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x3_t vld3q_dup_s8 (int8_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x3_t vld3_dup_s16 (int16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x3_t vld3q_dup_s16 (int16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x3_t vld3_dup_s32 (int32_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x3_t vld3q_dup_s32 (int32_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x3_t vld3_dup_u8 (uint8_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x3_t vld3q_dup_u8 (uint8_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x3_t vld3_dup_u16 (uint16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x3_t vld3q_dup_u16 (uint16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x3_t vld3_dup_u32 (uint32_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x3_t vld3q_dup_u32 (uint32_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x3_t vld3_dup_f16 (float16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x3_t vld3q_dup_f16 (float16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x3_t vld3_dup_f32 (float32_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x3_t vld3q_dup_f32 (float32_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x3_t vld3_dup_p8 (poly8_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x3_t vld3q_dup_p8 (poly8_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x3_t vld3_dup_p16 (poly16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x3_t vld3q_dup_p16 (poly16_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x3_t vld3_dup_s64 (int64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x3_t vld3_dup_u64 (uint64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x3_t vld3_dup_p64 (poly64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x3_t vld3q_dup_s64 (int64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x3_t vld3q_dup_u64 (uint64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x3_t vld3q_dup_p64 (poly64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x3_t vld3_dup_f64 (float64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x3_t vld3q_dup_f64 (float64_t const * ptr)Load single 3-element structure and replicate to all lanes of three registers

Description

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x4_t vld4_dup_s8 (int8_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

A64 Instruction

LD4R {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x4_t vld4q_dup_s8 (int8_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x4_t vld4_dup_s16 (int16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x4_t vld4q_dup_s16 (int16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x4_t vld4_dup_s32 (int32_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x4_t vld4q_dup_s32 (int32_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x4_t vld4_dup_u8 (uint8_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x4_t vld4q_dup_u8 (uint8_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x4_t vld4_dup_u16 (uint16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x4_t vld4q_dup_u16 (uint16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x4_t vld4_dup_u32 (uint32_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x4_t vld4q_dup_u32 (uint32_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x4_t vld4_dup_f16 (float16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x4_t vld4q_dup_f16 (float16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x4_t vld4_dup_f32 (float32_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x4_t vld4q_dup_f32 (float32_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x4_t vld4_dup_p8 (poly8_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x4_t vld4q_dup_p8 (poly8_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x4_t vld4_dup_p16 (poly16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x4_t vld4q_dup_p16 (poly16_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x4_t vld4_dup_s64 (int64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x4_t vld4_dup_u64 (uint64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x4_t vld4_dup_p64 (poly64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x4_t vld4q_dup_s64 (int64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x4_t vld4q_dup_u64 (uint64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x4_t vld4q_dup_p64 (poly64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x4_t vld4_dup_f64 (float64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x4_t vld4q_dup_f64 (float64_t const * ptr)Load single 4-element structure and replicate to all lanes of four registers

Description

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_s8 (int8_t * ptr, int8x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_s8 (int8_t * ptr, int8x16x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_s16 (int16_t * ptr, int16x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_s16 (int16_t * ptr, int16x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_s32 (int32_t * ptr, int32x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_s32 (int32_t * ptr, int32x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_u8 (uint8_t * ptr, uint8x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_u8 (uint8_t * ptr, uint8x16x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_u16 (uint16_t * ptr, uint16x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_u16 (uint16_t * ptr, uint16x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_u32 (uint32_t * ptr, uint32x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_u32 (uint32_t * ptr, uint32x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_f16 (float16_t * ptr, float16x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_f16 (float16_t * ptr, float16x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_f32 (float32_t * ptr, float32x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_f32 (float32_t * ptr, float32x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_p8 (poly8_t * ptr, poly8x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_p8 (poly8_t * ptr, poly8x16x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_p16 (poly16_t * ptr, poly16x4x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_p16 (poly16_t * ptr, poly16x8x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_s64 (int64_t * ptr, int64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_u64 (uint64_t * ptr, uint64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_p64 (poly64_t * ptr, poly64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst2q_s64 (int64_t * ptr, int64x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_u64 (uint64_t * ptr, uint64x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_p64 (poly64_t * ptr, poly64x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_f64 (float64_t * ptr, float64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_f64 (float64_t * ptr, float64x2x2_t val)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3_s8 (int8_t * ptr, int8x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_s8 (int8_t * ptr, int8x16x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_s16 (int16_t * ptr, int16x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_s16 (int16_t * ptr, int16x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_s32 (int32_t * ptr, int32x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_s32 (int32_t * ptr, int32x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_u8 (uint8_t * ptr, uint8x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_u8 (uint8_t * ptr, uint8x16x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_u16 (uint16_t * ptr, uint16x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_u16 (uint16_t * ptr, uint16x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_u32 (uint32_t * ptr, uint32x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_u32 (uint32_t * ptr, uint32x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_f16 (float16_t * ptr, float16x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_f16 (float16_t * ptr, float16x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_f32 (float32_t * ptr, float32x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_f32 (float32_t * ptr, float32x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_p8 (poly8_t * ptr, poly8x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_p8 (poly8_t * ptr, poly8x16x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_p16 (poly16_t * ptr, poly16x4x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_p16 (poly16_t * ptr, poly16x8x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_s64 (int64_t * ptr, int64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_u64 (uint64_t * ptr, uint64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_p64 (poly64_t * ptr, poly64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst3q_s64 (int64_t * ptr, int64x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_u64 (uint64_t * ptr, uint64x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_p64 (poly64_t * ptr, poly64x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3_f64 (float64_t * ptr, float64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_f64 (float64_t * ptr, float64x2x3_t val)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_s8 (int8_t * ptr, int8x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_s8 (int8_t * ptr, int8x16x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_s16 (int16_t * ptr, int16x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_s16 (int16_t * ptr, int16x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_s32 (int32_t * ptr, int32x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_s32 (int32_t * ptr, int32x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_u8 (uint8_t * ptr, uint8x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_u8 (uint8_t * ptr, uint8x16x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_u16 (uint16_t * ptr, uint16x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_u16 (uint16_t * ptr, uint16x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_u32 (uint32_t * ptr, uint32x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_u32 (uint32_t * ptr, uint32x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_f16 (float16_t * ptr, float16x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_f16 (float16_t * ptr, float16x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_f32 (float32_t * ptr, float32x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_f32 (float32_t * ptr, float32x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_p8 (poly8_t * ptr, poly8x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_p8 (poly8_t * ptr, poly8x16x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_p16 (poly16_t * ptr, poly16x4x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_p16 (poly16_t * ptr, poly16x8x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_s64 (int64_t * ptr, int64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_u64 (uint64_t * ptr, uint64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_p64 (poly64_t * ptr, poly64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst4q_s64 (int64_t * ptr, int64x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_u64 (uint64_t * ptr, uint64x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_p64 (poly64_t * ptr, poly64x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_f64 (float64_t * ptr, float64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_f64 (float64_t * ptr, float64x2x4_t val)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int16x4x2_t vld2_lane_s16 (int16_t const * ptr, int16x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x2_t vld2q_lane_s16 (int16_t const * ptr, int16x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x2_t vld2_lane_s32 (int32_t const * ptr, int32x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x2_t vld2q_lane_s32 (int32_t const * ptr, int32x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x2_t vld2_lane_u16 (uint16_t const * ptr, uint16x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x2_t vld2q_lane_u16 (uint16_t const * ptr, uint16x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x2_t vld2_lane_u32 (uint32_t const * ptr, uint32x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x2_t vld2q_lane_u32 (uint32_t const * ptr, uint32x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x2_t vld2_lane_f16 (float16_t const * ptr, float16x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x2_t vld2q_lane_f16 (float16_t const * ptr, float16x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x2_t vld2_lane_f32 (float32_t const * ptr, float32x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x2_t vld2q_lane_f32 (float32_t const * ptr, float32x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x2_t vld2_lane_p16 (poly16_t const * ptr, poly16x4x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x2_t vld2q_lane_p16 (poly16_t const * ptr, poly16x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x8x2_t vld2_lane_s8 (int8_t const * ptr, int8x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x2_t vld2_lane_u8 (uint8_t const * ptr, uint8x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x2_t vld2_lane_p8 (poly8_t const * ptr, poly8x8x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x2_t vld2q_lane_s8 (int8_t const * ptr, int8x16x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint8x16x2_t vld2q_lane_u8 (uint8_t const * ptr, uint8x16x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly8x16x2_t vld2q_lane_p8 (poly8_t const * ptr, poly8x16x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int64x1x2_t vld2_lane_s64 (int64_t const * ptr, int64x1x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

ptr → Xn
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int64x2x2_t vld2q_lane_s64 (int64_t const * ptr, int64x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

ptr → Xn
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x1x2_t vld2_lane_u64 (uint64_t const * ptr, uint64x1x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x2_t vld2q_lane_u64 (uint64_t const * ptr, uint64x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x1x2_t vld2_lane_p64 (poly64_t const * ptr, poly64x1x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x2_t vld2q_lane_p64 (poly64_t const * ptr, poly64x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x2_t vld2_lane_f64 (float64_t const * ptr, float64x1x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x2_t vld2q_lane_f64 (float64_t const * ptr, float64x2x2_t src, const int lane)Load single 2-element structure to one lane of two registers

Description

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int16x4x3_t vld3_lane_s16 (int16_t const * ptr, int16x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x3_t vld3q_lane_s16 (int16_t const * ptr, int16x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x3_t vld3_lane_s32 (int32_t const * ptr, int32x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2S 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x3_t vld3q_lane_s32 (int32_t const * ptr, int32x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4S 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x3_t vld3_lane_u16 (uint16_t const * ptr, uint16x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x3_t vld3q_lane_u16 (uint16_t const * ptr, uint16x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x3_t vld3_lane_u32 (uint32_t const * ptr, uint32x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2S 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x3_t vld3q_lane_u32 (uint32_t const * ptr, uint32x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4S 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x3_t vld3_lane_f16 (float16_t const * ptr, float16x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x3_t vld3q_lane_f16 (float16_t const * ptr, float16x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x3_t vld3_lane_f32 (float32_t const * ptr, float32x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2S 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x3_t vld3q_lane_f32 (float32_t const * ptr, float32x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4S 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x3_t vld3_lane_p16 (poly16_t const * ptr, poly16x4x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x3_t vld3q_lane_p16 (poly16_t const * ptr, poly16x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x8x3_t vld3_lane_s8 (int8_t const * ptr, int8x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8B 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x3_t vld3_lane_u8 (uint8_t const * ptr, uint8x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8B 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x3_t vld3_lane_p8 (poly8_t const * ptr, poly8x8x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.8B 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x3_t vld3q_lane_s8 (int8_t const * ptr, int8x16x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.16B 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint8x16x3_t vld3q_lane_u8 (uint8_t const * ptr, uint8x16x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.16B 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly8x16x3_t vld3q_lane_p8 (poly8_t const * ptr, poly8x16x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.16B 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int64x1x3_t vld3_lane_s64 (int64_t const * ptr, int64x1x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int64x2x3_t vld3q_lane_s64 (int64_t const * ptr, int64x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x1x3_t vld3_lane_u64 (uint64_t const * ptr, uint64x1x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x3_t vld3q_lane_u64 (uint64_t const * ptr, uint64x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x1x3_t vld3_lane_p64 (poly64_t const * ptr, poly64x1x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x3_t vld3q_lane_p64 (poly64_t const * ptr, poly64x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x3_t vld3_lane_f64 (float64_t const * ptr, float64x1x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x3_t vld3q_lane_f64 (float64_t const * ptr, float64x2x3_t src, const int lane)Load single 3-element structure to one lane of three registers

Description

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int16x4x4_t vld4_lane_s16 (int16_t const * ptr, int16x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4H 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x4_t vld4q_lane_s16 (int16_t const * ptr, int16x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8H 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x4_t vld4_lane_s32 (int32_t const * ptr, int32x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2S 

+src.val[2] → Vt3.2S 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x4_t vld4q_lane_s32 (int32_t const * ptr, int32x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4S 

+src.val[2] → Vt3.4S 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x4_t vld4_lane_u16 (uint16_t const * ptr, uint16x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4H 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x4_t vld4q_lane_u16 (uint16_t const * ptr, uint16x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8H 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x4_t vld4_lane_u32 (uint32_t const * ptr, uint32x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2S 

+src.val[2] → Vt3.2S 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x4_t vld4q_lane_u32 (uint32_t const * ptr, uint32x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4S 

+src.val[2] → Vt3.4S 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x4_t vld4_lane_f16 (float16_t const * ptr, float16x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4H 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x4_t vld4q_lane_f16 (float16_t const * ptr, float16x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8H 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x4_t vld4_lane_f32 (float32_t const * ptr, float32x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2S 

+src.val[2] → Vt3.2S 

+src.val[1] → Vt2.2S 

+src.val[0] → Vt.2S 

+0 << lane << 1

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x4_t vld4q_lane_f32 (float32_t const * ptr, float32x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4S 

+src.val[2] → Vt3.4S 

+src.val[1] → Vt2.4S 

+src.val[0] → Vt.4S 

+0 << lane << 3

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x4_t vld4_lane_p16 (poly16_t const * ptr, poly16x4x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.4H 

+src.val[2] → Vt3.4H 

+src.val[1] → Vt2.4H 

+src.val[0] → Vt.4H 

+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x4_t vld4q_lane_p16 (poly16_t const * ptr, poly16x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8H 

+src.val[2] → Vt3.8H 

+src.val[1] → Vt2.8H 

+src.val[0] → Vt.8H 

+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x8x4_t vld4_lane_s8 (int8_t const * ptr, int8x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8B 

+src.val[2] → Vt3.8B 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x4_t vld4_lane_u8 (uint8_t const * ptr, uint8x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8B 

+src.val[2] → Vt3.8B 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x4_t vld4_lane_p8 (poly8_t const * ptr, poly8x8x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.8B 

+src.val[2] → Vt3.8B 

+src.val[1] → Vt2.8B 

+src.val[0] → Vt.8B 

+0 << lane << 7

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x4_t vld4q_lane_s8 (int8_t const * ptr, int8x16x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.16B 

+src.val[2] → Vt3.16B 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint8x16x4_t vld4q_lane_u8 (uint8_t const * ptr, uint8x16x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.16B 

+src.val[2] → Vt3.16B 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly8x16x4_t vld4q_lane_p8 (poly8_t const * ptr, poly8x16x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.16B 

+src.val[2] → Vt3.16B 

+src.val[1] → Vt2.16B 

+src.val[0] → Vt.16B 

+0 << lane << 15

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int64x1x4_t vld4_lane_s64 (int64_t const * ptr, int64x1x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.1D 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int64x2x4_t vld4q_lane_s64 (int64_t const * ptr, int64x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2D 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x1x4_t vld4_lane_u64 (uint64_t const * ptr, uint64x1x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.1D 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

uint64x2x4_t vld4q_lane_u64 (uint64_t const * ptr, uint64x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2D 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x1x4_t vld4_lane_p64 (poly64_t const * ptr, poly64x1x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.1D 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

poly64x2x4_t vld4q_lane_p64 (poly64_t const * ptr, poly64x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2D 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x1x4_t vld4_lane_f64 (float64_t const * ptr, float64x1x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.1D 

+src.val[2] → Vt3.1D 

+src.val[1] → Vt2.1D 

+src.val[0] → Vt.1D 

+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x4_t vld4q_lane_f64 (float64_t const * ptr, float64x2x4_t src, const int lane)Load single 4-element structure to one lane of four registers

Description

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+src.val[3] → Vt4.2D 

+src.val[2] → Vt3.2D 

+src.val[1] → Vt2.2D 

+src.val[0] → Vt.2D 

+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_lane_s8 (int8_t * ptr, int8x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_u8 (uint8_t * ptr, uint8x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_p8 (poly8_t * ptr, poly8x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_s8 (int8_t * ptr, int8x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_u8 (uint8_t * ptr, uint8x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_p8 (poly8_t * ptr, poly8x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_s8 (int8_t * ptr, int8x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_u8 (uint8_t * ptr, uint8x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_p8 (poly8_t * ptr, poly8x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_s16 (int16_t * ptr, int16x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_s16 (int16_t * ptr, int16x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_s32 (int32_t * ptr, int32x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_s32 (int32_t * ptr, int32x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_u16 (uint16_t * ptr, uint16x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_u16 (uint16_t * ptr, uint16x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_u32 (uint32_t * ptr, uint32x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_u32 (uint32_t * ptr, uint32x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_f16 (float16_t * ptr, float16x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_f16 (float16_t * ptr, float16x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_f32 (float32_t * ptr, float32x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_f32 (float32_t * ptr, float32x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2_lane_p16 (poly16_t * ptr, poly16x4x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_p16 (poly16_t * ptr, poly16x8x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst2q_lane_s8 (int8_t * ptr, int8x16x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_lane_u8 (uint8_t * ptr, uint8x16x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_lane_p8 (poly8_t * ptr, poly8x16x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_lane_s64 (int64_t * ptr, int64x1x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_lane_s64 (int64_t * ptr, int64x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_lane_u64 (uint64_t * ptr, uint64x1x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_lane_u64 (uint64_t * ptr, uint64x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_lane_p64 (poly64_t * ptr, poly64x1x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_lane_p64 (poly64_t * ptr, poly64x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2_lane_f64 (float64_t * ptr, float64x1x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst2q_lane_f64 (float64_t * ptr, float64x2x2_t val, const int lane)Store single 2-element structure from one lane of two registers

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 2

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3_lane_s16 (int16_t * ptr, int16x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_s16 (int16_t * ptr, int16x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_s32 (int32_t * ptr, int32x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_s32 (int32_t * ptr, int32x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_u16 (uint16_t * ptr, uint16x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_u16 (uint16_t * ptr, uint16x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_u32 (uint32_t * ptr, uint32x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_u32 (uint32_t * ptr, uint32x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_f16 (float16_t * ptr, float16x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_f16 (float16_t * ptr, float16x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_f32 (float32_t * ptr, float32x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_f32 (float32_t * ptr, float32x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_p16 (poly16_t * ptr, poly16x4x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_p16 (poly16_t * ptr, poly16x8x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_s8 (int8_t * ptr, int8x16x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_u8 (uint8_t * ptr, uint8x16x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3q_lane_p8 (poly8_t * ptr, poly8x16x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst3_lane_s64 (int64_t * ptr, int64x1x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_lane_s64 (int64_t * ptr, int64x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3_lane_u64 (uint64_t * ptr, uint64x1x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_lane_u64 (uint64_t * ptr, uint64x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3_lane_p64 (poly64_t * ptr, poly64x1x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_lane_p64 (poly64_t * ptr, poly64x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3_lane_f64 (float64_t * ptr, float64x1x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst3q_lane_f64 (float64_t * ptr, float64x2x3_t val, const int lane)Store single 3-element structure from one lane of three registers

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_lane_s16 (int16_t * ptr, int16x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_s16 (int16_t * ptr, int16x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_s32 (int32_t * ptr, int32x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_s32 (int32_t * ptr, int32x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_u16 (uint16_t * ptr, uint16x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_u16 (uint16_t * ptr, uint16x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_u32 (uint32_t * ptr, uint32x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_u32 (uint32_t * ptr, uint32x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_f16 (float16_t * ptr, float16x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_f16 (float16_t * ptr, float16x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_f32 (float32_t * ptr, float32x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_f32 (float32_t * ptr, float32x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4_lane_p16 (poly16_t * ptr, poly16x4x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H 

+0 << lane << 3

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_p16 (poly16_t * ptr, poly16x8x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H 

+0 << lane << 7

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst4q_lane_s8 (int8_t * ptr, int8x16x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_lane_u8 (uint8_t * ptr, uint8x16x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_lane_p8 (poly8_t * ptr, poly8x16x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B 

+0 << lane << 15

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_lane_s64 (int64_t * ptr, int64x1x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_lane_s64 (int64_t * ptr, int64x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_lane_u64 (uint64_t * ptr, uint64x1x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_lane_u64 (uint64_t * ptr, uint64x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_lane_p64 (poly64_t * ptr, poly64x1x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_lane_p64 (poly64_t * ptr, poly64x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4_lane_f64 (float64_t * ptr, float64x1x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D 

+0 << lane << 0

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst4q_lane_f64 (float64_t * ptr, float64x2x4_t val, const int lane)Store single 4-element structure from one lane of four registers

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D 

+0 << lane << 1

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1_s8_x2 (int8_t * ptr, int8x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s8_x2 (int8_t * ptr, int8x16x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s16_x2 (int16_t * ptr, int16x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s16_x2 (int16_t * ptr, int16x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s32_x2 (int32_t * ptr, int32x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s32_x2 (int32_t * ptr, int32x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u8_x2 (uint8_t * ptr, uint8x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u8_x2 (uint8_t * ptr, uint8x16x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u16_x2 (uint16_t * ptr, uint16x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u16_x2 (uint16_t * ptr, uint16x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u32_x2 (uint32_t * ptr, uint32x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u32_x2 (uint32_t * ptr, uint32x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f16_x2 (float16_t * ptr, float16x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f32_x2 (float32_t * ptr, float32x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f32_x2 (float32_t * ptr, float32x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p8_x2 (poly8_t * ptr, poly8x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p8_x2 (poly8_t * ptr, poly8x16x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p16_x2 (poly16_t * ptr, poly16x4x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s64_x2 (int64_t * ptr, int64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u64_x2 (uint64_t * ptr, uint64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p64_x2 (poly64_t * ptr, poly64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1q_s64_x2 (int64_t * ptr, int64x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u64_x2 (uint64_t * ptr, uint64x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1_f64_x2 (float64_t * ptr, float64x1x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1q_f64_x2 (float64_t * ptr, float64x2x2_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1_s8_x3 (int8_t * ptr, int8x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s8_x3 (int8_t * ptr, int8x16x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s16_x3 (int16_t * ptr, int16x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s16_x3 (int16_t * ptr, int16x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s32_x3 (int32_t * ptr, int32x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s32_x3 (int32_t * ptr, int32x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u8_x3 (uint8_t * ptr, uint8x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u8_x3 (uint8_t * ptr, uint8x16x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u16_x3 (uint16_t * ptr, uint16x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u16_x3 (uint16_t * ptr, uint16x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u32_x3 (uint32_t * ptr, uint32x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u32_x3 (uint32_t * ptr, uint32x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f16_x3 (float16_t * ptr, float16x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f32_x3 (float32_t * ptr, float32x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f32_x3 (float32_t * ptr, float32x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p8_x3 (poly8_t * ptr, poly8x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p8_x3 (poly8_t * ptr, poly8x16x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p16_x3 (poly16_t * ptr, poly16x4x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s64_x3 (int64_t * ptr, int64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u64_x3 (uint64_t * ptr, uint64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p64_x3 (poly64_t * ptr, poly64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1q_s64_x3 (int64_t * ptr, int64x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u64_x3 (uint64_t * ptr, uint64x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f64_x3 (float64_t * ptr, float64x1x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1q_f64_x3 (float64_t * ptr, float64x2x3_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1_s8_x4 (int8_t * ptr, int8x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s8_x4 (int8_t * ptr, int8x16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s16_x4 (int16_t * ptr, int16x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s16_x4 (int16_t * ptr, int16x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s32_x4 (int32_t * ptr, int32x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_s32_x4 (int32_t * ptr, int32x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u8_x4 (uint8_t * ptr, uint8x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u8_x4 (uint8_t * ptr, uint8x16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u16_x4 (uint16_t * ptr, uint16x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u16_x4 (uint16_t * ptr, uint16x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u32_x4 (uint32_t * ptr, uint32x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u32_x4 (uint32_t * ptr, uint32x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f16_x4 (float16_t * ptr, float16x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f16_x4 (float16_t * ptr, float16x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_f32_x4 (float32_t * ptr, float32x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2S 

+val.val[2] → Vt3.2S 

+val.val[1] → Vt2.2S 

+val.val[0] → Vt.2S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_f32_x4 (float32_t * ptr, float32x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4S 

+val.val[2] → Vt3.4S 

+val.val[1] → Vt2.4S 

+val.val[0] → Vt.4S

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p8_x4 (poly8_t * ptr, poly8x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8B 

+val.val[2] → Vt3.8B 

+val.val[1] → Vt2.8B 

+val.val[0] → Vt.8B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p8_x4 (poly8_t * ptr, poly8x16x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.16B 

+val.val[2] → Vt3.16B 

+val.val[1] → Vt2.16B 

+val.val[0] → Vt.16B

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p16_x4 (poly16_t * ptr, poly16x4x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.4H 

+val.val[2] → Vt3.4H 

+val.val[1] → Vt2.4H 

+val.val[0] → Vt.4H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p16_x4 (poly16_t * ptr, poly16x8x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.8H 

+val.val[2] → Vt3.8H 

+val.val[1] → Vt2.8H 

+val.val[0] → Vt.8H

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_s64_x4 (int64_t * ptr, int64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_u64_x4 (uint64_t * ptr, uint64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1_p64_x4 (poly64_t * ptr, poly64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1q_s64_x4 (int64_t * ptr, int64x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_u64_x4 (uint64_t * ptr, uint64x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

void vst1q_p64_x4 (poly64_t * ptr, poly64x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

void vst1_f64_x4 (float64_t * ptr, float64x1x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.1D 

+val.val[2] → Vt3.1D 

+val.val[1] → Vt2.1D 

+val.val[0] → Vt.1D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

void vst1q_f64_x4 (float64_t * ptr, float64x2x4_t val)Store a single-element structure from one lane of one register

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

+val.val[3] → Vt4.2D 

+val.val[2] → Vt3.2D 

+val.val[1] → Vt2.2D 

+val.val[0] → Vt.2D

Results

void → result
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x2_t vld1_s8_x2 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x2_t vld1q_s8_x2 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x2_t vld1_s16_x2 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x2_t vld1q_s16_x2 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x2_t vld1_s32_x2 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x2_t vld1q_s32_x2 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x2_t vld1_u8_x2 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x2_t vld1q_u8_x2 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x2_t vld1_u16_x2 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x2_t vld1q_u16_x2 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x2_t vld1_u32_x2 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x2_t vld1q_u32_x2 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x2_t vld1_f16_x2 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x2_t vld1q_f16_x2 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x2_t vld1_f32_x2 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x2_t vld1q_f32_x2 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x2_t vld1_p8_x2 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x2_t vld1q_p8_x2 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x2_t vld1_p16_x2 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x2_t vld1q_p16_x2 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x2_t vld1_s64_x2 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x2_t vld1_u64_x2 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x2_t vld1_p64_x2 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x2_t vld1q_s64_x2 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x2x2_t vld1q_u64_x2 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x2x2_t vld1q_p64_x2 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

float64x1x2_t vld1_f64_x2 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x2_t vld1q_f64_x2 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x3_t vld1_s8_x3 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x3_t vld1q_s8_x3 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x3_t vld1_s16_x3 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x3_t vld1q_s16_x3 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x3_t vld1_s32_x3 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x3_t vld1q_s32_x3 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x3_t vld1_u8_x3 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x3_t vld1q_u8_x3 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x3_t vld1_u16_x3 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x3_t vld1q_u16_x3 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x3_t vld1_u32_x3 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x3_t vld1q_u32_x3 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x3_t vld1_f16_x3 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x3_t vld1q_f16_x3 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x3_t vld1_f32_x3 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x3_t vld1q_f32_x3 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x3_t vld1_p8_x3 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x3_t vld1q_p8_x3 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x3_t vld1_p16_x3 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x3_t vld1q_p16_x3 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x3_t vld1_s64_x3 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x3_t vld1_u64_x3 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x3_t vld1_p64_x3 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x3_t vld1q_s64_x3 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x2x3_t vld1q_u64_x3 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x2x3_t vld1q_p64_x3 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

float64x1x3_t vld1_f64_x3 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x3_t vld1q_f64_x3 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8x4_t vld1_s8_x4 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int8x16x4_t vld1q_s8_x4 (int8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x4x4_t vld1_s16_x4 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int16x8x4_t vld1q_s16_x4 (int16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x2x4_t vld1_s32_x4 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int32x4x4_t vld1q_s32_x4 (int32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x8x4_t vld1_u8_x4 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint8x16x4_t vld1q_u8_x4 (uint8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x4x4_t vld1_u16_x4 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint16x8x4_t vld1q_u16_x4 (uint16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x2x4_t vld1_u32_x4 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint32x4x4_t vld1q_u32_x4 (uint32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x4x4_t vld1_f16_x4 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float16x8x4_t vld1q_f16_x4 (float16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x2x4_t vld1_f32_x4 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

float32x4x4_t vld1q_f32_x4 (float32_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x8x4_t vld1_p8_x4 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly8x16x4_t vld1q_p8_x4 (poly8_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x4x4_t vld1_p16_x4 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly16x8x4_t vld1q_p16_x4 (poly16_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

int64x1x4_t vld1_s64_x4 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x1x4_t vld1_u64_x4 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x1x4_t vld1_p64_x4 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

int64x2x4_t vld1q_s64_x4 (int64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

uint64x2x4_t vld1q_u64_x4 (uint64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

v7/A32/A64

poly64x2x4_t vld1q_p64_x4 (poly64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A32/A64

float64x1x4_t vld1_f64_x4 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

float64x2x4_t vld1q_f64_x4 (float64_t const * ptr)Load one single-element structure to one lane of one register

Description

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;

Supported architectures

A64

int8x8_t vpadd_s8 (int8x8_t a, int8x8_t b)Add pairwise

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADDP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vpadd_s16 (int16x4_t a, int16x4_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vpadd_s32 (int32x2_t a, int32x2_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vpadd_u8 (uint8x8_t a, uint8x8_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vpadd_u16 (uint16x4_t a, uint16x4_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vpadd_u32 (uint32x2_t a, uint32x2_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vpadd_f32 (float32x2_t a, float32x2_t b)Floating-point add pairwise

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FADDP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vpaddq_s8 (int8x16_t a, int8x16_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vpaddq_s16 (int16x8_t a, int16x8_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vpaddq_s32 (int32x4_t a, int32x4_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

int64x2_t vpaddq_s64 (int64x2_t a, int64x2_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vpaddq_u8 (uint8x16_t a, uint8x16_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vpaddq_u16 (uint16x8_t a, uint16x8_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vpaddq_u32 (uint32x4_t a, uint32x4_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vpaddq_u64 (uint64x2_t a, uint64x2_t b)Add pairwise

Description

A64 Instruction

ADDP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

float32x4_t vpaddq_f32 (float32x4_t a, float32x4_t b)Floating-point add pairwise

Description

A64 Instruction

FADDP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vpaddq_f64 (float64x2_t a, float64x2_t b)Floating-point add pairwise

Description

A64 Instruction

FADDP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int16x4_t vpaddl_s8 (int8x8_t a)Signed add long pairwise

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

SADDLP Vd.4H,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vpaddlq_s8 (int8x16_t a)Signed add long pairwise

Description

A64 Instruction

SADDLP Vd.8H,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vpaddl_s16 (int16x4_t a)Signed add long pairwise

Description

A64 Instruction

SADDLP Vd.2S,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vpaddlq_s16 (int16x8_t a)Signed add long pairwise

Description

A64 Instruction

SADDLP Vd.4S,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vpaddl_s32 (int32x2_t a)Signed add long pairwise

Description

A64 Instruction

SADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vpaddlq_s32 (int32x4_t a)Signed add long pairwise

Description

A64 Instruction

SADDLP Vd.2D,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vpaddl_u8 (uint8x8_t a)Unsigned add long pairwise

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

UADDLP Vd.4H,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vpaddlq_u8 (uint8x16_t a)Unsigned add long pairwise

Description

A64 Instruction

UADDLP Vd.8H,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vpaddl_u16 (uint16x4_t a)Unsigned add long pairwise

Description

A64 Instruction

UADDLP Vd.2S,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vpaddlq_u16 (uint16x8_t a)Unsigned add long pairwise

Description

A64 Instruction

UADDLP Vd.4S,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vpaddl_u32 (uint32x2_t a)Unsigned add long pairwise

Description

A64 Instruction

UADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vpaddlq_u32 (uint32x4_t a)Unsigned add long pairwise

Description

A64 Instruction

UADDLP Vd.2D,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vpadal_s8 (int16x4_t a, int8x8_t b)Signed add and accumulate long pairwise

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

SADALP Vd.4H,Vn.8B
+

Argument Preparation

a → Vd.4H 

+b → Vn.8B

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vpadalq_s8 (int16x8_t a, int8x16_t b)Signed add and accumulate long pairwise

Description

A64 Instruction

SADALP Vd.8H,Vn.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vpadal_s16 (int32x2_t a, int16x4_t b)Signed add and accumulate long pairwise

Description

A64 Instruction

SADALP Vd.2S,Vn.4H
+

Argument Preparation

a → Vd.2S 

+b → Vn.4H

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vpadalq_s16 (int32x4_t a, int16x8_t b)Signed add and accumulate long pairwise

Description

A64 Instruction

SADALP Vd.4S,Vn.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vpadal_s32 (int64x1_t a, int32x2_t b)Signed add and accumulate long pairwise

Description

A64 Instruction

SADALP Vd.1D,Vn.2S
+

Argument Preparation

a → Vd.1D 

+b → Vn.2S

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vpadalq_s32 (int64x2_t a, int32x4_t b)Signed add and accumulate long pairwise

Description

A64 Instruction

SADALP Vd.2D,Vn.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vpadal_u8 (uint16x4_t a, uint8x8_t b)Unsigned add and accumulate long pairwise

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

A64 Instruction

UADALP Vd.4H,Vn.8B
+

Argument Preparation

a → Vd.4H 

+b → Vn.8B

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vpadalq_u8 (uint16x8_t a, uint8x16_t b)Unsigned add and accumulate long pairwise

Description

A64 Instruction

UADALP Vd.8H,Vn.16B
+

Argument Preparation

a → Vd.8H 

+b → Vn.16B

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vpadal_u16 (uint32x2_t a, uint16x4_t b)Unsigned add and accumulate long pairwise

Description

A64 Instruction

UADALP Vd.2S,Vn.4H
+

Argument Preparation

a → Vd.2S 

+b → Vn.4H

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vpadalq_u16 (uint32x4_t a, uint16x8_t b)Unsigned add and accumulate long pairwise

Description

A64 Instruction

UADALP Vd.4S,Vn.8H
+

Argument Preparation

a → Vd.4S 

+b → Vn.8H

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vpadal_u32 (uint64x1_t a, uint32x2_t b)Unsigned add and accumulate long pairwise

Description

A64 Instruction

UADALP Vd.1D,Vn.2S
+

Argument Preparation

a → Vd.1D 

+b → Vn.2S

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vpadalq_u32 (uint64x2_t a, uint32x4_t b)Unsigned add and accumulate long pairwise

Description

A64 Instruction

UADALP Vd.2D,Vn.4S
+

Argument Preparation

a → Vd.2D 

+b → Vn.4S

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vpmax_s8 (int8x8_t a, int8x8_t b)Signed maximum pairwise

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SMAXP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vpmax_s16 (int16x4_t a, int16x4_t b)Signed maximum pairwise

Description

A64 Instruction

SMAXP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vpmax_s32 (int32x2_t a, int32x2_t b)Signed maximum pairwise

Description

A64 Instruction

SMAXP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vpmax_u8 (uint8x8_t a, uint8x8_t b)Unsigned maximum pairwise

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UMAXP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vpmax_u16 (uint16x4_t a, uint16x4_t b)Unsigned maximum pairwise

Description

A64 Instruction

UMAXP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vpmax_u32 (uint32x2_t a, uint32x2_t b)Unsigned maximum pairwise

Description

A64 Instruction

UMAXP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vpmax_f32 (float32x2_t a, float32x2_t b)Floating-point maximum pairwise

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMAXP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vpmaxq_s8 (int8x16_t a, int8x16_t b)Signed maximum pairwise

Description

A64 Instruction

SMAXP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vpmaxq_s16 (int16x8_t a, int16x8_t b)Signed maximum pairwise

Description

A64 Instruction

SMAXP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vpmaxq_s32 (int32x4_t a, int32x4_t b)Signed maximum pairwise

Description

A64 Instruction

SMAXP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vpmaxq_u8 (uint8x16_t a, uint8x16_t b)Unsigned maximum pairwise

Description

A64 Instruction

UMAXP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vpmaxq_u16 (uint16x8_t a, uint16x8_t b)Unsigned maximum pairwise

Description

A64 Instruction

UMAXP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vpmaxq_u32 (uint32x4_t a, uint32x4_t b)Unsigned maximum pairwise

Description

A64 Instruction

UMAXP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

float32x4_t vpmaxq_f32 (float32x4_t a, float32x4_t b)Floating-point maximum pairwise

Description

A64 Instruction

FMAXP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vpmaxq_f64 (float64x2_t a, float64x2_t b)Floating-point maximum pairwise

Description

A64 Instruction

FMAXP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vpmin_s8 (int8x8_t a, int8x8_t b)Signed minimum pairwise

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SMINP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vpmin_s16 (int16x4_t a, int16x4_t b)Signed minimum pairwise

Description

A64 Instruction

SMINP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vpmin_s32 (int32x2_t a, int32x2_t b)Signed minimum pairwise

Description

A64 Instruction

SMINP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vpmin_u8 (uint8x8_t a, uint8x8_t b)Unsigned minimum pairwise

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UMINP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vpmin_u16 (uint16x4_t a, uint16x4_t b)Unsigned minimum pairwise

Description

A64 Instruction

UMINP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vpmin_u32 (uint32x2_t a, uint32x2_t b)Unsigned minimum pairwise

Description

A64 Instruction

UMINP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vpmin_f32 (float32x2_t a, float32x2_t b)Floating-point minimum pairwise

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMINP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vpminq_s8 (int8x16_t a, int8x16_t b)Signed minimum pairwise

Description

A64 Instruction

SMINP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int16x8_t vpminq_s16 (int16x8_t a, int16x8_t b)Signed minimum pairwise

Description

A64 Instruction

SMINP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32x4_t vpminq_s32 (int32x4_t a, int32x4_t b)Signed minimum pairwise

Description

A64 Instruction

SMINP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vpminq_u8 (uint8x16_t a, uint8x16_t b)Unsigned minimum pairwise

Description

A64 Instruction

UMINP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vpminq_u16 (uint16x8_t a, uint16x8_t b)Unsigned minimum pairwise

Description

A64 Instruction

UMINP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vpminq_u32 (uint32x4_t a, uint32x4_t b)Unsigned minimum pairwise

Description

A64 Instruction

UMINP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

float32x4_t vpminq_f32 (float32x4_t a, float32x4_t b)Floating-point minimum pairwise

Description

A64 Instruction

FMINP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vpminq_f64 (float64x2_t a, float64x2_t b)Floating-point minimum pairwise

Description

A64 Instruction

FMINP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vpmaxnm_f32 (float32x2_t a, float32x2_t b)Floating-point maximum number pairwise

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMAXNMP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vpmaxnmq_f32 (float32x4_t a, float32x4_t b)Floating-point maximum number pairwise

Description

A64 Instruction

FMAXNMP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vpmaxnmq_f64 (float64x2_t a, float64x2_t b)Floating-point maximum number pairwise

Description

A64 Instruction

FMAXNMP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vpminnm_f32 (float32x2_t a, float32x2_t b)Floating-point minimum number pairwise

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMINNMP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vpminnmq_f32 (float32x4_t a, float32x4_t b)Floating-point minimum number pairwise

Description

A64 Instruction

FMINNMP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vpminnmq_f64 (float64x2_t a, float64x2_t b)Floating-point minimum number pairwise

Description

A64 Instruction

FMINNMP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int64_t vpaddd_s64 (int64x2_t a)Add pairwise

Description

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint64_t vpaddd_u64 (uint64x2_t a)Add pairwise

Description

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

float32_t vpadds_f32 (float32x2_t a)Floating-point add pairwise

Description

A64 Instruction

FADDP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vpaddd_f64 (float64x2_t a)Floating-point add pairwise

Description

A64 Instruction

FADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vpmaxs_f32 (float32x2_t a)Floating-point maximum pairwise

Description

A64 Instruction

FMAXP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vpmaxqd_f64 (float64x2_t a)Floating-point maximum pairwise

Description

A64 Instruction

FMAXP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vpmins_f32 (float32x2_t a)Floating-point minimum pairwise

Description

A64 Instruction

FMINP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vpminqd_f64 (float64x2_t a)Floating-point minimum pairwise

Description

A64 Instruction

FMINP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vpmaxnms_f32 (float32x2_t a)Floating-point maximum number pairwise

Description

A64 Instruction

FMAXNMP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vpmaxnmqd_f64 (float64x2_t a)Floating-point maximum number pairwise

Description

A64 Instruction

FMAXNMP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vpminnms_f32 (float32x2_t a)Floating-point minimum number pairwise

Description

A64 Instruction

FMINNMP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vpminnmqd_f64 (float64x2_t a)Floating-point minimum number pairwise

Description

A64 Instruction

FMINNMP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8_t vaddv_s8 (int8x8_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

int8_t vaddvq_s8 (int8x16_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

int16_t vaddv_s16 (int16x4_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

int16_t vaddvq_s16 (int16x8_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

int32_t vaddv_s32 (int32x2_t a)Add pairwise

Description

A64 Instruction

ADDP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

int32_t vaddvq_s32 (int32x4_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

int64_t vaddvq_s64 (int64x2_t a)Add pairwise

Description

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint8_t vaddv_u8 (uint8x8_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

uint8_t vaddvq_u8 (uint8x16_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

uint16_t vaddv_u16 (uint16x4_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

uint16_t vaddvq_u16 (uint16x8_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

uint32_t vaddv_u32 (uint32x2_t a)Add pairwise

Description

A64 Instruction

ADDP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

uint32_t vaddvq_u32 (uint32x4_t a)Add across vector

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

A64 Instruction

ADDV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);

Supported architectures

A64

uint64_t vaddvq_u64 (uint64x2_t a)Add pairwise

Description

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;

Supported architectures

A64

float32_t vaddv_f32 (float32x2_t a)Floating-point add pairwise

Description

A64 Instruction

FADDP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vaddvq_f32 (float32x4_t a)Floating-point add pairwise

Description

A64 Instruction

FADDP Vt.4S,Vn.4S,Vm.4S
+FADDP Sd,Vt.2S
+

Argument Preparation

a → Vn.4S 

+a → Vm.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vaddvq_f64 (float64x2_t a)Floating-point add pairwise

Description

A64 Instruction

FADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int16_t vaddlv_s8 (int8x8_t a)Signed add long across vector

Description

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.

A64 Instruction

SADDLV Hd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

int16_t vaddlvq_s8 (int8x16_t a)Signed add long across vector

Description

A64 Instruction

SADDLV Hd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

int32_t vaddlv_s16 (int16x4_t a)Signed add long across vector

Description

A64 Instruction

SADDLV Sd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

int32_t vaddlvq_s16 (int16x8_t a)Signed add long across vector

Description

A64 Instruction

SADDLV Sd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

int64_t vaddlv_s32 (int32x2_t a)Signed add long pairwise

Description

A64 Instruction

SADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

A64

int64_t vaddlvq_s32 (int32x4_t a)Signed add long across vector

Description

A64 Instruction

SADDLV Dd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

uint16_t vaddlv_u8 (uint8x8_t a)Unsigned sum long across vector

Description

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

A64 Instruction

UADDLV Hd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

uint16_t vaddlvq_u8 (uint8x16_t a)Unsigned sum long across vector

Description

A64 Instruction

UADDLV Hd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

uint32_t vaddlv_u16 (uint16x4_t a)Unsigned sum long across vector

Description

A64 Instruction

UADDLV Sd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

uint32_t vaddlvq_u16 (uint16x8_t a)Unsigned sum long across vector

Description

A64 Instruction

UADDLV Sd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

uint64_t vaddlv_u32 (uint32x2_t a)Unsigned add long pairwise

Description

A64 Instruction

UADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;

Supported architectures

A64

uint64_t vaddlvq_u32 (uint32x4_t a)Unsigned sum long across vector

Description

A64 Instruction

UADDLV Dd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;

Supported architectures

A64

int8_t vmaxv_s8 (int8x8_t a)Signed maximum across vector

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

A64 Instruction

SMAXV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int8_t vmaxvq_s8 (int8x16_t a)Signed maximum across vector

Description

A64 Instruction

SMAXV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int16_t vmaxv_s16 (int16x4_t a)Signed maximum across vector

Description

A64 Instruction

SMAXV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int16_t vmaxvq_s16 (int16x8_t a)Signed maximum across vector

Description

A64 Instruction

SMAXV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int32_t vmaxv_s32 (int32x2_t a)Signed maximum pairwise

Description

A64 Instruction

SMAXP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32_t vmaxvq_s32 (int32x4_t a)Signed maximum across vector

Description

A64 Instruction

SMAXV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint8_t vmaxv_u8 (uint8x8_t a)Unsigned maximum across vector

Description

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

A64 Instruction

UMAXV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint8_t vmaxvq_u8 (uint8x16_t a)Unsigned maximum across vector

Description

A64 Instruction

UMAXV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint16_t vmaxv_u16 (uint16x4_t a)Unsigned maximum across vector

Description

A64 Instruction

UMAXV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint16_t vmaxvq_u16 (uint16x8_t a)Unsigned maximum across vector

Description

A64 Instruction

UMAXV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint32_t vmaxv_u32 (uint32x2_t a)Unsigned maximum pairwise

Description

A64 Instruction

UMAXP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32_t vmaxvq_u32 (uint32x4_t a)Unsigned maximum across vector

Description

A64 Instruction

UMAXV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

float32_t vmaxv_f32 (float32x2_t a)Floating-point maximum pairwise

Description

A64 Instruction

FMAXP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmaxvq_f32 (float32x4_t a)Floating-point maximum across vector

Description

Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMAXV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMAX, operand, esize);

Supported architectures

A64

float64_t vmaxvq_f64 (float64x2_t a)Floating-point maximum pairwise

Description

A64 Instruction

FMAXP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8_t vminv_s8 (int8x8_t a)Signed minimum across vector

Description

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

A64 Instruction

SMINV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int8_t vminvq_s8 (int8x16_t a)Signed minimum across vector

Description

A64 Instruction

SMINV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int16_t vminv_s16 (int16x4_t a)Signed minimum across vector

Description

A64 Instruction

SMINV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int16_t vminvq_s16 (int16x8_t a)Signed minimum across vector

Description

A64 Instruction

SMINV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

int32_t vminv_s32 (int32x2_t a)Signed minimum pairwise

Description

A64 Instruction

SMINP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

int32_t vminvq_s32 (int32x4_t a)Signed minimum across vector

Description

A64 Instruction

SMINV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint8_t vminv_u8 (uint8x8_t a)Unsigned minimum across vector

Description

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

A64 Instruction

UMINV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint8_t vminvq_u8 (uint8x16_t a)Unsigned minimum across vector

Description

A64 Instruction

UMINV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B

Results

Bd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint16_t vminv_u16 (uint16x4_t a)Unsigned minimum across vector

Description

A64 Instruction

UMINV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint16_t vminvq_u16 (uint16x8_t a)Unsigned minimum across vector

Description

A64 Instruction

UMINV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

uint32_t vminv_u32 (uint32x2_t a)Unsigned minimum pairwise

Description

A64 Instruction

UMINP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;

Supported architectures

A64

uint32_t vminvq_u32 (uint32x4_t a)Unsigned minimum across vector

Description

A64 Instruction

UMINV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;

Supported architectures

A64

float32_t vminv_f32 (float32x2_t a)Floating-point minimum pairwise

Description

A64 Instruction

FMINP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vminvq_f32 (float32x4_t a)Floating-point minimum across vector

Description

Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMINV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMIN, operand, esize);

Supported architectures

A64

float64_t vminvq_f64 (float64x2_t a)Floating-point minimum pairwise

Description

A64 Instruction

FMINP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmaxnmv_f32 (float32x2_t a)Floating-point maximum number pairwise

Description

A64 Instruction

FMAXNMP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vmaxnmvq_f32 (float32x4_t a)Floating-point maximum number across vector

Description

Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMAXNMV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMAXNUM, operand, esize);

Supported architectures

A64

float64_t vmaxnmvq_f64 (float64x2_t a)Floating-point maximum number pairwise

Description

A64 Instruction

FMAXNMP  Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vminnmv_f32 (float32x2_t a)Floating-point minimum number pairwise

Description

A64 Instruction

FMINNMP  Sd,Vn.2S
+

Argument Preparation

a → Vn.2S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32_t vminnmvq_f32 (float32x4_t a)Floating-point minimum number across vector

Description

Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FMINNMV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMINNUM, operand, esize);

Supported architectures

A64

float64_t vminnmvq_f64 (float64x2_t a)Floating-point minimum number pairwise

Description

A64 Instruction

FMINNMP  Dd,Vn.2D
+

Argument Preparation

a → Vn.2D

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8x8_t vext_s8 (int8x8_t a, int8x8_t b, const int n)Extract vector from pair of vectors

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#n
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int8x16_t vextq_s8 (int8x16_t a, int8x16_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#n
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int16x4_t vext_s16 (int16x4_t a, int16x4_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 3

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int16x8_t vextq_s16 (int16x8_t a, int16x8_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int32x2_t vext_s32 (int32x2_t a, int32x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 1

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int32x4_t vextq_s32 (int32x4_t a, int32x4_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 3

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int64x1_t vext_s64 (int64x1_t a, int64x1_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 0

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int64x2_t vextq_s64 (int64x2_t a, int64x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 1

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint8x8_t vext_u8 (uint8x8_t a, uint8x8_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#n
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint8x16_t vextq_u8 (uint8x16_t a, uint8x16_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#n
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint16x4_t vext_u16 (uint16x4_t a, uint16x4_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 3

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint16x8_t vextq_u16 (uint16x8_t a, uint16x8_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint32x2_t vext_u32 (uint32x2_t a, uint32x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 1

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint32x4_t vextq_u32 (uint32x4_t a, uint32x4_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 3

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint64x1_t vext_u64 (uint64x1_t a, uint64x1_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 0

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

uint64x2_t vextq_u64 (uint64x2_t a, uint64x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 1

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

poly64x1_t vext_p64 (poly64x1_t a, poly64x1_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 0

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

A32/A64

poly64x2_t vextq_p64 (poly64x2_t a, poly64x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 1

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

A32/A64

float32x2_t vext_f32 (float32x2_t a, float32x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 1

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

float32x4_t vextq_f32 (float32x4_t a, float32x4_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 3

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

float64x1_t vext_f64 (float64x1_t a, float64x1_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 0

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

A64

float64x2_t vextq_f64 (float64x2_t a, float64x2_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 1

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

A64

poly8x8_t vext_p8 (poly8x8_t a, poly8x8_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#n
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

poly8x16_t vextq_p8 (poly8x16_t a, poly8x16_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#n
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

poly16x4_t vext_p16 (poly16x4_t a, poly16x4_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B 

+0 << n << 3

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

poly16x8_t vextq_p16 (poly16x8_t a, poly16x8_t b, const int n)Extract vector from pair of vectors

Description

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B 

+0 << n << 7

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;

Supported architectures

v7/A32/A64

int8x8_t vrev64_s8 (int8x8_t vec)Reverse elements in 64-bit doublewords

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

REV64 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrev64q_s8 (int8x16_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrev64_s16 (int16x4_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrev64q_s16 (int16x8_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vrev64_s32 (int32x2_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.2S,Vn.2S
+

Argument Preparation

vec → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vrev64q_s32 (int32x4_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.4S,Vn.4S
+

Argument Preparation

vec → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrev64_u8 (uint8x8_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrev64q_u8 (uint8x16_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrev64_u16 (uint16x4_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrev64q_u16 (uint16x8_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrev64_u32 (uint32x2_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.2S,Vn.2S
+

Argument Preparation

vec → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrev64q_u32 (uint32x4_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.4S,Vn.4S
+

Argument Preparation

vec → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vrev64_f32 (float32x2_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.2S,Vn.2S
+

Argument Preparation

vec → Vn.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vrev64q_f32 (float32x4_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.4S,Vn.4S
+

Argument Preparation

vec → Vn.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vrev64_p8 (poly8x8_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vrev64q_p8 (poly8x16_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vrev64_p16 (poly16x4_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vrev64q_p16 (poly16x8_t vec)Reverse elements in 64-bit doublewords

Description

A64 Instruction

REV64 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vrev32_s8 (int8x8_t vec)Reverse elements in 32-bit words

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

REV32 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrev32q_s8 (int8x16_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrev32_s16 (int16x4_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrev32q_s16 (int16x8_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrev32_u8 (uint8x8_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrev32q_u8 (uint8x16_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrev32_u16 (uint16x4_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrev32q_u16 (uint16x8_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vrev32_p8 (poly8x8_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vrev32q_p8 (poly8x16_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vrev32_p16 (poly16x4_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vrev32q_p16 (poly16x8_t vec)Reverse elements in 32-bit words

Description

A64 Instruction

REV32 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vrev16_s8 (int8x8_t vec)Reverse elements in 16-bit halfwords

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

REV16 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrev16q_s8 (int8x16_t vec)Reverse elements in 16-bit halfwords

Description

A64 Instruction

REV16 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrev16_u8 (uint8x8_t vec)Reverse elements in 16-bit halfwords

Description

A64 Instruction

REV16 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrev16q_u8 (uint8x16_t vec)Reverse elements in 16-bit halfwords

Description

A64 Instruction

REV16 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vrev16_p8 (poly8x8_t vec)Reverse elements in 16-bit halfwords

Description

A64 Instruction

REV16 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vrev16q_p8 (poly8x16_t vec)Reverse elements in 16-bit halfwords

Description

A64 Instruction

REV16 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vzip1_s8 (int8x8_t a, int8x8_t b)Zip vectors

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

A64 Instruction

ZIP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vzip1q_s8 (int8x16_t a, int8x16_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int16x4_t vzip1_s16 (int16x4_t a, int16x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int16x8_t vzip1q_s16 (int16x8_t a, int16x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int32x2_t vzip1_s32 (int32x2_t a, int32x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int32x4_t vzip1q_s32 (int32x4_t a, int32x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int64x2_t vzip1q_s64 (int64x2_t a, int64x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vzip1_u8 (uint8x8_t a, uint8x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vzip1q_u8 (uint8x16_t a, uint8x16_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vzip1_u16 (uint16x4_t a, uint16x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vzip1q_u16 (uint16x8_t a, uint16x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vzip1_u32 (uint32x2_t a, uint32x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vzip1q_u32 (uint32x4_t a, uint32x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vzip1q_u64 (uint64x2_t a, uint64x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly64x2_t vzip1q_p64 (poly64x2_t a, poly64x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

float32x2_t vzip1_f32 (float32x2_t a, float32x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

float32x4_t vzip1q_f32 (float32x4_t a, float32x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

float64x2_t vzip1q_f64 (float64x2_t a, float64x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vzip1_p8 (poly8x8_t a, poly8x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vzip1q_p8 (poly8x16_t a, poly8x16_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x4_t vzip1_p16 (poly16x4_t a, poly16x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vzip1q_p16 (poly16x8_t a, poly16x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vzip2_s8 (int8x8_t a, int8x8_t b)Zip vectors

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

A64 Instruction

ZIP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vzip2q_s8 (int8x16_t a, int8x16_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int16x4_t vzip2_s16 (int16x4_t a, int16x4_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int16x8_t vzip2q_s16 (int16x8_t a, int16x8_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int32x2_t vzip2_s32 (int32x2_t a, int32x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int32x4_t vzip2q_s32 (int32x4_t a, int32x4_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int64x2_t vzip2q_s64 (int64x2_t a, int64x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vzip2_u8 (uint8x8_t a, uint8x8_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vzip2q_u8 (uint8x16_t a, uint8x16_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vzip2_u16 (uint16x4_t a, uint16x4_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vzip2q_u16 (uint16x8_t a, uint16x8_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vzip2_u32 (uint32x2_t a, uint32x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vzip2q_u32 (uint32x4_t a, uint32x4_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vzip2q_u64 (uint64x2_t a, uint64x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly64x2_t vzip2q_p64 (poly64x2_t a, poly64x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

float32x2_t vzip2_f32 (float32x2_t a, float32x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

float32x4_t vzip2q_f32 (float32x4_t a, float32x4_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

float64x2_t vzip2q_f64 (float64x2_t a, float64x2_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vzip2_p8 (poly8x8_t a, poly8x8_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vzip2q_p8 (poly8x16_t a, poly8x16_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x4_t vzip2_p16 (poly16x4_t a, poly16x4_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vzip2q_p16 (poly16x8_t a, poly16x8_t b)Zip vectors

Description

A64 Instruction

ZIP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vuzp1_s8 (int8x8_t a, int8x8_t b)Unzip vectors

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UZP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vuzp1q_s8 (int8x16_t a, int8x16_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x4_t vuzp1_s16 (int16x4_t a, int16x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x8_t vuzp1q_s16 (int16x8_t a, int16x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x2_t vuzp1_s32 (int32x2_t a, int32x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x4_t vuzp1q_s32 (int32x4_t a, int32x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int64x2_t vuzp1q_s64 (int64x2_t a, int64x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vuzp1_u8 (uint8x8_t a, uint8x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vuzp1q_u8 (uint8x16_t a, uint8x16_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vuzp1_u16 (uint16x4_t a, uint16x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vuzp1q_u16 (uint16x8_t a, uint16x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vuzp1_u32 (uint32x2_t a, uint32x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vuzp1q_u32 (uint32x4_t a, uint32x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vuzp1q_u64 (uint64x2_t a, uint64x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly64x2_t vuzp1q_p64 (poly64x2_t a, poly64x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x2_t vuzp1_f32 (float32x2_t a, float32x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x4_t vuzp1q_f32 (float32x4_t a, float32x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

float64x2_t vuzp1q_f64 (float64x2_t a, float64x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vuzp1_p8 (poly8x8_t a, poly8x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vuzp1q_p8 (poly8x16_t a, poly8x16_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x4_t vuzp1_p16 (poly16x4_t a, poly16x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vuzp1q_p16 (poly16x8_t a, poly16x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vuzp2_s8 (int8x8_t a, int8x8_t b)Unzip vectors

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UZP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vuzp2q_s8 (int8x16_t a, int8x16_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x4_t vuzp2_s16 (int16x4_t a, int16x4_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x8_t vuzp2q_s16 (int16x8_t a, int16x8_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x2_t vuzp2_s32 (int32x2_t a, int32x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x4_t vuzp2q_s32 (int32x4_t a, int32x4_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int64x2_t vuzp2q_s64 (int64x2_t a, int64x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vuzp2_u8 (uint8x8_t a, uint8x8_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vuzp2q_u8 (uint8x16_t a, uint8x16_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vuzp2_u16 (uint16x4_t a, uint16x4_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vuzp2q_u16 (uint16x8_t a, uint16x8_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vuzp2_u32 (uint32x2_t a, uint32x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vuzp2q_u32 (uint32x4_t a, uint32x4_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vuzp2q_u64 (uint64x2_t a, uint64x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly64x2_t vuzp2q_p64 (poly64x2_t a, poly64x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x2_t vuzp2_f32 (float32x2_t a, float32x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x4_t vuzp2q_f32 (float32x4_t a, float32x4_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

float64x2_t vuzp2q_f64 (float64x2_t a, float64x2_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vuzp2_p8 (poly8x8_t a, poly8x8_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vuzp2q_p8 (poly8x16_t a, poly8x16_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x4_t vuzp2_p16 (poly16x4_t a, poly16x4_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vuzp2q_p16 (poly16x8_t a, poly16x8_t b)Unzip vectors

Description

A64 Instruction

UZP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vtrn1_s8 (int8x8_t a, int8x8_t b)Transpose vectors

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

A64 Instruction

TRN1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vtrn1q_s8 (int8x16_t a, int8x16_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x4_t vtrn1_s16 (int16x4_t a, int16x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x8_t vtrn1q_s16 (int16x8_t a, int16x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x2_t vtrn1_s32 (int32x2_t a, int32x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x4_t vtrn1q_s32 (int32x4_t a, int32x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int64x2_t vtrn1q_s64 (int64x2_t a, int64x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vtrn1_u8 (uint8x8_t a, uint8x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vtrn1q_u8 (uint8x16_t a, uint8x16_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vtrn1_u16 (uint16x4_t a, uint16x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vtrn1q_u16 (uint16x8_t a, uint16x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vtrn1_u32 (uint32x2_t a, uint32x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vtrn1q_u32 (uint32x4_t a, uint32x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vtrn1q_u64 (uint64x2_t a, uint64x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly64x2_t vtrn1q_p64 (poly64x2_t a, poly64x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x2_t vtrn1_f32 (float32x2_t a, float32x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x4_t vtrn1q_f32 (float32x4_t a, float32x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

float64x2_t vtrn1q_f64 (float64x2_t a, float64x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vtrn1_p8 (poly8x8_t a, poly8x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vtrn1q_p8 (poly8x16_t a, poly8x16_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x4_t vtrn1_p16 (poly16x4_t a, poly16x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vtrn1q_p16 (poly16x8_t a, poly16x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vtrn2_s8 (int8x8_t a, int8x8_t b)Transpose vectors

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

A64 Instruction

TRN2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vtrn2q_s8 (int8x16_t a, int8x16_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x4_t vtrn2_s16 (int16x4_t a, int16x4_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int16x8_t vtrn2q_s16 (int16x8_t a, int16x8_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x2_t vtrn2_s32 (int32x2_t a, int32x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int32x4_t vtrn2q_s32 (int32x4_t a, int32x4_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int64x2_t vtrn2q_s64 (int64x2_t a, int64x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vtrn2_u8 (uint8x8_t a, uint8x8_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vtrn2q_u8 (uint8x16_t a, uint8x16_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x4_t vtrn2_u16 (uint16x4_t a, uint16x4_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint16x8_t vtrn2q_u16 (uint16x8_t a, uint16x8_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x2_t vtrn2_u32 (uint32x2_t a, uint32x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint32x4_t vtrn2q_u32 (uint32x4_t a, uint32x4_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

uint64x2_t vtrn2q_u64 (uint64x2_t a, uint64x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly64x2_t vtrn2q_p64 (poly64x2_t a, poly64x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x2_t vtrn2_f32 (float32x2_t a, float32x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

float32x4_t vtrn2q_f32 (float32x4_t a, float32x4_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

float64x2_t vtrn2q_f64 (float64x2_t a, float64x2_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vtrn2_p8 (poly8x8_t a, poly8x8_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vtrn2q_p8 (poly8x16_t a, poly8x16_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x4_t vtrn2_p16 (poly16x4_t a, poly16x4_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

poly16x8_t vtrn2q_p16 (poly16x8_t a, poly16x8_t b)Transpose vectors

Description

A64 Instruction

TRN2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vtbl1_s8 (int8x8_t a, int8x8_t b)Table vector lookup

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → Zeros(64):a 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtbl1_u8 (uint8x8_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → Zeros(64):a 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vtbl1_p8 (poly8x8_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → Zeros(64):a 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vtbx1_s8 (int8x8_t a, int8x8_t b, int8x8_t c)Bitwise insert if false

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

A64 Instruction

MOVI Vtmp.8B,#8
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 

+Vn → Zeros(64):b 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint8x8_t vtbx1_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Bitwise insert if false

Description

A64 Instruction

MOVI Vtmp.8B,#8
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 

+Vn → Zeros(64):b 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly8x8_t vtbx1_p8 (poly8x8_t a, poly8x8_t b, uint8x8_t c)Bitwise insert if false

Description

A64 Instruction

MOVI Vtmp.8B,#8
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B, Vtmp.8B
+

Argument Preparation

a → Vd 

+Vn → Zeros(64):b 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int8x8_t vtbl2_s8 (int8x8x2_t a, int8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtbl2_u8 (uint8x8x2_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vtbl2_p8 (poly8x8x2_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vtbl3_s8 (int8x8x3_t a, int8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+Vn+1 → Zeros(64):a.val[2] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtbl3_u8 (uint8x8x3_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+Vn+1 → Zeros(64):a.val[2] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vtbl3_p8 (poly8x8x3_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+Vn+1 → Zeros(64):a.val[2] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vtbl4_s8 (int8x8x4_t a, int8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+Vn+1 → a.val[3]:a.val[2] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtbl4_u8 (uint8x8x4_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+Vn+1 → a.val[3]:a.val[2] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vtbl4_p8 (poly8x8x4_t a, uint8x8_t b)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 

+Vn+1 → a.val[3]:a.val[2] 

+b → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vtbx2_s8 (int8x8_t a, int8x8x2_t b, int8x8_t c)Table vector lookup extension

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtbx2_u8 (uint8x8_t a, uint8x8x2_t b, uint8x8_t c)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vtbx2_p8 (poly8x8_t a, poly8x8x2_t b, uint8x8_t c)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vtbx3_s8 (int8x8_t a, int8x8x3_t b, int8x8_t c)Bitwise insert if false

Description

A64 Instruction

MOVI Vtmp.8B,#24
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+Vn+1 → Zeros(64):b.val[2] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

uint8x8_t vtbx3_u8 (uint8x8_t a, uint8x8x3_t b, uint8x8_t c)Bitwise insert if false

Description

A64 Instruction

MOVI Vtmp.8B,#24
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+Vn+1 → Zeros(64):b.val[2] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

poly8x8_t vtbx3_p8 (poly8x8_t a, poly8x8x3_t b, uint8x8_t c)Bitwise insert if false

Description

A64 Instruction

MOVI Vtmp.8B,#24
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+Vn+1 → Zeros(64):b.val[2] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);

Supported architectures

v7/A32/A64

int8x8_t vtbx4_s8 (int8x8_t a, int8x8x4_t b, int8x8_t c)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+Vn+1 → b.val[3]:b.val[2] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vtbx4_u8 (uint8x8_t a, uint8x8x4_t b, uint8x8_t c)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+Vn+1 → b.val[3]:b.val[2] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vtbx4_p8 (poly8x8_t a, poly8x8x4_t b, uint8x8_t c)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd 

+Vn → b.val[1]:b.val[0] 

+Vn+1 → b.val[3]:b.val[2] 

+c → Vm

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vqtbl1_s8 (int8x16_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

t → Vn.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbl1q_s8 (int8x16_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

t → Vn.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbl1_u8 (uint8x16_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

t → Vn.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbl1q_u8 (uint8x16_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

t → Vn.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbl1_p8 (poly8x16_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

t → Vn.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbl1q_p8 (poly8x16_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

t → Vn.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbx1_s8 (int8x8_t a, int8x16_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t → Vn.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbx1q_s8 (int8x16_t a, int8x16_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t → Vn.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbx1_u8 (uint8x8_t a, uint8x16_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t → Vn.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbx1q_u8 (uint8x16_t a, uint8x16_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t → Vn.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbx1_p8 (poly8x8_t a, poly8x16_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t → Vn.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbx1q_p8 (poly8x16_t a, poly8x16_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t → Vn.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbl2_s8 (int8x16x2_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbl2q_s8 (int8x16x2_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbl2_u8 (uint8x16x2_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbl2q_u8 (uint8x16x2_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbl2_p8 (poly8x16x2_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbl2q_p8 (poly8x16x2_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbl3_s8 (int8x16x3_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbl3q_s8 (int8x16x3_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbl3_u8 (uint8x16x3_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbl3q_u8 (uint8x16x3_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbl3_p8 (poly8x16x3_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbl3q_p8 (poly8x16x3_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbl4_s8 (int8x16x4_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbl4q_s8 (int8x16x4_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbl4_u8 (uint8x16x4_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbl4q_u8 (uint8x16x4_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbl4_p8 (poly8x16x4_t t, uint8x8_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbl4q_p8 (poly8x16x4_t t, uint8x16_t idx)Table vector lookup

Description

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbx2_s8 (int8x8_t a, int8x16x2_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbx2q_s8 (int8x16_t a, int8x16x2_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbx2_u8 (uint8x8_t a, uint8x16x2_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbx2q_u8 (uint8x16_t a, uint8x16x2_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbx2_p8 (poly8x8_t a, poly8x16x2_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbx2q_p8 (poly8x16_t a, poly8x16x2_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbx3_s8 (int8x8_t a, int8x16x3_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbx3q_s8 (int8x16_t a, int8x16x3_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbx3_u8 (uint8x8_t a, uint8x16x3_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbx3q_u8 (uint8x16_t a, uint8x16x3_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbx3_p8 (poly8x8_t a, poly8x16x3_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbx3q_p8 (poly8x16_t a, poly8x16x3_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x8_t vqtbx4_s8 (int8x8_t a, int8x16x4_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

int8x16_t vqtbx4q_s8 (int8x16_t a, int8x16x4_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x8_t vqtbx4_u8 (uint8x8_t a, uint8x16x4_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8x16_t vqtbx4q_u8 (uint8x16_t a, uint8x16x4_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x8_t vqtbx4_p8 (poly8x8_t a, poly8x16x4_t t, uint8x8_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.8B

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

poly8x16_t vqtbx4q_p8 (poly8x16_t a, poly8x16x4_t t, uint8x16_t idx)Table vector lookup extension

Description

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 

+t.val[0] → Vn.16B 

+t.val[1] → Vn+1.16B 

+t.val[2] → Vn+2.16B 

+t.val[3] → Vn+3.16B 

+idx → Vm.16B

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;

Supported architectures

A64

uint8_t vget_lane_u8 (uint8x8_t v, const int lane)Unsigned move vector element to general-purpose register

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.8B 

+0 << lane << 7

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

uint16_t vget_lane_u16 (uint16x4_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 

+0 << lane << 3

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

uint32_t vget_lane_u32 (uint32x2_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.2S 

+0 << lane << 1

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

uint64_t vget_lane_u64 (uint64x1_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 

+0 << lane << 0

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

poly64_t vget_lane_p64 (poly64x1_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 

+0 << lane << 0

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

A32/A64

int8_t vget_lane_s8 (int8x8_t v, const int lane)Signed move vector element to general-purpose register

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

A64 Instruction

SMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.8B 

+0 << lane << 7

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

int16_t vget_lane_s16 (int16x4_t v, const int lane)Signed move vector element to general-purpose register

Description

A64 Instruction

SMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 

+0 << lane << 3

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

int32_t vget_lane_s32 (int32x2_t v, const int lane)Signed move vector element to general-purpose register

Description

A64 Instruction

SMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.2S 

+0 << lane << 1

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

int64_t vget_lane_s64 (int64x1_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 

+0 << lane << 0

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

poly8_t vget_lane_p8 (poly8x8_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.8B 

+0 << lane << 7

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

poly16_t vget_lane_p16 (poly16x4_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 

+0 << lane << 3

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

float32_t vget_lane_f32 (float32x2_t v, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

v → Vn.2S 

+0 << lane << 1

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64_t vget_lane_f64 (float64x1_t v, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 

+0 << lane << 0

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8_t vgetq_lane_u8 (uint8x16_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.16B 

+0 << lane << 15

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

uint16_t vgetq_lane_u16 (uint16x8_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 

+0 << lane << 7

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

uint32_t vgetq_lane_u32 (uint32x4_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.4S 

+0 << lane << 3

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

uint64_t vgetq_lane_u64 (uint64x2_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 

+0 << lane << 1

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

poly64_t vgetq_lane_p64 (poly64x2_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 

+0 << lane << 1

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

A32/A64

int8_t vgetq_lane_s8 (int8x16_t v, const int lane)Signed move vector element to general-purpose register

Description

A64 Instruction

SMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.16B 

+0 << lane << 15

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

int16_t vgetq_lane_s16 (int16x8_t v, const int lane)Signed move vector element to general-purpose register

Description

A64 Instruction

SMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 

+0 << lane << 7

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

int32_t vgetq_lane_s32 (int32x4_t v, const int lane)Signed move vector element to general-purpose register

Description

A64 Instruction

SMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.4S 

+0 << lane << 3

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

int64_t vgetq_lane_s64 (int64x2_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 

+0 << lane << 1

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

poly8_t vgetq_lane_p8 (poly8x16_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.16B 

+0 << lane << 15

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

poly16_t vgetq_lane_p16 (poly16x8_t v, const int lane)Unsigned move vector element to general-purpose register

Description

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 

+0 << lane << 7

Results

Rd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);

Supported architectures

v7/A32/A64

float16_t vget_lane_f16 (float16x4_t v, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 

+0 << lane << 3

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float16_t vgetq_lane_f16 (float16x8_t v, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 

+0 << lane << 7

Results

Hd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32_t vgetq_lane_f32 (float32x4_t v, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

v → Vn.4S 

+0 << lane << 3

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64_t vgetq_lane_f64 (float64x2_t v, const int lane)Duplicate general-purpose register to vector

Description

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 

+0 << lane << 1

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x8_t vset_lane_u8 (uint8_t a, uint8x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.8B 

+0 << lane << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vset_lane_u16 (uint16_t a, uint16x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vset_lane_u32 (uint32_t a, uint32x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vset_lane_u64 (uint64_t a, uint64x1_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.1D 

+0 << lane << 0

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x1_t vset_lane_p64 (poly64_t a, poly64x1_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.1D 

+0 << lane << 0

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

int8x8_t vset_lane_s8 (int8_t a, int8x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.8B 

+0 << lane << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vset_lane_s16 (int16_t a, int16x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vset_lane_s32 (int32_t a, int32x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vset_lane_s64 (int64_t a, int64x1_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.1D 

+0 << lane << 0

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vset_lane_p8 (poly8_t a, poly8x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.8B 

+0 << lane << 7

Results

Vd.8B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4_t vset_lane_p16 (poly16_t a, poly16x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float16x4_t vset_lane_f16 (float16_t a, float16x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Vn.H[0]
+

Argument Preparation

a → VnH 

+v → Vd.4H 

+0 << lane << 3

Results

Vd.4H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float16x8_t vsetq_lane_f16 (float16_t a, float16x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Vn.H[0]
+

Argument Preparation

a → VnH 

+v → Vd.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vset_lane_f32 (float32_t a, float32x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2S 

+0 << lane << 1

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vset_lane_f64 (float64_t a, float64x1_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.1D 

+0 << lane << 0

Results

Vd.1D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

uint8x16_t vsetq_lane_u8 (uint8_t a, uint8x16_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.16B 

+0 << lane << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vsetq_lane_u16 (uint16_t a, uint16x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vsetq_lane_u32 (uint32_t a, uint32x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vsetq_lane_u64 (uint64_t a, uint64x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly64x2_t vsetq_lane_p64 (poly64_t a, poly64x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A32/A64

int8x16_t vsetq_lane_s8 (int8_t a, int8x16_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.16B 

+0 << lane << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vsetq_lane_s16 (int16_t a, int16x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vsetq_lane_s32 (int32_t a, int32x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vsetq_lane_s64 (int64_t a, int64x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vsetq_lane_p8 (poly8_t a, poly8x16_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.16B 

+0 << lane << 15

Results

Vd.16B → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8_t vsetq_lane_p16 (poly16_t a, poly16x8_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.8H 

+0 << lane << 7

Results

Vd.8H → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vsetq_lane_f32 (float32_t a, float32x4_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.4S 

+0 << lane << 3

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

v7/A32/A64

float64x2_t vsetq_lane_f64 (float64_t a, float64x2_t v, const int lane)Insert vector element from general-purpose register

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 

+v → Vd.2D 

+0 << lane << 1

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;

Supported architectures

A64

float32_t vrecpxs_f32 (float32_t a)Floating-point reciprocal exponent

Description

Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FRECPX Sd,Sn
+

Argument Preparation

a → Sn

Results

Sd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecpX(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64_t vrecpxd_f64 (float64_t a)Floating-point reciprocal exponent

Description

A64 Instruction

FRECPX Dd,Dn
+

Argument Preparation

a → Dn

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecpX(element, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x2_t vfma_n_f32 (float32x2_t a, float32x2_t b, float32_t n)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+n → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vfmaq_n_f32 (float32x4_t a, float32x4_t b, float32_t n)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+n → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vfms_n_f32 (float32x2_t a, float32x2_t b, float32_t n)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 

+b → Vn.2S 

+n → Vm.S[0]

Results

Vd.2S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float32x4_t vfmsq_n_f32 (float32x4_t a, float32x4_t b, float32_t n)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 

+b → Vn.4S 

+n → Vm.S[0]

Results

Vd.4S → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vfma_n_f64 (float64x1_t a, float64x1_t b, float64_t n)Floating-point fused multiply-add

Description

A64 Instruction

FMADD Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 

+b → Dn 

+n → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmaq_n_f64 (float64x2_t a, float64x2_t b, float64_t n)Floating-point fused multiply-add to accumulator

Description

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+n → Vm.D[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x1_t vfms_n_f64 (float64x1_t a, float64x1_t b, float64_t n)Floating-point fused multiply-subtract

Description

A64 Instruction

FMSUB Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 

+b → Dn 

+n → Dm

Results

Dd → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+operand1 = FPNeg(operand1);
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;

Supported architectures

A64

float64x2_t vfmsq_n_f64 (float64x2_t a, float64x2_t b, float64_t n)Floating-point fused multiply-subtract from accumulator

Description

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[0]
+

Argument Preparation

a → Vd.2D 

+b → Vn.2D 

+n → Vm.D[0]

Results

Vd.2D → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;

Supported architectures

A64

int8x8x2_t vtrn_s8 (int8x8_t a, int8x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.8B,Vn.8B,Vm.8B
+TRN2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4x2_t vtrn_s16 (int16x4_t a, int16x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.4H,Vn.4H,Vm.4H
+TRN2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8x2_t vtrn_u8 (uint8x8_t a, uint8x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.8B,Vn.8B,Vm.8B
+TRN2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4x2_t vtrn_u16 (uint16x4_t a, uint16x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.4H,Vn.4H,Vm.4H
+TRN2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8x2_t vtrn_p8 (poly8x8_t a, poly8x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.8B,Vn.8B,Vm.8B
+TRN2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4x2_t vtrn_p16 (poly16x4_t a, poly16x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.4H,Vn.4H,Vm.4H
+TRN2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2x2_t vtrn_s32 (int32x2_t a, int32x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.2S,Vn.2S,Vm.2S
+TRN2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2x2_t vtrn_f32 (float32x2_t a, float32x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.2S,Vn.2S,Vm.2S
+TRN2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2x2_t vtrn_u32 (uint32x2_t a, uint32x2_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.2S,Vn.2S,Vm.2S
+TRN2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16x2_t vtrnq_s8 (int8x16_t a, int8x16_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.16B,Vn.16B,Vm.16B
+TRN2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8x2_t vtrnq_s16 (int16x8_t a, int16x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.8H,Vn.8H,Vm.8H
+TRN2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4x2_t vtrnq_s32 (int32x4_t a, int32x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.4S,Vn.4S,Vm.4S
+TRN2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4x2_t vtrnq_f32 (float32x4_t a, float32x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.4S,Vn.4S,Vm.4S
+TRN2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16x2_t vtrnq_u8 (uint8x16_t a, uint8x16_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.16B,Vn.16B,Vm.16B
+TRN2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8x2_t vtrnq_u16 (uint16x8_t a, uint16x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.8H,Vn.8H,Vm.8H
+TRN2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4x2_t vtrnq_u32 (uint32x4_t a, uint32x4_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.4S,Vn.4S,Vm.4S
+TRN2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16x2_t vtrnq_p8 (poly8x16_t a, poly8x16_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.16B,Vn.16B,Vm.16B
+TRN2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8x2_t vtrnq_p16 (poly16x8_t a, poly16x8_t b)Transpose vectors

Description

A64 Instruction

TRN1 Vd1.8H,Vn.8H,Vm.8H
+TRN2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8x2_t vzip_s8 (int8x8_t a, int8x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.8B,Vn.8B,Vm.8B
+ZIP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4x2_t vzip_s16 (int16x4_t a, int16x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.4H,Vn.4H,Vm.4H
+ZIP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8x2_t vzip_u8 (uint8x8_t a, uint8x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.8B,Vn.8B,Vm.8B
+ZIP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4x2_t vzip_u16 (uint16x4_t a, uint16x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.4H,Vn.4H,Vm.4H
+ZIP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8x2_t vzip_p8 (poly8x8_t a, poly8x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.8B,Vn.8B,Vm.8B
+ZIP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4x2_t vzip_p16 (poly16x4_t a, poly16x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.4H,Vn.4H,Vm.4H
+ZIP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2x2_t vzip_s32 (int32x2_t a, int32x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.2S,Vn.2S,Vm.2S
+ZIP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2x2_t vzip_f32 (float32x2_t a, float32x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.2S,Vn.2S,Vm.2S
+ZIP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2x2_t vzip_u32 (uint32x2_t a, uint32x2_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.2S,Vn.2S,Vm.2S
+ZIP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16x2_t vzipq_s8 (int8x16_t a, int8x16_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.16B,Vn.16B,Vm.16B
+ZIP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8x2_t vzipq_s16 (int16x8_t a, int16x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.8H,Vn.8H,Vm.8H
+ZIP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4x2_t vzipq_s32 (int32x4_t a, int32x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.4S,Vn.4S,Vm.4S
+ZIP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4x2_t vzipq_f32 (float32x4_t a, float32x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.4S,Vn.4S,Vm.4S
+ZIP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16x2_t vzipq_u8 (uint8x16_t a, uint8x16_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.16B,Vn.16B,Vm.16B
+ZIP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8x2_t vzipq_u16 (uint16x8_t a, uint16x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.8H,Vn.8H,Vm.8H
+ZIP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4x2_t vzipq_u32 (uint32x4_t a, uint32x4_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.4S,Vn.4S,Vm.4S
+ZIP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16x2_t vzipq_p8 (poly8x16_t a, poly8x16_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.16B,Vn.16B,Vm.16B
+ZIP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8x2_t vzipq_p16 (poly16x8_t a, poly16x8_t b)Zip vectors

Description

A64 Instruction

ZIP1 Vd1.8H,Vn.8H,Vm.8H
+ZIP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x8x2_t vuzp_s8 (int8x8_t a, int8x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.8B,Vn.8B,Vm.8B
+UZP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4x2_t vuzp_s16 (int16x4_t a, int16x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.4H,Vn.4H,Vm.4H
+UZP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x2x2_t vuzp_s32 (int32x2_t a, int32x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.2S,Vn.2S,Vm.2S
+UZP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x2x2_t vuzp_f32 (float32x2_t a, float32x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.2S,Vn.2S,Vm.2S
+UZP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x8x2_t vuzp_u8 (uint8x8_t a, uint8x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.8B,Vn.8B,Vm.8B
+UZP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x4x2_t vuzp_u16 (uint16x4_t a, uint16x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.4H,Vn.4H,Vm.4H
+UZP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x2x2_t vuzp_u32 (uint32x2_t a, uint32x2_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.2S,Vn.2S,Vm.2S
+UZP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 

+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x8x2_t vuzp_p8 (poly8x8_t a, poly8x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.8B,Vn.8B,Vm.8B
+UZP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 

+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x4x2_t vuzp_p16 (poly16x4_t a, poly16x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.4H,Vn.4H,Vm.4H
+UZP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 

+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int8x16x2_t vuzpq_s8 (int8x16_t a, int8x16_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.16B,Vn.16B,Vm.16B
+UZP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x8x2_t vuzpq_s16 (int16x8_t a, int16x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.8H,Vn.8H,Vm.8H
+UZP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int32x4x2_t vuzpq_s32 (int32x4_t a, int32x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.4S,Vn.4S,Vm.4S
+UZP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

float32x4x2_t vuzpq_f32 (float32x4_t a, float32x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.4S,Vn.4S,Vm.4S
+UZP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint8x16x2_t vuzpq_u8 (uint8x16_t a, uint8x16_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.16B,Vn.16B,Vm.16B
+UZP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint16x8x2_t vuzpq_u16 (uint16x8_t a, uint16x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.8H,Vn.8H,Vm.8H
+UZP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

uint32x4x2_t vuzpq_u32 (uint32x4_t a, uint32x4_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.4S,Vn.4S,Vm.4S
+UZP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 

+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly8x16x2_t vuzpq_p8 (poly8x16_t a, poly8x16_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.16B,Vn.16B,Vm.16B
+UZP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 

+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

poly16x8x2_t vuzpq_p16 (poly16x8_t a, poly16x8_t b)Unzip vectors

Description

A64 Instruction

UZP1 Vd1.8H,Vn.8H,Vm.8H
+UZP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 

+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_s8 (int8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_s16 (int16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_s32 (int32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

A32/A64

poly64x1_t vreinterpret_p64_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A64

float16x4_t vreinterpret_f16_f32 (float32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_u8 (uint8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_u16 (uint16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_u32 (uint32x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_p8 (poly8x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_p16 (poly16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_u64 (uint64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A64

uint64x1_t vreinterpret_u64_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A32/A64

float16x4_t vreinterpret_f16_s64 (int64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int8x8_t vreinterpret_s8_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

int16x4_t vreinterpret_s16_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

int32x2_t vreinterpret_s32_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

float32x2_t vreinterpret_f32_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

uint8x8_t vreinterpret_u8_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

uint16x4_t vreinterpret_u16_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint32x2_t vreinterpret_u32_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

poly8x8_t vreinterpret_p8_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

poly16x4_t vreinterpret_p16_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

uint64x1_t vreinterpret_u64_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

int64x1_t vreinterpret_s64_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

float64x1_t vreinterpret_f64_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A64

poly64x1_t vreinterpret_p64_f16 (float16x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H

Results

Vd.1D → result
+

Supported architectures

A32/A64

int16x8_t vreinterpretq_s16_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_s8 (int8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_s16 (int16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_s32 (int32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.1Q → result
+

Supported architectures

A32/A64

poly64x2_t vreinterpretq_p64_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A64

poly128_t vreinterpretq_p128_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.2D → result
+

Supported architectures

A64

float16x8_t vreinterpretq_f16_f32 (float32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_u8 (uint8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_u16 (uint16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_u32 (uint32x4_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_p8 (poly8x16_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.1Q → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_p16 (poly16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly64x2_t vreinterpretq_p64_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.2D → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_u64 (uint64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A32/A64

float16x8_t vreinterpretq_f16_s64 (int64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int8x16_t vreinterpretq_s8_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

int16x8_t vreinterpretq_s16_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

int32x4_t vreinterpretq_s32_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

float32x4_t vreinterpretq_f32_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

uint8x16_t vreinterpretq_u8_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

uint16x8_t vreinterpretq_u16_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint32x4_t vreinterpretq_u32_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

poly8x16_t vreinterpretq_p8_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

poly16x8_t vreinterpretq_p16_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

uint64x2_t vreinterpretq_u64_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

int64x2_t vreinterpretq_s64_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

float64x2_t vreinterpretq_f64_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A64

poly64x2_t vreinterpretq_p64_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.2D → result
+

Supported architectures

A32/A64

poly128_t vreinterpretq_p128_f16 (float16x8_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H

Results

Vd.1Q → result
+

Supported architectures

A32/A64

int8x8_t vreinterpret_s8_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

A64

int16x4_t vreinterpret_s16_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A64

int32x2_t vreinterpret_s32_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

A64

uint8x8_t vreinterpret_u8_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

A64

uint16x4_t vreinterpret_u16_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A64

uint32x2_t vreinterpret_u32_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

A64

poly8x8_t vreinterpret_p8_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

A64

poly16x4_t vreinterpret_p16_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A64

uint64x1_t vreinterpret_u64_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A64

int64x1_t vreinterpret_s64_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A64

float16x4_t vreinterpret_f16_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A64

float32x2_t vreinterpret_f32_f64 (float64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

A64

int8x16_t vreinterpretq_s8_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

A64

int16x8_t vreinterpretq_s16_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A64

int32x4_t vreinterpretq_s32_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

A64

uint8x16_t vreinterpretq_u8_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

A64

uint16x8_t vreinterpretq_u16_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A64

uint32x4_t vreinterpretq_u32_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

A64

poly8x16_t vreinterpretq_p8_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

A64

poly16x8_t vreinterpretq_p16_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A64

uint64x2_t vreinterpretq_u64_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A64

int64x2_t vreinterpretq_s64_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A64

float16x8_t vreinterpretq_f16_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A64

float32x4_t vreinterpretq_f32_f64 (float64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

A64

int8x8_t vreinterpret_s8_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

A32/A64

int16x4_t vreinterpret_s16_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A32/A64

int32x2_t vreinterpret_s32_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

A32/A64

uint8x8_t vreinterpret_u8_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

A32/A64

uint16x4_t vreinterpret_u16_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A32/A64

uint32x2_t vreinterpret_u32_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.2S → result
+

Supported architectures

A32/A64

poly8x8_t vreinterpret_p8_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.8B → result
+

Supported architectures

A32/A64

poly16x4_t vreinterpret_p16_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A32/A64

uint64x1_t vreinterpret_u64_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A32/A64

int64x1_t vreinterpret_s64_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A32/A64

float64x1_t vreinterpret_f64_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.1D → result
+

Supported architectures

A64

float16x4_t vreinterpret_f16_p64 (poly64x1_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D

Results

Vd.4H → result
+

Supported architectures

A32/A64

int8x16_t vreinterpretq_s8_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

A32/A64

int16x8_t vreinterpretq_s16_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A32/A64

int32x4_t vreinterpretq_s32_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

A32/A64

uint8x16_t vreinterpretq_u8_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

A32/A64

uint16x8_t vreinterpretq_u16_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A32/A64

uint32x4_t vreinterpretq_u32_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.4S → result
+

Supported architectures

A32/A64

poly8x16_t vreinterpretq_p8_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.16B → result
+

Supported architectures

A32/A64

poly16x8_t vreinterpretq_p16_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A32/A64

uint64x2_t vreinterpretq_u64_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A32/A64

int64x2_t vreinterpretq_s64_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A32/A64

float64x2_t vreinterpretq_f64_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.2D → result
+

Supported architectures

A64

float16x8_t vreinterpretq_f16_p64 (poly64x2_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D

Results

Vd.8H → result
+

Supported architectures

A32/A64

int8x16_t vreinterpretq_s8_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.16B → result
+

Supported architectures

A32/A64

int16x8_t vreinterpretq_s16_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.8H → result
+

Supported architectures

A32/A64

int32x4_t vreinterpretq_s32_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.4S → result
+

Supported architectures

A32/A64

uint8x16_t vreinterpretq_u8_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.16B → result
+

Supported architectures

A32/A64

uint16x8_t vreinterpretq_u16_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.8H → result
+

Supported architectures

A32/A64

uint32x4_t vreinterpretq_u32_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.4S → result
+

Supported architectures

A32/A64

poly8x16_t vreinterpretq_p8_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.16B → result
+

Supported architectures

A32/A64

poly16x8_t vreinterpretq_p16_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.8H → result
+

Supported architectures

A32/A64

uint64x2_t vreinterpretq_u64_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.2D → result
+

Supported architectures

A32/A64

int64x2_t vreinterpretq_s64_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.2D → result
+

Supported architectures

A32/A64

float64x2_t vreinterpretq_f64_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.2D → result
+

Supported architectures

A64

float16x8_t vreinterpretq_f16_p128 (poly128_t a)Vector reinterpret cast operation

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q

Results

Vd.8H → result
+

Supported architectures

A32/A64

poly128_t vldrq_p128 (poly128_t const * ptr)Load SIMD&FP register

Description

Load SIMD&FP Register (register offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

A64 Instruction

LDR Qd,[Xn]
+

Argument Preparation

ptr → Xn

Results

Qd → result
+

Operation

bits(64) offset = ExtendReg(m, extend_type, shift);
+if HaveMTEExt() then
+    boolean is_load_store = memop IN {MemOp_STORE, MemOp_LOAD};
+    SetNotTagCheckedInstruction(is_load_store && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+bits(64) address;
+bits(datasize) data;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+address = address + offset;
+
+case memop of
+    when MemOp_STORE
+        data = V[t];
+        Mem[address, datasize DIV 8, AccType_VEC] = data;
+
+    when MemOp_LOAD
+        data = Mem[address, datasize DIV 8, AccType_VEC];
+        V[t] = data;

Supported architectures

A32/A64

void vstrq_p128 (poly128_t * ptr, poly128_t val)Store SIMD&FP register

Description

Store SIMD&FP register (register offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

A64 Instruction

STR Qt,[Xn]
+

Argument Preparation

ptr → Xn 

+val → Qt

Results

void → result
+

Operation

bits(64) offset = ExtendReg(m, extend_type, shift);
+if HaveMTEExt() then
+    boolean is_load_store = memop IN {MemOp_STORE, MemOp_LOAD};
+    SetNotTagCheckedInstruction(is_load_store && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+bits(64) address;
+bits(datasize) data;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+address = address + offset;
+
+case memop of
+    when MemOp_STORE
+        data = V[t];
+        Mem[address, datasize DIV 8, AccType_VEC] = data;
+
+    when MemOp_LOAD
+        data = Mem[address, datasize DIV 8, AccType_VEC];
+        V[t] = data;

Supported architectures

A32/A64

uint8x16_t vaeseq_u8 (uint8x16_t data, uint8x16_t key)AES single round encryption

Description

AES single round encryption.

A64 Instruction

AESE Vd.16B,Vn.16B
+

Argument Preparation

data → Vd.16B 

+key → Vn.16B

Results

Vd.16B → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+result = operand1 EOR operand2;
+result = AESSubBytes(AESShiftRows(result));
+
+V[d] = result;

Supported architectures

A32/A64

uint8x16_t vaesdq_u8 (uint8x16_t data, uint8x16_t key)AES single round decryption

Description

AES single round decryption.

A64 Instruction

AESD Vd.16B,Vn.16B
+

Argument Preparation

data → Vd.16B 

+key → Vn.16B

Results

Vd.16B → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+result = operand1 EOR operand2;
+result = AESInvSubBytes(AESInvShiftRows(result));
+V[d] = result;

Supported architectures

A32/A64

uint8x16_t vaesmcq_u8 (uint8x16_t data)AES mix columns

Description

AES mix columns.

A64 Instruction

AESMC Vd.16B,Vn.16B
+

Argument Preparation

data → Vn.16B

Results

Vd.16B → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand = V[n];
+bits(128) result;
+result = AESMixColumns(operand);
+V[d] = result;

Supported architectures

A32/A64

uint8x16_t vaesimcq_u8 (uint8x16_t data)AES inverse mix columns

Description

AES inverse mix columns.

A64 Instruction

AESIMC Vd.16B,Vn.16B
+

Argument Preparation

data → Vn.16B

Results

Vd.16B → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand = V[n];
+bits(128) result;
+result = AESInvMixColumns(operand);
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)SHA1 hash update (choose)

Description

SHA1 hash update (choose).

A64 Instruction

SHA1C Qd,Sn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 

+hash_e → Sn 

+wk → Vm.4S

Results

Qd → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) X = V[d];
+bits(32) Y = V[n];    // Note: 32 not 128 bits wide
+bits(128) W = V[m];
+bits(32) t;
+
+for e = 0 to 3
+    t = SHAchoose(X<63:32>, X<95:64>, X<127:96>);
+    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
+    X<63:32> = ROL(X<63:32>, 30);
+    <Y, X> = ROL(Y:X, 32);
+V[d] = X;

Supported architectures

A32/A64

uint32x4_t vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)SHA1 hash update (parity)

Description

SHA1 hash update (parity).

A64 Instruction

SHA1P Qd,Sn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 

+hash_e → Sn 

+wk → Vm.4S

Results

Qd → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) X = V[d];
+bits(32) Y = V[n];    // Note: 32 not 128 bits wide
+bits(128) W = V[m];
+bits(32) t;
+
+for e = 0 to 3
+    t = SHAparity(X<63:32>, X<95:64>, X<127:96>);
+    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
+    X<63:32> = ROL(X<63:32>, 30);
+    <Y, X> = ROL(Y:X, 32);
+V[d] = X;

Supported architectures

A32/A64

uint32x4_t vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)SHA1 hash update (majority)

Description

SHA1 hash update (majority).

A64 Instruction

SHA1M Qd,Sn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 

+hash_e → Sn 

+wk → Vm.4S

Results

Qd → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) X = V[d];
+bits(32) Y = V[n];    // Note: 32 not 128 bits wide
+bits(128) W = V[m];
+bits(32) t;
+
+for e = 0 to 3
+    t = SHAmajority(X<63:32>, X<95:64>, X<127:96>);
+    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
+    X<63:32> = ROL(X<63:32>, 30);
+    <Y, X> = ROL(Y:X, 32);
+V[d] = X;

Supported architectures

A32/A64

uint32_t vsha1h_u32 (uint32_t hash_e)SHA1 fixed rotate

Description

SHA1 fixed rotate.

A64 Instruction

SHA1H Sd,Sn
+

Argument Preparation

hash_e → Sn

Results

Sd → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(32) operand = V[n];    // read element [0] only,  [1-3] zeroed
+V[d] = ROL(operand, 30);

Supported architectures

A32/A64

uint32x4_t vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)SHA1 schedule update 0

Description

SHA1 schedule update 0.

A64 Instruction

SHA1SU0 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

w0_3 → Vd.4S 

+w4_7 → Vn.4S 

+w8_11 → Vm.4S

Results

Vd.4S → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) operand3 = V[m];
+bits(128) result;
+
+result = operand2<63:0>:operand1<127:64>;
+result = result EOR operand1 EOR operand3;
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)SHA1 schedule update 1

Description

SHA1 schedule update 1.

A64 Instruction

SHA1SU1 Vd.4S,Vn.4S
+

Argument Preparation

tw0_3 → Vd.4S 

+w12_15 → Vn.4S

Results

Vd.4S → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+bits(128) T = operand1 EOR LSR(operand2, 32);
+result<31:0> = ROL(T<31:0>, 1);
+result<63:32> = ROL(T<63:32>, 1);
+result<95:64> = ROL(T<95:64>, 1);
+result<127:96> = ROL(T<127:96>, 1) EOR ROL(T<31:0>, 2);
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)SHA256 hash update (part 1)

Description

SHA256 hash update (part 1).

A64 Instruction

SHA256H Qd,Qn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 

+hash_efgh → Qn 

+wk → Vm.4S

Results

Qd → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) result;
+result = SHA256hash(V[d], V[n], V[m], TRUE);
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)SHA256 hash update (part 2)

Description

SHA256 hash update (part 2).

A64 Instruction

SHA256H2 Qd,Qn,Vm.4S
+

Argument Preparation

hash_efgh → Qd 

+hash_abcd → Qn 

+wk → Vm.4S

Results

Qd → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) result;
+result = SHA256hash(V[n], V[d], V[m], FALSE);
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)SHA256 schedule update 0

Description

SHA256 schedule update 0.

A64 Instruction

SHA256SU0 Vd.4S,Vn.4S
+

Argument Preparation

w0_3 → Vd.4S 

+w4_7 → Vn.4S

Results

Vd.4S → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+bits(128) T = operand2<31:0>:operand1<127:32>;
+bits(32) elt;
+
+for e = 0 to 3
+    elt = Elem[T, e, 32];
+    elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3);
+    Elem[result, e, 32] = elt + Elem[operand1, e, 32];
+V[d] = result;

Supported architectures

A32/A64

uint32x4_t vsha256su1q_u32 (uint32x4_t tw0_3, uint32x4_t w8_11, uint32x4_t w12_15)SHA256 schedule update 1

Description

SHA256 schedule update 1.

A64 Instruction

SHA256SU1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

tw0_3 → Vd.4S 

+w8_11 → Vn.4S 

+w12_15 → Vm.4S

Results

Vd.4S → result
+

Operation

AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) operand3 = V[m];
+bits(128) result;
+bits(128) T0 = operand3<31:0>:operand2<127:32>;
+bits(64) T1;
+bits(32) elt;
+
+T1 = operand3<127:64>;
+for e = 0 to 1
+    elt = Elem[T1, e, 32];
+    elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
+    elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
+    Elem[result, e, 32] = elt;
+
+T1 = result<63:0>;
+for e = 2 to 3
+    elt = Elem[T1, e-2, 32];
+    elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
+    elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
+    Elem[result, e, 32] = elt;
+
+V[d] = result;

Supported architectures

A32/A64

poly128_t vmull_p64 (poly64_t a, poly64_t b)Polynomial multiply long

Description

A64 Instruction

PMULL Vd.1Q,Vn.1D,Vm.1D
+

Argument Preparation

a → Vn.1D 

+b → Vm.1D

Results

Vd.1Q → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;

Supported architectures

A32/A64

poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)Polynomial multiply long

Description

A64 Instruction

PMULL2 Vd.1Q,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 

+b → Vm.2D

Results

Vd.1Q → result
+

Operation

CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;

Supported architectures

A32/A64

uint32_t __crc32b (uint32_t a, uint8_t b)CRC32 checksum

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.

A64 Instruction

CRC32B Wd,Wn,Wm
+

Argument Preparation

a → Wn 

+b → Wm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32h (uint32_t a, uint16_t b)CRC32 checksum

Description

A64 Instruction

CRC32H Wd,Wn,Wm
+

Argument Preparation

a → Wn 

+b → Wm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32w (uint32_t a, uint32_t b)CRC32 checksum

Description

A64 Instruction

CRC32W Wd,Wn,Wm
+

Argument Preparation

a → Wn 

+b → Wm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32d (uint32_t a, uint64_t b)CRC32 checksum

Description

A64 Instruction

CRC32X Wd,Wn,Xm
+

Argument Preparation

a → Wn 

+b → Xm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32cb (uint32_t a, uint8_t b)CRC32 checksum

Description

A64 Instruction

CRC32CB Wd,Wn,Wm
+

Argument Preparation

a → Wn 

+b → Wm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32ch (uint32_t a, uint16_t b)CRC32 checksum

Description

A64 Instruction

CRC32CH Wd,Wn,Wm
+

Argument Preparation

a → Wn 

+b → Wm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32cw (uint32_t a, uint32_t b)CRC32 checksum

Description

A64 Instruction

CRC32CW Wd,Wn,Wm
+

Argument Preparation

a → Wn 

+b → Wm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

uint32_t __crc32cd (uint32_t a, uint64_t b)CRC32 checksum

Description

A64 Instruction

CRC32CX Wd,Wn,Xm
+

Argument Preparation

a → Wn 

+b → Xm

Results

Wd → result
+

Operation

bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));

Supported architectures

A32/A64

+ +

+ + +

+ // ... + + let children = node.children.borrow(); + let mut children = children + .iter() + .filter(|node| matches!(node.data, NodeData::Element { .. })); + let _input = children.next().expect("no "); + let label = children.next().expect("no "); + let article = children.next().expect("no

"); + assert!(children.next().is_none()); + + // Find `for="..."` in `` + let name = match &label.data { + NodeData::Element { attrs, .. } => attrs + .borrow() + .iter() + .filter(|attr| attr.name.local.eq_str_ignore_ascii_case("for")) + .map(|attr| attr.value.to_string()) + .next() + .expect("no `for` attribute"), + _ => panic!(), + }; + + // Find contents of inner `

` in `` + let label_children = label.children.borrow(); + let mut label_children = label_children + .iter() + .filter(|node| matches!(node.data, NodeData::Element { .. })); + let label_div = label_children.next().expect("no

in "); + assert!(label_children.next().is_none()); + let text = label_div.children.borrow(); + let mut text = text.iter().filter_map(|node| match &node.data { + NodeData::Text { contents } => Some(contents.borrow().to_string()), + _ => None, + }); + let ret = text.next().unwrap(); + let ret = ret.trim(); + let args = text.next().unwrap(); + let args = args.trim(); + assert!(text.next().is_none()); + + // Find the instruction within the article + let article_children = article.children.borrow(); + let mut article_children = article_children + .iter() + .filter(|node| matches!(node.data, NodeData::Element { .. })); + let mut instruction = None; + while let Some(child) = article_children.next() { + let mut header = String::new(); + collect_text(&mut header, child); + if !header.ends_with(" Instruction") { + continue; + } + let next = article_children.next().expect("no next child"); + assert!(instruction.is_none()); + let mut instr = String::new(); + collect_text(&mut instr, &next); + instruction = Some(instr); + } + + let instruction = match instruction { + Some(s) => s.trim().to_lowercase(), + None => panic!("can't find instruction for `{}`", name), + }; + + Intrinsic { + name, + ret: if ret == "void" { + None + } else { + Some(parse_ty(ret)) + }, + instruction, + arguments: args // "(...)" + .trim_start_matches('(') // "...)" + .trim_end_matches(')') // "..." + .split(',') // " Type name ", ".." + .map(|s| s.trim()) // "Type name" + .map(|s| s.rsplitn(2, ' ').nth(1).unwrap()) // "Type" + .map(|s| { + let const_ = "const "; + if s.starts_with(const_) { + (parse_ty(&s[const_.len()..]), true) + } else { + (parse_ty(s), false) + } + }) + .collect(), + } +} + +fn parse_ty(s: &str) -> Type { + let suffix = " const *"; + if s.ends_with(suffix) { + Type::ConstPtr(parse_ty_base(&s[..s.len() - suffix.len()])) + } else if s.ends_with(" *") { + Type::MutPtr(parse_ty_base(&s[..s.len() - 2])) + } else { + *parse_ty_base(s) + } +} + +fn parse_ty_base(s: &str) -> &'static Type { + match s { + "float16_t" => &F16, + "float16x4_t" => &F16X4, + "float16x4x2_t" => &F16X4X2, + "float16x4x3_t" => &F16X4X3, + "float16x4x4_t" => &F16X4X4, + "float16x8_t" => &F16X8, + "float16x8x2_t" => &F16X8X2, + "float16x8x3_t" => &F16X8X3, + "float16x8x4_t" => &F16X8X4, + "float32_t" => &F32, + "float32x2_t" => &F32X2, + "float32x2x2_t" => &F32X2X2, + "float32x2x3_t" => &F32X2X3, + "float32x2x4_t" => &F32X2X4, + "float32x4_t" => &F32X4, + "float32x4x2_t" => &F32X4X2, + "float32x4x3_t" => &F32X4X3, + "float32x4x4_t" => &F32X4X4, + "float64_t" => &F64, + "float64x1_t" => &F64X1, + "float64x1x2_t" => &F64X1X2, + "float64x1x3_t" => &F64X1X3, + "float64x1x4_t" => &F64X1X4, + "float64x2_t" => &F64X2, + "float64x2x2_t" => &F64X2X2, + "float64x2x3_t" => &F64X2X3, + "float64x2x4_t" => &F64X2X4, + "int16_t" => &I16, + "int16x2_t" => &I16X2, + "int16x4_t" => &I16X4, + "int16x4x2_t" => &I16X4X2, + "int16x4x3_t" => &I16X4X3, + "int16x4x4_t" => &I16X4X4, + "int16x8_t" => &I16X8, + "int16x8x2_t" => &I16X8X2, + "int16x8x3_t" => &I16X8X3, + "int16x8x4_t" => &I16X8X4, + "int32_t" | "int" => &I32, + "int32x2_t" => &I32X2, + "int32x2x2_t" => &I32X2X2, + "int32x2x3_t" => &I32X2X3, + "int32x2x4_t" => &I32X2X4, + "int32x4_t" => &I32X4, + "int32x4x2_t" => &I32X4X2, + "int32x4x3_t" => &I32X4X3, + "int32x4x4_t" => &I32X4X4, + "int64_t" => &I64, + "int64x1_t" => &I64X1, + "int64x1x2_t" => &I64X1X2, + "int64x1x3_t" => &I64X1X3, + "int64x1x4_t" => &I64X1X4, + "int64x2_t" => &I64X2, + "int64x2x2_t" => &I64X2X2, + "int64x2x3_t" => &I64X2X3, + "int64x2x4_t" => &I64X2X4, + "int8_t" => &I8, + "int8x16_t" => &I8X16, + "int8x16x2_t" => &I8X16X2, + "int8x16x3_t" => &I8X16X3, + "int8x16x4_t" => &I8X16X4, + "int8x4_t" => &I8X4, + "int8x8_t" => &I8X8, + "int8x8x2_t" => &I8X8X2, + "int8x8x3_t" => &I8X8X3, + "int8x8x4_t" => &I8X8X4, + "poly128_t" => &P128, + "poly16_t" => &P16, + "poly16x4_t" => &POLY16X4, + "poly16x4x2_t" => &P16X4X2, + "poly16x4x3_t" => &P16X4X3, + "poly16x4x4_t" => &P16X4X4, + "poly16x8_t" => &POLY16X8, + "poly16x8x2_t" => &P16X8X2, + "poly16x8x3_t" => &P16X8X3, + "poly16x8x4_t" => &P16X8X4, + "poly64_t" => &P64, + "poly64x1_t" => &POLY64X1, + "poly64x1x2_t" => &P64X1X2, + "poly64x1x3_t" => &P64X1X3, + "poly64x1x4_t" => &P64X1X4, + "poly64x2_t" => &POLY64X2, + "poly64x2x2_t" => &P64X2X2, + "poly64x2x3_t" => &P64X2X3, + "poly64x2x4_t" => &P64X2X4, + "poly8_t" => &P8, + "poly8x16_t" => &POLY8X16, + "poly8x16x2_t" => &POLY8X16X2, + "poly8x16x3_t" => &POLY8X16X3, + "poly8x16x4_t" => &POLY8X16X4, + "poly8x8_t" => &POLY8X8, + "poly8x8x2_t" => &POLY8X8X2, + "poly8x8x3_t" => &POLY8X8X3, + "poly8x8x4_t" => &POLY8X8X4, + "uint16_t" => &U16, + "uint16x4_t" => &U16X4, + "uint16x4x2_t" => &U16X4X2, + "uint16x4x3_t" => &U16X4X3, + "uint16x4x4_t" => &U16X4X4, + "uint16x8_t" => &U16X8, + "uint16x8x2_t" => &U16X8X2, + "uint16x8x3_t" => &U16X8X3, + "uint16x8x4_t" => &U16X8X4, + "uint32_t" => &U32, + "uint32x2_t" => &U32X2, + "uint32x2x2_t" => &U32X2X2, + "uint32x2x3_t" => &U32X2X3, + "uint32x2x4_t" => &U32X2X4, + "uint32x4_t" => &U32X4, + "uint32x4x2_t" => &U32X4X2, + "uint32x4x3_t" => &U32X4X3, + "uint32x4x4_t" => &U32X4X4, + "uint64_t" => &U64, + "uint64x1_t" => &U64X1, + "uint64x1x2_t" => &U64X1X2, + "uint64x1x3_t" => &U64X1X3, + "uint64x1x4_t" => &U64X1X4, + "uint64x2_t" => &U64X2, + "uint64x2x2_t" => &U64X2X2, + "uint64x2x3_t" => &U64X2X3, + "uint64x2x4_t" => &U64X2X4, + "uint8_t" => &U8, + "uint8x16_t" => &U8X16, + "uint8x16x2_t" => &U8X16X2, + "uint8x16x3_t" => &U8X16X3, + "uint8x16x4_t" => &U8X16X4, + "uint8x8_t" => &U8X8, + "uint8x8x2_t" => &U8X8X2, + "uint8x8x3_t" => &U8X8X3, + "uint8x8x4_t" => &U8X8X4, + + _ => panic!("failed to parse html type {:?}", s), + } +} + +fn collect_text(s: &mut String, node: &Node) { + if let NodeData::Text { contents } = &node.data { + s.push(' '); + s.push_str(&contents.borrow().to_string()); + } + for child in node.children.borrow().iter() { + collect_text(s, child); + } +} diff --git a/library/stdarch/crates/stdarch-verify/tests/mips.rs b/library/stdarch/crates/stdarch-verify/tests/mips.rs new file mode 100644 index 000000000..1eb86dc29 --- /dev/null +++ b/library/stdarch/crates/stdarch-verify/tests/mips.rs @@ -0,0 +1,366 @@ +//! Verification of MIPS MSA intrinsics +#![allow(bad_style, unused)] + +// This file is obtained from +// https://gcc.gnu.org/onlinedocs//gcc/MIPS-SIMD-Architecture-Built-in-Functions.html +static HEADER: &str = include_str!("../mips-msa.h"); + +stdarch_verify::mips_functions!(static FUNCTIONS); + +struct Function { + name: &'static str, + arguments: &'static [&'static Type], + ret: Option<&'static Type>, + target_feature: Option<&'static str>, + instrs: &'static [&'static str], + file: &'static str, + required_const: &'static [usize], + has_test: bool, +} + +static F16: Type = Type::PrimFloat(16); +static F32: Type = Type::PrimFloat(32); +static F64: Type = Type::PrimFloat(64); +static I8: Type = Type::PrimSigned(8); +static I16: Type = Type::PrimSigned(16); +static I32: Type = Type::PrimSigned(32); +static I64: Type = Type::PrimSigned(64); +static U8: Type = Type::PrimUnsigned(8); +static U16: Type = Type::PrimUnsigned(16); +static U32: Type = Type::PrimUnsigned(32); +static U64: Type = Type::PrimUnsigned(64); +static NEVER: Type = Type::Never; +static TUPLE: Type = Type::Tuple; +static v16i8: Type = Type::I(8, 16, 1); +static v8i16: Type = Type::I(16, 8, 1); +static v4i32: Type = Type::I(32, 4, 1); +static v2i64: Type = Type::I(64, 2, 1); +static v16u8: Type = Type::U(8, 16, 1); +static v8u16: Type = Type::U(16, 8, 1); +static v4u32: Type = Type::U(32, 4, 1); +static v2u64: Type = Type::U(64, 2, 1); +static v8f16: Type = Type::F(16, 8, 1); +static v4f32: Type = Type::F(32, 4, 1); +static v2f64: Type = Type::F(64, 2, 1); + +#[derive(Debug, Copy, Clone, PartialEq)] +enum Type { + PrimFloat(u8), + PrimSigned(u8), + PrimUnsigned(u8), + PrimPoly(u8), + MutPtr(&'static Type), + ConstPtr(&'static Type), + Tuple, + I(u8, u8, u8), + U(u8, u8, u8), + P(u8, u8, u8), + F(u8, u8, u8), + Never, +} + +#[derive(Copy, Clone, Debug, PartialEq)] +#[allow(non_camel_case_types)] +enum MsaTy { + v16i8, + v8i16, + v4i32, + v2i64, + v16u8, + v8u16, + v4u32, + v2u64, + v8f16, + v4f32, + v2f64, + imm0_1, + imm0_3, + imm0_7, + imm0_15, + imm0_31, + imm0_63, + imm0_255, + imm_n16_15, + imm_n512_511, + imm_n1024_1022, + imm_n2048_2044, + imm_n4096_4088, + i32, + u32, + i64, + u64, + Void, + MutVoidPtr, +} + +impl<'a> From<&'a str> for MsaTy { + fn from(s: &'a str) -> MsaTy { + match s { + "v16i8" => MsaTy::v16i8, + "v8i16" => MsaTy::v8i16, + "v4i32" => MsaTy::v4i32, + "v2i64" => MsaTy::v2i64, + "v16u8" => MsaTy::v16u8, + "v8u16" => MsaTy::v8u16, + "v4u32" => MsaTy::v4u32, + "v2u64" => MsaTy::v2u64, + "v8f16" => MsaTy::v8f16, + "v4f32" => MsaTy::v4f32, + "v2f64" => MsaTy::v2f64, + "imm0_1" => MsaTy::imm0_1, + "imm0_3" => MsaTy::imm0_3, + "imm0_7" => MsaTy::imm0_7, + "imm0_15" => MsaTy::imm0_15, + "imm0_31" => MsaTy::imm0_31, + "imm0_63" => MsaTy::imm0_63, + "imm0_255" => MsaTy::imm0_255, + "imm_n16_15" => MsaTy::imm_n16_15, + "imm_n512_511" => MsaTy::imm_n512_511, + "imm_n1024_1022" => MsaTy::imm_n1024_1022, + "imm_n2048_2044" => MsaTy::imm_n2048_2044, + "imm_n4096_4088" => MsaTy::imm_n4096_4088, + "i32" => MsaTy::i32, + "u32" => MsaTy::u32, + "i64" => MsaTy::i64, + "u64" => MsaTy::u64, + "void" => MsaTy::Void, + "void *" => MsaTy::MutVoidPtr, + v => panic!("unknown ty: \"{}\"", v), + } + } +} + +#[derive(Debug, Clone)] +struct MsaIntrinsic { + id: String, + arg_tys: Vec, + ret_ty: MsaTy, + instruction: String, +} + +struct NoneError; + +impl std::convert::TryFrom<&'static str> for MsaIntrinsic { + // The intrinsics are just C function declarations of the form: + // $ret_ty __builtin_${fn_id}($($arg_ty),*); + type Error = NoneError; + fn try_from(line: &'static str) -> Result { + return inner(line).ok_or(NoneError); + + fn inner(line: &'static str) -> Option { + let first_whitespace = line.find(char::is_whitespace)?; + let ret_ty = &line[0..first_whitespace]; + let ret_ty = MsaTy::from(ret_ty); + + let first_parentheses = line.find('(')?; + assert!(first_parentheses > first_whitespace); + let id = &line[first_whitespace + 1..first_parentheses].trim(); + assert!(id.starts_with("__builtin")); + let mut id_str = "_".to_string(); + id_str += &id[9..]; + let id = id_str; + + let mut arg_tys = Vec::new(); + + let last_parentheses = line.find(')')?; + for arg in (&line[first_parentheses + 1..last_parentheses]).split(',') { + let arg = arg.trim(); + arg_tys.push(MsaTy::from(arg)); + } + + // The instruction is the intrinsic name without the __msa_ prefix. + let instruction = &id[6..]; + let mut instruction = instruction.to_string(); + // With all underscores but the first one replaced with a `.` + if let Some(first_underscore) = instruction.find('_') { + let postfix = instruction[first_underscore + 1..].replace('_', "."); + instruction = instruction[0..=first_underscore].to_string(); + instruction += &postfix; + } + + Some(MsaIntrinsic { + id, + ret_ty, + arg_tys, + instruction, + }) + } + } +} + +#[test] +fn verify_all_signatures() { + // Parse the C intrinsic header file: + let mut intrinsics = std::collections::HashMap::::new(); + for line in HEADER.lines() { + if line.is_empty() { + continue; + } + + use std::convert::TryFrom; + let intrinsic: MsaIntrinsic = TryFrom::try_from(line) + .unwrap_or_else(|_| panic!("failed to parse line: \"{}\"", line)); + assert!(!intrinsics.contains_key(&intrinsic.id)); + intrinsics.insert(intrinsic.id.clone(), intrinsic); + } + + let mut all_valid = true; + for rust in FUNCTIONS { + if !rust.has_test { + let skip = [ + "__msa_ceqi_d", + "__msa_cfcmsa", + "__msa_clei_s_d", + "__msa_clti_s_d", + "__msa_ctcmsa", + "__msa_ldi_d", + "__msa_maxi_s_d", + "__msa_mini_s_d", + "break_", + ]; + if !skip.contains(&rust.name) { + println!( + "missing run-time test named `test_{}` for `{}`", + { + let mut id = rust.name; + while id.starts_with('_') { + id = &id[1..]; + } + id + }, + rust.name + ); + all_valid = false; + } + } + + // Skip some intrinsics that aren't part of MSA + match rust.name { + "break_" => continue, + _ => {} + } + let mips = match intrinsics.get(rust.name) { + Some(i) => i, + None => { + eprintln!( + "missing mips definition for {:?} in {}", + rust.name, rust.file + ); + all_valid = false; + continue; + } + }; + + if let Err(e) = matches(rust, mips) { + println!("failed to verify `{}`", rust.name); + println!(" * {}", e); + all_valid = false; + } + } + assert!(all_valid); +} + +fn matches(rust: &Function, mips: &MsaIntrinsic) -> Result<(), String> { + macro_rules! bail { + ($($t:tt)*) => (return Err(format!($($t)*))) + } + + if rust.ret.is_none() && mips.ret_ty != MsaTy::Void { + bail!("mismatched return value") + } + + if rust.arguments.len() != mips.arg_tys.len() { + bail!("mismatched argument lengths"); + } + + let mut nconst = 0; + for (i, (rust_arg, mips_arg)) in rust.arguments.iter().zip(mips.arg_tys.iter()).enumerate() { + match mips_arg { + MsaTy::v16i8 if **rust_arg == v16i8 => (), + MsaTy::v8i16 if **rust_arg == v8i16 => (), + MsaTy::v4i32 if **rust_arg == v4i32 => (), + MsaTy::v2i64 if **rust_arg == v2i64 => (), + MsaTy::v16u8 if **rust_arg == v16u8 => (), + MsaTy::v8u16 if **rust_arg == v8u16 => (), + MsaTy::v4u32 if **rust_arg == v4u32 => (), + MsaTy::v2u64 if **rust_arg == v2u64 => (), + MsaTy::v4f32 if **rust_arg == v4f32 => (), + MsaTy::v2f64 if **rust_arg == v2f64 => (), + MsaTy::imm0_1 + | MsaTy::imm0_3 + | MsaTy::imm0_7 + | MsaTy::imm0_15 + | MsaTy::imm0_31 + | MsaTy::imm0_63 + | MsaTy::imm0_255 + | MsaTy::imm_n16_15 + | MsaTy::imm_n512_511 + | MsaTy::imm_n1024_1022 + | MsaTy::imm_n2048_2044 + | MsaTy::imm_n4096_4088 + if **rust_arg == I32 => {} + MsaTy::i32 if **rust_arg == I32 => (), + MsaTy::i64 if **rust_arg == I64 => (), + MsaTy::u32 if **rust_arg == U32 => (), + MsaTy::u64 if **rust_arg == U64 => (), + MsaTy::MutVoidPtr if **rust_arg == Type::MutPtr(&U8) => (), + m => bail!( + "mismatched argument \"{}\"= \"{:?}\" != \"{:?}\"", + i, + m, + *rust_arg + ), + } + + let is_const = matches!( + mips_arg, + MsaTy::imm0_1 + | MsaTy::imm0_3 + | MsaTy::imm0_7 + | MsaTy::imm0_15 + | MsaTy::imm0_31 + | MsaTy::imm0_63 + | MsaTy::imm0_255 + | MsaTy::imm_n16_15 + | MsaTy::imm_n512_511 + | MsaTy::imm_n1024_1022 + | MsaTy::imm_n2048_2044 + | MsaTy::imm_n4096_4088 + ); + if is_const { + nconst += 1; + if !rust.required_const.contains(&i) { + bail!("argument const mismatch"); + } + } + } + + if nconst != rust.required_const.len() { + bail!("wrong number of const arguments"); + } + + if rust.target_feature != Some("msa") { + bail!("wrong target_feature"); + } + + if !rust.instrs.is_empty() { + // Normalize slightly to get rid of assembler differences + let actual = rust.instrs[0].replace(".", "_"); + let expected = mips.instruction.replace(".", "_"); + if actual != expected { + bail!( + "wrong instruction: \"{}\" != \"{}\"", + rust.instrs[0], + mips.instruction + ); + } + } else { + bail!( + "missing assert_instr for \"{}\" (should be \"{}\")", + mips.id, + mips.instruction + ); + } + + Ok(()) +} diff --git a/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs new file mode 100644 index 000000000..89494bfd2 --- /dev/null +++ b/library/stdarch/crates/stdarch-verify/tests/x86-intel.rs @@ -0,0 +1,841 @@ +#![allow(bad_style)] +#![allow(unused)] +#![allow( + clippy::shadow_reuse, + clippy::cast_lossless, + clippy::match_same_arms, + clippy::nonminimal_bool, + clippy::print_stdout, + clippy::use_debug, + clippy::eq_op, + clippy::useless_format +)] + +use std::collections::{BTreeMap, HashMap}; + +use serde::Deserialize; + +const PRINT_INSTRUCTION_VIOLATIONS: bool = false; +const PRINT_MISSING_LISTS: bool = false; +const PRINT_MISSING_LISTS_MARKDOWN: bool = false; + +struct Function { + name: &'static str, + arguments: &'static [&'static Type], + ret: Option<&'static Type>, + target_feature: Option<&'static str>, + instrs: &'static [&'static str], + file: &'static str, + required_const: &'static [usize], + has_test: bool, +} + +static F32: Type = Type::PrimFloat(32); +static F64: Type = Type::PrimFloat(64); +static I8: Type = Type::PrimSigned(8); +static I16: Type = Type::PrimSigned(16); +static I32: Type = Type::PrimSigned(32); +static I64: Type = Type::PrimSigned(64); +static U8: Type = Type::PrimUnsigned(8); +static U16: Type = Type::PrimUnsigned(16); +static U32: Type = Type::PrimUnsigned(32); +static U64: Type = Type::PrimUnsigned(64); +static U128: Type = Type::PrimUnsigned(128); +static ORDERING: Type = Type::Ordering; + +static M64: Type = Type::M64; +static M128: Type = Type::M128; +static M128BH: Type = Type::M128BH; +static M128I: Type = Type::M128I; +static M128D: Type = Type::M128D; +static M256: Type = Type::M256; +static M256BH: Type = Type::M256BH; +static M256I: Type = Type::M256I; +static M256D: Type = Type::M256D; +static M512: Type = Type::M512; +static M512BH: Type = Type::M512BH; +static M512I: Type = Type::M512I; +static M512D: Type = Type::M512D; +static MMASK8: Type = Type::MMASK8; +static MMASK16: Type = Type::MMASK16; +static MMASK32: Type = Type::MMASK32; +static MMASK64: Type = Type::MMASK64; +static MM_CMPINT_ENUM: Type = Type::MM_CMPINT_ENUM; +static MM_MANTISSA_NORM_ENUM: Type = Type::MM_MANTISSA_NORM_ENUM; +static MM_MANTISSA_SIGN_ENUM: Type = Type::MM_MANTISSA_SIGN_ENUM; +static MM_PERM_ENUM: Type = Type::MM_PERM_ENUM; + +static TUPLE: Type = Type::Tuple; +static CPUID: Type = Type::CpuidResult; +static NEVER: Type = Type::Never; + +#[derive(Debug)] +enum Type { + PrimFloat(u8), + PrimSigned(u8), + PrimUnsigned(u8), + MutPtr(&'static Type), + ConstPtr(&'static Type), + M64, + M128, + M128BH, + M128D, + M128I, + M256, + M256BH, + M256D, + M256I, + M512, + M512BH, + M512D, + M512I, + MMASK8, + MMASK16, + MMASK32, + MMASK64, + MM_CMPINT_ENUM, + MM_MANTISSA_NORM_ENUM, + MM_MANTISSA_SIGN_ENUM, + MM_PERM_ENUM, + Tuple, + CpuidResult, + Never, + Ordering, +} + +stdarch_verify::x86_functions!(static FUNCTIONS); + +#[derive(Deserialize)] +struct Data { + #[serde(rename = "intrinsic", default)] + intrinsics: Vec, +} + +#[derive(Deserialize)] +struct Intrinsic { + #[serde(rename = "return")] + return_: Return, + name: String, + #[serde(rename = "CPUID", default)] + cpuid: Vec, + #[serde(rename = "parameter", default)] + parameters: Vec, + #[serde(default)] + instruction: Vec, +} + +#[derive(Deserialize)] +struct Parameter { + #[serde(rename = "type")] + type_: String, + #[serde(default)] + etype: String, +} + +#[derive(Deserialize)] +struct Return { + #[serde(rename = "type")] + type_: String, +} + +#[derive(Deserialize, Debug)] +struct Instruction { + name: String, +} + +macro_rules! bail { + ($($t:tt)*) => (return Err(format!($($t)*))) +} + +#[test] +fn verify_all_signatures() { + // This XML document was downloaded from Intel's site. To update this you + // can visit intel's intrinsics guide online documentation: + // + // https://software.intel.com/sites/landingpage/IntrinsicsGuide/# + // + // Open up the network console and you'll see an xml file was downloaded + // (currently called data-3.4.xml). That's the file we downloaded + // here. + let xml = include_bytes!("../x86-intel.xml"); + + let xml = &xml[..]; + let data: Data = serde_xml_rs::from_reader(xml).expect("failed to deserialize xml"); + let mut map = HashMap::new(); + for intrinsic in &data.intrinsics { + map.entry(&intrinsic.name[..]) + .or_insert_with(Vec::new) + .push(intrinsic); + } + + let mut all_valid = true; + 'outer: for rust in FUNCTIONS { + if !rust.has_test { + // FIXME: this list should be almost empty + let skip = [ + "__readeflags", + "__readeflags", + "__writeeflags", + "__writeeflags", + "_mm_comige_ss", + "_mm_cvt_ss2si", + "_mm_cvtt_ss2si", + "_mm_cvt_si2ss", + "_mm_set_ps1", + "_mm_load_ps1", + "_mm_store_ps1", + "_mm_getcsr", + "_mm_setcsr", + "_MM_GET_EXCEPTION_MASK", + "_MM_GET_EXCEPTION_STATE", + "_MM_GET_FLUSH_ZERO_MODE", + "_MM_GET_ROUNDING_MODE", + "_MM_SET_EXCEPTION_MASK", + "_MM_SET_EXCEPTION_STATE", + "_MM_SET_FLUSH_ZERO_MODE", + "_MM_SET_ROUNDING_MODE", + "_mm_prefetch", + "_mm_undefined_ps", + "_m_pmaxsw", + "_m_pmaxub", + "_m_pminsw", + "_m_pminub", + "_m_pavgb", + "_m_pavgw", + "_m_psadbw", + "_mm_cvt_pi2ps", + "_m_maskmovq", + "_m_pextrw", + "_m_pinsrw", + "_m_pmovmskb", + "_m_pshufw", + "_mm_cvtt_ps2pi", + "_mm_cvt_ps2pi", + "__cpuid_count", + "__cpuid", + "__get_cpuid_max", + "_xsave", + "_xrstor", + "_xsetbv", + "_xgetbv", + "_xsaveopt", + "_xsavec", + "_xsaves", + "_xrstors", + "_mm_bslli_si128", + "_mm_bsrli_si128", + "_mm_undefined_pd", + "_mm_undefined_si128", + "_mm_cvtps_ph", + "_mm256_cvtps_ph", + "_rdtsc", + "__rdtscp", + "_mm256_castps128_ps256", + "_mm256_castpd128_pd256", + "_mm256_castsi128_si256", + "_mm256_undefined_ps", + "_mm256_undefined_pd", + "_mm256_undefined_si256", + "_bextr2_u32", + "_mm_tzcnt_32", + "_m_paddb", + "_m_paddw", + "_m_paddd", + "_m_paddsb", + "_m_paddsw", + "_m_paddusb", + "_m_paddusw", + "_m_psubb", + "_m_psubw", + "_m_psubd", + "_m_psubsb", + "_m_psubsw", + "_m_psubusb", + "_m_psubusw", + "_mm_set_pi16", + "_mm_set_pi32", + "_mm_set_pi8", + "_mm_set1_pi16", + "_mm_set1_pi32", + "_mm_set1_pi8", + "_mm_setr_pi16", + "_mm_setr_pi32", + "_mm_setr_pi8", + "ud2", + "_mm_min_epi8", + "_mm_min_epi32", + "_xbegin", + "_xend", + "_rdrand16_step", + "_rdrand32_step", + "_rdseed16_step", + "_rdseed32_step", + "_fxsave", + "_fxrstor", + "_t1mskc_u64", + "_mm256_shuffle_epi32", + "_mm256_bslli_epi128", + "_mm256_bsrli_epi128", + "_mm256_unpackhi_epi8", + "_mm256_unpacklo_epi8", + "_mm256_unpackhi_epi16", + "_mm256_unpacklo_epi16", + "_mm256_unpackhi_epi32", + "_mm256_unpacklo_epi32", + "_mm256_unpackhi_epi64", + "_mm256_unpacklo_epi64", + "_xsave64", + "_xrstor64", + "_xsaveopt64", + "_xsavec64", + "_xsaves64", + "_xrstors64", + "_mm_cvtsi64x_si128", + "_mm_cvtsi128_si64x", + "_mm_cvtsi64x_sd", + "cmpxchg16b", + "_rdrand64_step", + "_rdseed64_step", + "_bextr2_u64", + "_mm_tzcnt_64", + "_fxsave64", + "_fxrstor64", + "_mm512_undefined_ps", + "_mm512_undefined_pd", + "_mm512_undefined_epi32", + "_mm512_undefined", + ]; + if !skip.contains(&rust.name) { + println!( + "missing run-time test named `test_{}` for `{}`", + { + let mut id = rust.name; + while id.starts_with('_') { + id = &id[1..]; + } + id + }, + rust.name + ); + all_valid = false; + } + } + + match rust.name { + // These aren't defined by Intel but they're defined by what appears + // to be all other compilers. For more information see + // rust-lang/stdarch#307, and otherwise these signatures + // have all been manually verified. + "__readeflags" | + "__writeeflags" | + "__cpuid_count" | + "__cpuid" | + "__get_cpuid_max" | + // Not listed with intel, but manually verified + "cmpxchg16b" | + // The UD2 intrinsic is not defined by Intel, but it was agreed on + // in the RFC Issue 2512: + // https://github.com/rust-lang/rfcs/issues/2512 + "ud2" + => continue, + // Intel requires the mask argument for _mm_shuffle_ps to be an + // unsigned integer, but all other _mm_shuffle_.. intrinsics + // take a signed-integer. This breaks `_MM_SHUFFLE` for + // `_mm_shuffle_ps`: + "_mm_shuffle_ps" => continue, + _ => {} + } + + // these are all AMD-specific intrinsics + if let Some(feature) = rust.target_feature { + if feature.contains("sse4a") || feature.contains("tbm") { + continue; + } + } + + let intel = match map.remove(rust.name) { + Some(i) => i, + None => panic!("missing intel definition for {}", rust.name), + }; + + let mut errors = Vec::new(); + for intel in intel { + match matches(rust, intel) { + Ok(()) => continue 'outer, + Err(e) => errors.push(e), + } + } + println!("failed to verify `{}`", rust.name); + for error in errors { + println!(" * {}", error); + } + all_valid = false; + } + assert!(all_valid); + + let mut missing = BTreeMap::new(); + for (name, intel) in &map { + // currently focused mainly on missing SIMD intrinsics, but there's + // definitely some other assorted ones that we're missing. + if !name.starts_with("_mm") { + continue; + } + + // we'll get to avx-512 later + // let avx512 = intel.iter().any(|i| { + // i.name.starts_with("_mm512") || i.cpuid.iter().any(|c| { + // c.contains("512") + // }) + // }); + // if avx512 { + // continue + // } + + for intel in intel { + missing + .entry(&intel.cpuid) + .or_insert_with(Vec::new) + .push(intel); + } + } + + // generate a bulleted list of missing intrinsics + if PRINT_MISSING_LISTS || PRINT_MISSING_LISTS_MARKDOWN { + for (k, v) in missing { + if PRINT_MISSING_LISTS_MARKDOWN { + println!("\n

{:?}

\n", k); + for intel in v { + let url = format!( + "https://software.intel.com/sites/landingpage\ + /IntrinsicsGuide/#text={}&expand=5236", + intel.name + ); + println!(" * [ ] [`{}`]({})", intel.name, url); + } + println!("

\n"); + } else { + println!("\n{:?}\n", k); + for intel in v { + println!("\t{}", intel.name); + } + } + } + } +} + +fn matches(rust: &Function, intel: &Intrinsic) -> Result<(), String> { + // Verify that all `#[target_feature]` annotations are correct, + // ensuring that we've actually enabled the right instruction + // set for this intrinsic. + match rust.name { + "_bswap" | "_bswap64" => {} + + // These don't actually have a target feature unlike their brethren with + // the `x` inside the name which requires adx + "_addcarry_u32" | "_addcarry_u64" | "_subborrow_u32" | "_subborrow_u64" => {} + + "_bittest" + | "_bittestandset" + | "_bittestandreset" + | "_bittestandcomplement" + | "_bittest64" + | "_bittestandset64" + | "_bittestandreset64" + | "_bittestandcomplement64" => {} + + _ => { + if intel.cpuid.is_empty() { + bail!("missing cpuid for {}", rust.name); + } + } + } + + for cpuid in &intel.cpuid { + // The pause intrinsic is in the SSE2 module, but it is backwards + // compatible with CPUs without SSE2, and it therefore does not need the + // target-feature attribute. + if rust.name == "_mm_pause" { + continue; + } + // this is needed by _xsave and probably some related intrinsics, + // but let's just skip it for now. + if *cpuid == "XSS" { + continue; + } + + // these flags on the rdtsc/rtdscp intrinsics we don't test for right + // now, but we may wish to add these one day! + // + // For more info see #308 + if *cpuid == "TSC" || *cpuid == "RDTSCP" { + continue; + } + + let cpuid = cpuid + .chars() + .flat_map(|c| c.to_lowercase()) + .collect::(); + + // Fix mismatching feature names: + let fixup_cpuid = |cpuid: String| match cpuid.as_ref() { + // The XML file names IFMA as "avx512ifma52", while Rust calls + // it "avx512ifma". + "avx512ifma52" => String::from("avx512ifma"), + // The XML file names BITALG as "avx512_bitalg", while Rust calls + // it "avx512bitalg". + "avx512_bitalg" => String::from("avx512bitalg"), + // The XML file names VBMI as "avx512_vbmi", while Rust calls + // it "avx512vbmi". + "avx512_vbmi" => String::from("avx512vbmi"), + // The XML file names VBMI2 as "avx512_vbmi2", while Rust calls + // it "avx512vbmi2". + "avx512_vbmi2" => String::from("avx512vbmi2"), + // The XML file names VNNI as "avx512_vnni", while Rust calls + // it "avx512vnni". + "avx512_vnni" => String::from("avx512vnni"), + // Some AVX512f intrinsics are also supported by Knight's Corner. + // The XML lists them as avx512f/kncni, but we are solely gating + // them behind avx512f since we don't have a KNC feature yet. + "avx512f/kncni" => String::from("avx512f"), + // See: https://github.com/rust-lang/stdarch/issues/738 + // The intrinsics guide calls `f16c` `fp16c` in disagreement with + // Intel's architecture manuals. + "fp16c" => String::from("f16c"), + "avx512_bf16" => String::from("avx512bf16"), + // The XML file names VNNI as "avx512_bf16", while Rust calls + // it "avx512bf16". + _ => cpuid, + }; + let fixed_cpuid = fixup_cpuid(cpuid); + + let rust_feature = rust + .target_feature + .unwrap_or_else(|| panic!("no target feature listed for {}", rust.name)); + + if rust_feature.contains(&fixed_cpuid) { + continue; + } + bail!( + "intel cpuid `{}` not in `{}` for {}", + fixed_cpuid, + rust_feature, + rust.name + ) + } + + if PRINT_INSTRUCTION_VIOLATIONS { + if rust.instrs.is_empty() { + if !intel.instruction.is_empty() { + println!( + "instruction not listed for `{}`, but intel lists {:?}", + rust.name, intel.instruction + ); + } + + // If intel doesn't list any instructions and we do then don't + // bother trying to look for instructions in intel, we've just got + // some extra assertions on our end. + } else if !intel.instruction.is_empty() { + for instr in rust.instrs { + let asserting = intel.instruction.iter().any(|a| a.name.starts_with(instr)); + if !asserting { + println!( + "intel failed to list `{}` as an instruction for `{}`", + instr, rust.name + ); + } + } + } + } + + // Make sure we've got the right return type. + if let Some(t) = rust.ret { + equate(t, &intel.return_.type_, "", rust.name, false)?; + } else if intel.return_.type_ != "" && intel.return_.type_ != "void" { + bail!( + "{} returns `{}` with intel, void in rust", + rust.name, + intel.return_.type_ + ) + } + + // If there's no arguments on Rust's side intel may list one "void" + // argument, so handle that here. + if rust.arguments.is_empty() && intel.parameters.len() == 1 { + if intel.parameters[0].type_ != "void" { + bail!("rust has 0 arguments, intel has one for") + } + } else { + // Otherwise we want all parameters to be exactly the same + if rust.arguments.len() != intel.parameters.len() { + bail!("wrong number of arguments on {}", rust.name) + } + for (i, (a, b)) in intel.parameters.iter().zip(rust.arguments).enumerate() { + let is_const = rust.required_const.contains(&i); + equate(b, &a.type_, &a.etype, &intel.name, is_const)?; + } + } + + let any_i64 = rust + .arguments + .iter() + .cloned() + .chain(rust.ret) + .any(|arg| matches!(*arg, Type::PrimSigned(64) | Type::PrimUnsigned(64))); + let any_i64_exempt = match rust.name { + // These intrinsics have all been manually verified against Clang's + // headers to be available on x86, and the u64 arguments seem + // spurious I guess? + "_xsave" | "_xrstor" | "_xsetbv" | "_xgetbv" | "_xsaveopt" | "_xsavec" | "_xsaves" + | "_xrstors" => true, + + // Apparently all of clang/msvc/gcc accept these intrinsics on + // 32-bit, so let's do the same + "_mm_set_epi64x" + | "_mm_set1_epi64x" + | "_mm256_set_epi64x" + | "_mm256_setr_epi64x" + | "_mm256_set1_epi64x" + | "_mm512_set1_epi64" + | "_mm256_mask_set1_epi64" + | "_mm256_maskz_set1_epi64" + | "_mm_mask_set1_epi64" + | "_mm_maskz_set1_epi64" + | "_mm512_set4_epi64" + | "_mm512_setr4_epi64" + | "_mm512_set_epi64" + | "_mm512_setr_epi64" + | "_mm512_reduce_add_epi64" + | "_mm512_mask_reduce_add_epi64" + | "_mm512_reduce_mul_epi64" + | "_mm512_mask_reduce_mul_epi64" + | "_mm512_reduce_max_epi64" + | "_mm512_mask_reduce_max_epi64" + | "_mm512_reduce_max_epu64" + | "_mm512_mask_reduce_max_epu64" + | "_mm512_reduce_min_epi64" + | "_mm512_mask_reduce_min_epi64" + | "_mm512_reduce_min_epu64" + | "_mm512_mask_reduce_min_epu64" + | "_mm512_reduce_and_epi64" + | "_mm512_mask_reduce_and_epi64" + | "_mm512_reduce_or_epi64" + | "_mm512_mask_reduce_or_epi64" + | "_mm512_mask_set1_epi64" + | "_mm512_maskz_set1_epi64" + | "_mm_cvt_roundss_si64" + | "_mm_cvt_roundss_i64" + | "_mm_cvt_roundss_u64" + | "_mm_cvtss_i64" + | "_mm_cvtss_u64" + | "_mm_cvt_roundsd_si64" + | "_mm_cvt_roundsd_i64" + | "_mm_cvt_roundsd_u64" + | "_mm_cvtsd_i64" + | "_mm_cvtsd_u64" + | "_mm_cvt_roundi64_ss" + | "_mm_cvt_roundi64_sd" + | "_mm_cvt_roundsi64_ss" + | "_mm_cvt_roundsi64_sd" + | "_mm_cvt_roundu64_ss" + | "_mm_cvt_roundu64_sd" + | "_mm_cvti64_ss" + | "_mm_cvti64_sd" + | "_mm_cvtt_roundss_si64" + | "_mm_cvtt_roundss_i64" + | "_mm_cvtt_roundss_u64" + | "_mm_cvttss_i64" + | "_mm_cvttss_u64" + | "_mm_cvtt_roundsd_si64" + | "_mm_cvtt_roundsd_i64" + | "_mm_cvtt_roundsd_u64" + | "_mm_cvttsd_i64" + | "_mm_cvttsd_u64" + | "_mm_cvtu64_ss" + | "_mm_cvtu64_sd" => true, + + // These return a 64-bit argument but they're assembled from other + // 32-bit registers, so these work on 32-bit just fine. See #308 for + // more info. + "_rdtsc" | "__rdtscp" => true, + + _ => false, + }; + if any_i64 && !any_i64_exempt && !rust.file.contains("x86_64") { + bail!( + "intrinsic `{}` uses a 64-bit bare type but may be \ + available on 32-bit platforms", + rust.name + ) + } + Ok(()) +} + +fn equate( + t: &Type, + intel: &str, + etype: &str, + intrinsic: &str, + is_const: bool, +) -> Result<(), String> { + // Make pointer adjacent to the type: float * foo => float* foo + let mut intel = intel.replace(" *", "*"); + // Make mutability modifier adjacent to the pointer: + // float const * foo => float const* foo + intel = intel.replace("const *", "const*"); + // Normalize mutability modifier to after the type: + // const float* foo => float const* + if intel.starts_with("const") && intel.ends_with('*') { + intel = intel.replace("const ", ""); + intel = intel.replace("*", " const*"); + } + if etype == "IMM" { + // The _bittest intrinsics claim to only accept immediates but actually + // accept run-time values as well. + if !is_const && !intrinsic.starts_with("_bittest") { + return bail!("argument required to be const but isn't"); + } + } else { + // const int must be an IMM + assert_ne!(intel, "const int"); + if is_const { + return bail!("argument is const but shouldn't be"); + } + } + match (t, &intel[..]) { + (&Type::PrimFloat(32), "float") => {} + (&Type::PrimFloat(64), "double") => {} + (&Type::PrimSigned(16), "__int16") => {} + (&Type::PrimSigned(16), "short") => {} + (&Type::PrimSigned(32), "__int32") => {} + (&Type::PrimSigned(32), "const int") => {} + (&Type::PrimSigned(32), "int") => {} + (&Type::PrimSigned(64), "__int64") => {} + (&Type::PrimSigned(64), "long long") => {} + (&Type::PrimSigned(8), "__int8") => {} + (&Type::PrimSigned(8), "char") => {} + (&Type::PrimUnsigned(16), "unsigned short") => {} + (&Type::PrimUnsigned(32), "unsigned int") => {} + (&Type::PrimUnsigned(32), "const unsigned int") => {} + (&Type::PrimUnsigned(64), "unsigned __int64") => {} + (&Type::PrimUnsigned(8), "unsigned char") => {} + (&Type::M64, "__m64") => {} + (&Type::M128, "__m128") => {} + (&Type::M128BH, "__m128bh") => {} + (&Type::M128I, "__m128i") => {} + (&Type::M128D, "__m128d") => {} + (&Type::M256, "__m256") => {} + (&Type::M256BH, "__m256bh") => {} + (&Type::M256I, "__m256i") => {} + (&Type::M256D, "__m256d") => {} + (&Type::M512, "__m512") => {} + (&Type::M512BH, "__m512bh") => {} + (&Type::M512I, "__m512i") => {} + (&Type::M512D, "__m512d") => {} + (&Type::MMASK64, "__mmask64") => {} + (&Type::MMASK32, "__mmask32") => {} + (&Type::MMASK16, "__mmask16") => {} + (&Type::MMASK8, "__mmask8") => {} + + (&Type::MutPtr(&Type::PrimFloat(32)), "float*") => {} + (&Type::MutPtr(&Type::PrimFloat(64)), "double*") => {} + (&Type::MutPtr(&Type::PrimFloat(32)), "void*") => {} + (&Type::MutPtr(&Type::PrimFloat(64)), "void*") => {} + (&Type::MutPtr(&Type::PrimSigned(32)), "void*") => {} + (&Type::MutPtr(&Type::PrimSigned(16)), "void*") => {} + (&Type::MutPtr(&Type::PrimSigned(8)), "void*") => {} + (&Type::MutPtr(&Type::PrimSigned(32)), "int*") => {} + (&Type::MutPtr(&Type::PrimSigned(32)), "__int32*") => {} + (&Type::MutPtr(&Type::PrimSigned(64)), "void*") => {} + (&Type::MutPtr(&Type::PrimSigned(64)), "__int64*") => {} + (&Type::MutPtr(&Type::PrimSigned(8)), "char*") => {} + (&Type::MutPtr(&Type::PrimUnsigned(16)), "unsigned short*") => {} + (&Type::MutPtr(&Type::PrimUnsigned(32)), "unsigned int*") => {} + (&Type::MutPtr(&Type::PrimUnsigned(64)), "unsigned __int64*") => {} + (&Type::MutPtr(&Type::PrimUnsigned(8)), "void*") => {} + (&Type::MutPtr(&Type::PrimUnsigned(32)), "__mmask32*") => {} + (&Type::MutPtr(&Type::PrimUnsigned(64)), "__mmask64*") => {} + (&Type::MutPtr(&Type::M64), "__m64*") => {} + (&Type::MutPtr(&Type::M128), "__m128*") => {} + (&Type::MutPtr(&Type::M128BH), "__m128bh*") => {} + (&Type::MutPtr(&Type::M128I), "__m128i*") => {} + (&Type::MutPtr(&Type::M128D), "__m128d*") => {} + (&Type::MutPtr(&Type::M256), "__m256*") => {} + (&Type::MutPtr(&Type::M256BH), "__m256bh*") => {} + (&Type::MutPtr(&Type::M256I), "__m256i*") => {} + (&Type::MutPtr(&Type::M256D), "__m256d*") => {} + (&Type::MutPtr(&Type::M512), "__m512*") => {} + (&Type::MutPtr(&Type::M512BH), "__m512bh*") => {} + (&Type::MutPtr(&Type::M512I), "__m512i*") => {} + (&Type::MutPtr(&Type::M512D), "__m512d*") => {} + + (&Type::ConstPtr(&Type::PrimFloat(32)), "float const*") => {} + (&Type::ConstPtr(&Type::PrimFloat(64)), "double const*") => {} + (&Type::ConstPtr(&Type::PrimFloat(32)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimFloat(64)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(32)), "int const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(32)), "__int32 const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(8)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(16)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(32)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(64)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(64)), "__int64 const*") => {} + (&Type::ConstPtr(&Type::PrimSigned(8)), "char const*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(16)), "unsigned short const*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(32)), "unsigned int const*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(64)), "unsigned __int64 const*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(8)), "void const*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(32)), "void const*") => {} + (&Type::ConstPtr(&Type::M64), "__m64 const*") => {} + (&Type::ConstPtr(&Type::M128), "__m128 const*") => {} + (&Type::ConstPtr(&Type::M128BH), "__m128bh const*") => {} + (&Type::ConstPtr(&Type::M128I), "__m128i const*") => {} + (&Type::ConstPtr(&Type::M128D), "__m128d const*") => {} + (&Type::ConstPtr(&Type::M256), "__m256 const*") => {} + (&Type::ConstPtr(&Type::M256BH), "__m256bh const*") => {} + (&Type::ConstPtr(&Type::M256I), "__m256i const*") => {} + (&Type::ConstPtr(&Type::M256D), "__m256d const*") => {} + (&Type::ConstPtr(&Type::M512), "__m512 const*") => {} + (&Type::ConstPtr(&Type::M512BH), "__m512bh const*") => {} + (&Type::ConstPtr(&Type::M512I), "__m512i const*") => {} + (&Type::ConstPtr(&Type::M512D), "__m512d const*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(32)), "__mmask32*") => {} + (&Type::ConstPtr(&Type::PrimUnsigned(64)), "__mmask64*") => {} + + (&Type::MM_CMPINT_ENUM, "_MM_CMPINT_ENUM") => {} + (&Type::MM_MANTISSA_NORM_ENUM, "_MM_MANTISSA_NORM_ENUM") => {} + (&Type::MM_MANTISSA_SIGN_ENUM, "_MM_MANTISSA_SIGN_ENUM") => {} + (&Type::MM_PERM_ENUM, "_MM_PERM_ENUM") => {} + + // This is a macro (?) in C which seems to mutate its arguments, but + // that means that we're taking pointers to arguments in rust + // as we're not exposing it as a macro. + (&Type::MutPtr(&Type::M128), "__m128") if intrinsic == "_MM_TRANSPOSE4_PS" => {} + + // The _rdtsc intrinsic uses a __int64 return type, but this is a bug in + // the intrinsics guide: https://github.com/rust-lang/stdarch/issues/559 + // We have manually fixed the bug by changing the return type to `u64`. + (&Type::PrimUnsigned(64), "__int64") if intrinsic == "_rdtsc" => {} + + // The _bittest and _bittest64 intrinsics takes a mutable pointer in the + // intrinsics guide even though it never writes through the pointer: + (&Type::ConstPtr(&Type::PrimSigned(32)), "__int32*") if intrinsic == "_bittest" => {} + (&Type::ConstPtr(&Type::PrimSigned(64)), "__int64*") if intrinsic == "_bittest64" => {} + // The _xrstor, _fxrstor, _xrstor64, _fxrstor64 intrinsics take a + // mutable pointer in the intrinsics guide even though they never write + // through the pointer: + (&Type::ConstPtr(&Type::PrimUnsigned(8)), "void*") + if intrinsic == "_xrstor" + || intrinsic == "_xrstor64" + || intrinsic == "_fxrstor" + || intrinsic == "_fxrstor64" => {} + + _ => bail!( + "failed to equate: `{}` and {:?} for {}", + intel, + t, + intrinsic + ), + } + Ok(()) +} diff --git a/library/stdarch/crates/stdarch-verify/x86-intel.xml b/library/stdarch/crates/stdarch-verify/x86-intel.xml new file mode 100644 index 000000000..264ecee0e --- /dev/null +++ b/library/stdarch/crates/stdarch-verify/x86-intel.xml @@ -0,0 +1,148137 @@ + + + Integer + Flag + ADX + Arithmetic + + + + + + Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag). + +tmp[32:0] := a[31:0] + b[31:0] + (c_in > 0 ? 1 : 0) +MEM[out+31:out] := tmp[31:0] +dst[0] := tmp[32] +dst[7:1] := 0 + + + +

immintrin.h

+ + + Integer + Flag + ADX + Arithmetic + + + + + + Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry or overflow flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag). + +tmp[64:0] := a[63:0] + b[63:0] + (c_in > 0 ? 1 : 0) +MEM[out+63:out] := tmp[63:0] +dst[0] := tmp[64] +dst[7:1] := 0 + + + +

immintrin.h

+ + + Integer + AES + Cryptography + + + + Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"." + a[127:0] := ShiftRows(a[127:0]) +a[127:0] := SubBytes(a[127:0]) +a[127:0] := MixColumns(a[127:0]) +dst[127:0] := a[127:0] XOR RoundKey[127:0] + + +

wmmintrin.h

+ + + Integer + AES + Cryptography + + + + Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst"." + a[127:0] := ShiftRows(a[127:0]) +a[127:0] := SubBytes(a[127:0]) +dst[127:0] := a[127:0] XOR RoundKey[127:0] + + +

wmmintrin.h

+ + + Integer + AES + Cryptography + + + + Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst". + a[127:0] := InvShiftRows(a[127:0]) +a[127:0] := InvSubBytes(a[127:0]) +a[127:0] := InvMixColumns(a[127:0]) +dst[127:0] := a[127:0] XOR RoundKey[127:0] + + +

wmmintrin.h

+ + + Integer + AES + Cryptography + + + + Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the result in "dst". + a[127:0] := InvShiftRows(a[127:0]) +a[127:0] := InvSubBytes(a[127:0]) +dst[127:0] := a[127:0] XOR RoundKey[127:0] + + +

wmmintrin.h

+ + + Integer + AES + Cryptography + + + Perform the InvMixColumns transformation on "a" and store the result in "dst". + dst[127:0] := InvMixColumns(a[127:0]) + + +

wmmintrin.h

+ + + Integer + AES + Cryptography + + + + Assist in expanding the AES cipher key by computing steps towards generating a round key for encryption cipher using data from "a" and an 8-bit round constant specified in "imm8", and store the result in "dst"." + X3[31:0] := a[127:96] +X2[31:0] := a[95:64] +X1[31:0] := a[63:32] +X0[31:0] := a[31:0] +RCON[31:0] := ZeroExtend32(imm8[7:0]) +dst[31:0] := SubWord(X1) +dst[63:32] := RotWord(SubWord(X1)) XOR RCON +dst[95:64] := SubWord(X3) +dst[127:96] := RotWord(SubWord(X3)) XOR RCON + + +

wmmintrin.h

+ + + Tile + Floating Point + AMXBF16 + Application-Targeted + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in tiles "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "dst", and store the 32-bit result back to tile "dst". + FOR m := 0 TO dst.rows - 1 + tmp := dst.row[m] + FOR k := 0 TO (a.colsb / 4) - 1 + FOR n := 0 TO (dst.colsb / 4) - 1 + tmp.fp32[n] += FP32(a.row[m].bf16[2*k+0]) * FP32(b.row[k].bf16[2*n+0]) + tmp.fp32[n] += FP32(a.row[m].bf16[2*k+1]) * FP32(b.row[k].bf16[2*n+1]) + ENDFOR + ENDFOR + write_row_and_zero(dst, m, tmp, dst.colsb) +ENDFOR +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXINT8 + Application-Targeted + + + + + Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "a" with corresponding unsigned 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". + DEFINE DPBD(c, x, y) { + tmp1 := SignExtend32(x.byte[0]) * ZeroExtend32(y.byte[0]) + tmp2 := SignExtend32(x.byte[1]) * ZeroExtend32(y.byte[1]) + tmp3 := SignExtend32(x.byte[2]) * ZeroExtend32(y.byte[2]) + tmp4 := SignExtend32(x.byte[3]) * ZeroExtend32(y.byte[3]) + + RETURN c + tmp1 + tmp2 + tmp3 + tmp4 +} +FOR m := 0 TO dst.rows - 1 + tmp := dst.row[m] + FOR k := 0 TO (a.colsb / 4) - 1 + FOR n := 0 TO (dst.colsb / 4) - 1 + tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n]) + ENDFOR + ENDFOR + write_row_and_zero(dst, m, tmp, dst.colsb) +ENDFOR +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXINT8 + Application-Targeted + + + + + Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". + DEFINE DPBD(c, x, y) { + tmp1 := ZeroExtend32(x.byte[0]) * SignExtend32(y.byte[0]) + tmp2 := ZeroExtend32(x.byte[1]) * SignExtend32(y.byte[1]) + tmp3 := ZeroExtend32(x.byte[2]) * SignExtend32(y.byte[2]) + tmp4 := ZeroExtend32(x.byte[3]) * SignExtend32(y.byte[3]) + + RETURN c + tmp1 + tmp2 + tmp3 + tmp4 +} +FOR m := 0 TO dst.rows - 1 + tmp := dst.row[m] + FOR k := 0 TO (a.colsb / 4) - 1 + FOR n := 0 TO (dst.colsb / 4) - 1 + tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n]) + ENDFOR + ENDFOR + write_row_and_zero(dst, m, tmp, dst.colsb) +ENDFOR +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXINT8 + Application-Targeted + + + + + Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding unsigned 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". + DEFINE DPBD(c, x, y) { + tmp1 := ZeroExtend32(x.byte[0]) * ZeroExtend32(y.byte[0]) + tmp2 := ZeroExtend32(x.byte[1]) * ZeroExtend32(y.byte[1]) + tmp3 := ZeroExtend32(x.byte[2]) * ZeroExtend32(y.byte[2]) + tmp4 := ZeroExtend32(x.byte[3]) * ZeroExtend32(y.byte[3]) + + RETURN c + tmp1 + tmp2 + tmp3 + tmp4 +} +FOR m := 0 TO dst.rows - 1 + tmp := dst.row[m] + FOR k := 0 TO (a.colsb / 4) - 1 + FOR n := 0 TO (dst.colsb / 4) - 1 + tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n]) + ENDFOR + ENDFOR + write_row_and_zero(dst, m, tmp, dst.colsb) +ENDFOR +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXINT8 + Application-Targeted + + + + + Compute dot-product of bytes in tiles with a source/destination accumulator. Multiply groups of 4 adjacent pairs of signed 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate 32-bit results. Sum these 4 results with the corresponding 32-bit integer in "dst", and store the 32-bit result back to tile "dst". + DEFINE DPBD(c, x, y) { + tmp1 := SignExtend32(x.byte[0]) * SignExtend32(y.byte[0]) + tmp2 := SignExtend32(x.byte[1]) * SignExtend32(y.byte[1]) + tmp3 := SignExtend32(x.byte[2]) * SignExtend32(y.byte[2]) + tmp4 := SignExtend32(x.byte[3]) * SignExtend32(y.byte[3]) + + RETURN c + tmp1 + tmp2 + tmp3 + tmp4 +} +FOR m := 0 TO dst.rows - 1 + tmp := dst.row[m] + FOR k := 0 TO (a.colsb / 4) - 1 + FOR n := 0 TO (dst.colsb / 4) - 1 + tmp.dword[n] := DPBD(tmp.dword[n], a.row[m].dword[k], b.row[k].dword[n]) + ENDFOR + ENDFOR + write_row_and_zero(dst, m, tmp, dst.colsb) +ENDFOR +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + + Load tile configuration from a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If the specified pallette_id is zero, that signifies the init state for both the tile config and the tile data, and the tiles are zeroed. Any invalid configurations will result in #GP fault. + +// format of memory payload. each field is a byte. +// 0: palette_id +// 1: startRow (8b) +// 2-15: reserved (must be zero) +// 16-17: tile0.colsb -- bytes_per_row +// 18-19: tile1.colsb +// 20-21: tile2.colsb +// ... +// 46-47: tile15.colsb +// 48: tile0.rows +// 49: tile1.rows +// 50: tile2.rows +// ... +// 63: tile15.rows + + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + + Stores the current tile configuration to a 64-byte memory location specified by "mem_addr". The tile configuration format is specified below, and includes the tile type pallette, the number of bytes per row, and the number of rows. If tiles are not configured, all zeroes will be stored to memory. + +// format of memory payload. each field is a byte. +// 0: palette_id +// 1: startRow (8b) +// 2-15: reserved (must be zero) +// 16-17: tile0.colsb -- bytes_per_row +// 18-19: tile1.colsb +// 20-21: tile2.colsb +// ... +// 46-47: tile15.colsb +// 48: tile0.rows +// 49: tile1.rows +// 50: tile2.rows +// ... +// 63: tile15.rows + + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + + + + Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst" using the tile configuration previously configured via "_tile_loadconfig". + start := tileconfig.startRow +IF start == 0 // not restarting, zero incoming state + tilezero(dst) +FI +nbytes := dst.colsb +DO WHILE start < dst.rows + memptr := base + start * stride + write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes) + start := start + 1 +OD +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + + + + Load tile rows from memory specifieid by "base" address and "stride" into destination tile "dst" using the tile configuration previously configured via "_tile_loadconfig". This intrinsic provides a hint to the implementation that the data will likely not be reused in the near future and the data caching can be optimized accordingly. + start := tileconfig.startRow +IF start == 0 // not restarting, zero incoming state + tilezero(dst) +FI +nbytes := dst.colsb +DO WHILE start < dst.rows + memptr := base + start * stride + write_row_and_zero(dst, start, read_memory(memptr, nbytes), nbytes) + start := start + 1 +OD +zero_upper_rows(dst, dst.rows) +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + Release the tile configuration to return to the init state, which releases all storage it currently holds. + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + + + + Store the tile specified by "src" to memory specifieid by "base" address and "stride" using the tile configuration previously configured via "_tile_loadconfig". + start := tileconfig.startRow +DO WHILE start < src.rows + memptr := base + start * stride + write_memory(memptr, src.colsb, src.row[start]) + start := start + 1 +OD +zero_tileconfig_start() + + +

immintrin.h

+ + + Tile + AMXTILE + Application-Targeted + + + Zero the tile specified by "tdest". + nbytes := palette_table[tileconfig.palette_id].bytes_per_row +FOR i := 0 TO palette_table[tileconfig.palette_id].max_rows-1 + FOR j := 0 TO nbytes-1 + tdest.row[i].byte[j] := 0 + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + b[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + b[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF imm8[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF imm8[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF mask[i+63] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF mask[i+31] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + dst[i+63:i] := a[i+63:i] / b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := a[i+31:i] / b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + + Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8". + +DEFINE DP(a[127:0], b[127:0], imm8[7:0]) { + FOR j := 0 to 3 + i := j*32 + IF imm8[(4+j)%8] + temp[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + temp[i+31:i] := FP32(0.0) + FI + ENDFOR + + sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0]) + + FOR j := 0 to 3 + i := j*32 + IF imm8[j%8] + tmpdst[i+31:i] := sum[31:0] + ELSE + tmpdst[i+31:i] := FP32(0.0) + FI + ENDFOR + RETURN tmpdst[127:0] +} +dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0]) +dst[255:128] := DP(a[255:128], b[255:128], imm8[7:0]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[63:0] := a[127:64] + a[63:0] +dst[127:64] := b[127:64] + b[63:0] +dst[191:128] := a[255:192] + a[191:128] +dst[255:192] := b[255:192] + b[191:128] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[31:0] := a[63:32] + a[31:0] +dst[63:32] := a[127:96] + a[95:64] +dst[95:64] := b[63:32] + b[31:0] +dst[127:96] := b[127:96] + b[95:64] +dst[159:128] := a[191:160] + a[159:128] +dst[191:160] := a[255:224] + a[223:192] +dst[223:192] := b[191:160] + b[159:128] +dst[255:224] := b[255:224] + b[223:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[63:0] := a[63:0] - a[127:64] +dst[127:64] := b[63:0] - b[127:64] +dst[191:128] := a[191:128] - a[255:192] +dst[255:192] := b[191:128] - b[255:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[31:0] := a[31:0] - a[63:32] +dst[63:32] := a[95:64] - a[127:96] +dst[95:64] := b[31:0] - b[63:32] +dst[127:96] := b[95:64] - b[127:96] +dst[159:128] := a[159:128] - a[191:160] +dst[191:160] := a[223:192] - a[255:224] +dst[223:192] := b[159:128] - b[191:160] +dst[255:224] := b[223:192] - b[255:224] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] * b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] * b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] OR b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] OR b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst". + +dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192] +dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +dst[223:192] := SELECT4(b[255:128], imm8[5:4]) +dst[255:224] := SELECT4(b[255:128], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Arithmetic + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Logical + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ( a[i+63:i] OP b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in "dst". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ( a[i+31:i] OP b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Compare + + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +dst[63:0] := ( a[63:0] OP b[63:0] ) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Compare + + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +dst[31:0] := ( a[31:0] OP b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX + Convert + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + m := j*64 + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX + Convert + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 32*j + dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + Extract a 32-bit integer from "a", selected with "index", and store the result in "dst". + +dst[31:0] := (a[255:0] >> (index[2:0] * 32))[31:0] + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + Extract a 64-bit integer from "a", selected with "index", and store the result in "dst". + +dst[63:0] := (a[255:0] >> (index[1:0] * 64))[63:0] + +

immintrin.h

+ + + AVX + General Support + + + Zero the contents of all XMM or YMM registers. + YMM0[MAX:0] := 0 +YMM1[MAX:0] := 0 +YMM2[MAX:0] := 0 +YMM3[MAX:0] := 0 +YMM4[MAX:0] := 0 +YMM5[MAX:0] := 0 +YMM6[MAX:0] := 0 +YMM7[MAX:0] := 0 +IF _64_BIT_MODE + YMM8[MAX:0] := 0 + YMM9[MAX:0] := 0 + YMM10[MAX:0] := 0 + YMM11[MAX:0] := 0 + YMM12[MAX:0] := 0 + YMM13[MAX:0] := 0 + YMM14[MAX:0] := 0 + YMM15[MAX:0] := 0 +FI + + +

immintrin.h

+ + + AVX + General Support + + + Zero the upper 128 bits of all YMM registers; the lower 128-bits of the registers are unmodified. + YMM0[MAX:128] := 0 +YMM1[MAX:128] := 0 +YMM2[MAX:128] := 0 +YMM3[MAX:128] := 0 +YMM4[MAX:128] := 0 +YMM5[MAX:128] := 0 +YMM6[MAX:128] := 0 +YMM7[MAX:128] := 0 +IF _64_BIT_MODE + YMM8[MAX:128] := 0 + YMM9[MAX:128] := 0 + YMM10[MAX:128] := 0 + YMM11[MAX:128] := 0 + YMM12[MAX:128] := 0 + YMM13[MAX:128] := 0 + YMM14[MAX:128] := 0 + YMM15[MAX:128] := 0 +FI + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], b[1:0]) +dst[63:32] := SELECT4(a[127:0], b[33:32]) +dst[95:64] := SELECT4(a[127:0], b[65:64]) +dst[127:96] := SELECT4(a[127:0], b[97:96]) +dst[159:128] := SELECT4(a[255:128], b[129:128]) +dst[191:160] := SELECT4(a[255:128], b[161:160]) +dst[223:192] := SELECT4(a[255:128], b[193:192]) +dst[255:224] := SELECT4(a[255:128], b[225:224]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], b[1:0]) +dst[63:32] := SELECT4(a[127:0], b[33:32]) +dst[95:64] := SELECT4(a[127:0], b[65:64]) +dst[127:96] := SELECT4(a[127:0], b[97:96]) +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst". + +IF (b[1] == 0) dst[63:0] := a[63:0]; FI +IF (b[1] == 1) dst[63:0] := a[127:64]; FI +IF (b[65] == 0) dst[127:64] := a[63:0]; FI +IF (b[65] == 1) dst[127:64] := a[127:64]; FI +IF (b[129] == 0) dst[191:128] := a[191:128]; FI +IF (b[129] == 1) dst[191:128] := a[255:192]; FI +IF (b[193] == 0) dst[255:192] := a[191:128]; FI +IF (b[193] == 1) dst[255:192] := a[255:192]; FI +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst". + +IF (b[1] == 0) dst[63:0] := a[63:0]; FI +IF (b[1] == 1) dst[63:0] := a[127:64]; FI +IF (b[65] == 0) dst[127:64] := a[63:0]; FI +IF (b[65] == 1) dst[127:64] := a[127:64]; FI +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI +IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI +IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI +IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI +IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst". + +IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Shuffle 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src1, src2, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src1[127:0] + 1: tmp[127:0] := src1[255:128] + 2: tmp[127:0] := src2[127:0] + 3: tmp[127:0] := src2[255:128] + ESAC + IF control[3] + tmp[127:0] := 0 + FI + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0]) +dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Shuffle 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src1, src2, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src1[127:0] + 1: tmp[127:0] := src1[255:128] + 2: tmp[127:0] := src2[127:0] + 3: tmp[127:0] := src2[255:128] + ESAC + IF control[3] + tmp[127:0] := 0 + FI + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0]) +dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + + Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src1, src2, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src1[127:0] + 1: tmp[127:0] := src1[255:128] + 2: tmp[127:0] := src2[127:0] + 3: tmp[127:0] := src2[255:128] + ESAC + IF control[3] + tmp[127:0] := 0 + FI + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0]) +dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst". + +tmp[31:0] := MEM[mem_addr+31:mem_addr] +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := tmp[31:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Load + Swizzle + + + Broadcast a single-precision (32-bit) floating-point element from memory to all elements of "dst". + +tmp[31:0] := MEM[mem_addr+31:mem_addr] +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := tmp[31:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Load + Swizzle + + + Broadcast a double-precision (64-bit) floating-point element from memory to all elements of "dst". + +tmp[63:0] := MEM[mem_addr+63:mem_addr] +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := tmp[63:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Load + Swizzle + + + Broadcast 128 bits from memory (composed of 4 packed single-precision (32-bit) floating-point elements) to all elements of "dst". + +tmp[127:0] := MEM[mem_addr+127:mem_addr] +dst[127:0] := tmp[127:0] +dst[255:128] := tmp[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Load + Swizzle + + + Broadcast 128 bits from memory (composed of 2 packed double-precision (64-bit) floating-point elements) to all elements of "dst". + +tmp[127:0] := MEM[mem_addr+127:mem_addr] +dst[127:0] := tmp[127:0] +dst[255:128] := tmp[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE (imm8[0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + + Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE imm8[0] OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + + Copy "a" to "dst", then insert 128 bits from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE (imm8[0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + + Copy "a" to "dst", and insert the 8-bit integer "i" into "dst" at the location specified by "index". + +dst[255:0] := a[255:0] +sel := index[4:0]*8 +dst[sel+7:sel] := i[7:0] + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + + Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "index". + +dst[255:0] := a[255:0] +sel := index[3:0]*16 +dst[sel+15:sel] := i[15:0] + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + + Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "index". + +dst[255:0] := a[255:0] +sel := index[2:0]*32 +dst[sel+31:sel] := i[31:0] + +

immintrin.h

+ + + Integer + AVX + Swizzle + + + + + Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "index". + +dst[255:0] := a[255:0] +sel := index[1:0]*64 +dst[sel+63:sel] := i[63:0] + +

immintrin.h

+ + + Floating Point + AVX + Load + + + Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX + Load + + + Load 256-bits of integer data from memory into "dst". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Store + + + + Store 256-bits of integer data from "a" into memory. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX + Load + + + Load 256-bits of integer data from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Store + + + + Store 256-bits of integer data from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set). + +FOR j := 0 to 3 + i := j*64 + IF mask[i+63] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask". + +FOR j := 0 to 3 + i := j*64 + IF mask[i+63] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set). + +FOR j := 0 to 1 + i := j*64 + IF mask[i+63] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using "mask". + +FOR j := 0 to 1 + i := j*64 + IF mask[i+63] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set). + +FOR j := 0 to 7 + i := j*32 + IF mask[i+31] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask". + +FOR j := 0 to 7 + i := j*32 + IF mask[i+31] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using "mask" (elements are zeroed out when the high bit of the corresponding element is not set). + +FOR j := 0 to 3 + i := j*32 + IF mask[i+31] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using "mask". + +FOR j := 0 to 3 + i := j*32 + IF mask[i+31] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX + Move + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst". + +dst[31:0] := a[63:32] +dst[63:32] := a[63:32] +dst[95:64] := a[127:96] +dst[127:96] := a[127:96] +dst[159:128] := a[191:160] +dst[191:160] := a[191:160] +dst[223:192] := a[255:224] +dst[255:224] := a[255:224] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Move + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst". + +dst[31:0] := a[31:0] +dst[63:32] := a[31:0] +dst[95:64] := a[95:64] +dst[127:96] := a[95:64] +dst[159:128] := a[159:128] +dst[191:160] := a[159:128] +dst[223:192] := a[223:192] +dst[255:224] := a[223:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Move + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst". + +dst[63:0] := a[63:0] +dst[127:64] := a[63:0] +dst[191:128] := a[191:128] +dst[255:192] := a[191:128] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Load + + + Load 256-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm256_loadu_si256" when the data crosses a cache line boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Store + + + + Store 256-bits of integer data from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := 1.0 / a[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SQRT(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SQRT(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + + Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst". + [round_note] + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ROUND(a[i+63:i], rounding) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + + Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ROUND(a[i+31:i], rounding) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Swizzle + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value. + +IF ((a[255:0] AND b[255:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[255:0]) AND b[255:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +RETURN ZF + + +

immintrin.h

+ + + Integer + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value. + +IF ((a[255:0] AND b[255:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[255:0]) AND b[255:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +RETURN CF + + +

immintrin.h

+ + + Integer + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +IF ((a[255:0] AND b[255:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[255:0]) AND b[255:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value. + +tmp[255:0] := a[255:0] AND b[255:0] +IF (tmp[63] == 0 && tmp[127] == 0 && tmp[191] == 0 && tmp[255] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[255:0] := (NOT a[255:0]) AND b[255:0] +IF (tmp[63] == 0 && tmp[127] == 0 && tmp[191] == 0 && tmp[255] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := ZF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value. + +tmp[255:0] := a[255:0] AND b[255:0] +IF (tmp[63] == 0 && tmp[127] == 0 && tmp[191] == 0 && tmp[255] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[255:0] := (NOT a[255:0]) AND b[255:0] +IF (tmp[63] == 0 && tmp[127] == 0 && tmp[191] == 0 && tmp[255] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := CF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +tmp[255:0] := a[255:0] AND b[255:0] +IF (tmp[63] == 0 && tmp[127] == 0 && tmp[191] == 0 && tmp[255] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[255:0] := (NOT a[255:0]) AND b[255:0] +IF (tmp[63] == 0 && tmp[127] == 0 && tmp[191] == 0 && tmp[255] == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value. + +tmp[127:0] := a[127:0] AND b[127:0] +IF (tmp[63] == 0 && tmp[127] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[127:0] := (NOT a[127:0]) AND b[127:0] +IF (tmp[63] == 0 && tmp[127] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := ZF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value. + +tmp[127:0] := a[127:0] AND b[127:0] +IF (tmp[63] == 0 && tmp[127] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[127:0] := (NOT a[127:0]) AND b[127:0] +IF (tmp[63] == 0 && tmp[127] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := CF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +tmp[127:0] := a[127:0] AND b[127:0] +IF (tmp[63] == 0 && tmp[127] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[127:0] := (NOT a[127:0]) AND b[127:0] +IF (tmp[63] == 0 && tmp[127] == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value. + +tmp[255:0] := a[255:0] AND b[255:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0 && \ + tmp[159] == 0 && tmp[191] == 0 && tmp[223] == 0 && tmp[255] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[255:0] := (NOT a[255:0]) AND b[255:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0 && \ + tmp[159] == 0 && tmp[191] == 0 && tmp[223] == 0 && tmp[255] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := ZF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value. + +tmp[255:0] := a[255:0] AND b[255:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0 && \ + tmp[159] == 0 && tmp[191] == 0 && tmp[223] == 0 && tmp[255] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[255:0] := (NOT a[255:0]) AND b[255:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0 && \ + tmp[159] == 0 && tmp[191] == 0 && tmp[223] == 0 && tmp[255] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := CF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 256-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +tmp[255:0] := a[255:0] AND b[255:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0 && \ + tmp[159] == 0 && tmp[191] == 0 && tmp[223] == 0 && tmp[255] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[255:0] := (NOT a[255:0]) AND b[255:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0 && \ + tmp[159] == 0 && tmp[191] == 0 && tmp[223] == 0 && tmp[255] == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "ZF" value. + +tmp[127:0] := a[127:0] AND b[127:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[127:0] := (NOT a[127:0]) AND b[127:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := ZF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return the "CF" value. + +tmp[127:0] := a[127:0] AND b[127:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[127:0] := (NOT a[127:0]) AND b[127:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := CF + + +

immintrin.h

+ + + Floating Point + Flag + AVX + Logical + + + + Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in "a" and "b", producing an intermediate 128-bit value, and set "ZF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", producing an intermediate value, and set "CF" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +tmp[127:0] := a[127:0] AND b[127:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0) + ZF := 1 +ELSE + ZF := 0 +FI +tmp[127:0] := (NOT a[127:0]) AND b[127:0] +IF (tmp[31] == 0 && tmp[63] == 0 && tmp[95] == 0 && tmp[127] == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Floating Point + AVX + Miscellaneous + + + Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a". + +FOR j := 0 to 3 + i := j*64 + IF a[i+63] + dst[j] := 1 + ELSE + dst[j] := 0 + FI +ENDFOR +dst[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Miscellaneous + + + Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a". + +FOR j := 0 to 7 + i := j*32 + IF a[i+31] + dst[j] := 1 + ELSE + dst[j] := 0 + FI +ENDFOR +dst[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Set + + + Return vector of type __m256d with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Set + + + Return vector of type __m256 with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Integer + AVX + Set + + + Return vector of type __m256i with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 +dst[191:128] := e2 +dst[255:192] := e3 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 +dst[95:64] := e2 +dst[127:96] := e3 +dst[159:128] := e4 +dst[191:160] := e5 +dst[223:192] := e6 +dst[255:224] := e7 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values. + +dst[7:0] := e0 +dst[15:8] := e1 +dst[23:16] := e2 +dst[31:24] := e3 +dst[39:32] := e4 +dst[47:40] := e5 +dst[55:48] := e6 +dst[63:56] := e7 +dst[71:64] := e8 +dst[79:72] := e9 +dst[87:80] := e10 +dst[95:88] := e11 +dst[103:96] := e12 +dst[111:104] := e13 +dst[119:112] := e14 +dst[127:120] := e15 +dst[135:128] := e16 +dst[143:136] := e17 +dst[151:144] := e18 +dst[159:152] := e19 +dst[167:160] := e20 +dst[175:168] := e21 +dst[183:176] := e22 +dst[191:184] := e23 +dst[199:192] := e24 +dst[207:200] := e25 +dst[215:208] := e26 +dst[223:216] := e27 +dst[231:224] := e28 +dst[239:232] := e29 +dst[247:240] := e30 +dst[255:248] := e31 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + + + + + + + + + + + + + Set packed 16-bit integers in "dst" with the supplied values. + +dst[15:0] := e0 +dst[31:16] := e1 +dst[47:32] := e2 +dst[63:48] := e3 +dst[79:64] := e4 +dst[95:80] := e5 +dst[111:96] := e6 +dst[127:112] := e7 +dst[143:128] := e8 +dst[159:144] := e9 +dst[175:160] := e10 +dst[191:176] := e11 +dst[207:192] := e12 +dst[223:208] := e13 +dst[239:224] := e14 +dst[255:240] := e15 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + + + + + Set packed 32-bit integers in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 +dst[95:64] := e2 +dst[127:96] := e3 +dst[159:128] := e4 +dst[191:160] := e5 +dst[223:192] := e6 +dst[255:224] := e7 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + Set packed 64-bit integers in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 +dst[191:128] := e2 +dst[255:192] := e3 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order. + +dst[63:0] := e3 +dst[127:64] := e2 +dst[191:128] := e1 +dst[255:192] := e0 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order. + +dst[31:0] := e7 +dst[63:32] := e6 +dst[95:64] := e5 +dst[127:96] := e4 +dst[159:128] := e3 +dst[191:160] := e2 +dst[223:192] := e1 +dst[255:224] := e0 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values in reverse order. + +dst[7:0] := e31 +dst[15:8] := e30 +dst[23:16] := e29 +dst[31:24] := e28 +dst[39:32] := e27 +dst[47:40] := e26 +dst[55:48] := e25 +dst[63:56] := e24 +dst[71:64] := e23 +dst[79:72] := e22 +dst[87:80] := e21 +dst[95:88] := e20 +dst[103:96] := e19 +dst[111:104] := e18 +dst[119:112] := e17 +dst[127:120] := e16 +dst[135:128] := e15 +dst[143:136] := e14 +dst[151:144] := e13 +dst[159:152] := e12 +dst[167:160] := e11 +dst[175:168] := e10 +dst[183:176] := e9 +dst[191:184] := e8 +dst[199:192] := e7 +dst[207:200] := e6 +dst[215:208] := e5 +dst[223:216] := e4 +dst[231:224] := e3 +dst[239:232] := e2 +dst[247:240] := e1 +dst[255:248] := e0 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + + + + + + + + + + + + + Set packed 16-bit integers in "dst" with the supplied values in reverse order. + +dst[15:0] := e15 +dst[31:16] := e14 +dst[47:32] := e13 +dst[63:48] := e12 +dst[79:64] := e11 +dst[95:80] := e10 +dst[111:96] := e9 +dst[127:112] := e8 +dst[143:128] := e7 +dst[159:144] := e6 +dst[175:160] := e5 +dst[191:176] := e4 +dst[207:192] := e3 +dst[223:208] := e2 +dst[239:224] := e1 +dst[255:240] := e0 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + + + + + Set packed 32-bit integers in "dst" with the supplied values in reverse order. + +dst[31:0] := e7 +dst[63:32] := e6 +dst[95:64] := e5 +dst[127:96] := e4 +dst[159:128] := e3 +dst[191:160] := e2 +dst[223:192] := e1 +dst[255:224] := e0 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + + + + Set packed 64-bit integers in "dst" with the supplied values in reverse order. + +dst[63:0] := e3 +dst[127:64] := e2 +dst[191:128] := e1 +dst[255:192] := e0 +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Set + + + Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Set + + + Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastb". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate the "vpbroadcastw". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastd". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Set + + + Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m256d to type __m256. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m256 to type __m256d. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + AVX + Cast + + + Cast vector of type __m256 to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + AVX + Cast + + + Cast vector of type __m256d to type __m256i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m256i to type __m256. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m256i to type __m256d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m256 to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m256d to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX + Cast + + + Cast vector of type __m256i to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m128 to type __m256; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX + Cast + + + Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are undefined. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m128 to type __m256; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Cast + + + Cast vector of type __m128d to type __m256d; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX + Cast + + + Cast vector of type __m128i to type __m256i; the upper 128 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := FLOOR(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := CEIL(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := FLOOR(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CEIL(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + General Support + + + Return vector of type __m256 with undefined elements. +

immintrin.h

+ + + Floating Point + AVX + General Support + + + Return vector of type __m256d with undefined elements. +

immintrin.h

+ + + Integer + AVX + General Support + + + Return vector of type __m256i with undefined elements. +

immintrin.h

+ + + Floating Point + AVX + Set + + + + Set packed __m256 vector "dst" with the supplied values. + +dst[127:0] := lo[127:0] +dst[255:128] := hi[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + Set packed __m256d vector "dst" with the supplied values. + +dst[127:0] := lo[127:0] +dst[255:128] := hi[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Set + + + + Set packed __m256i vector "dst" with the supplied values. + +dst[127:0] := lo[127:0] +dst[255:128] := hi[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + Set packed __m256 vector "dst" with the supplied values. + +dst[127:0] := lo[127:0] +dst[255:128] := hi[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Set + + + + Set packed __m256d vector "dst" with the supplied values. + +dst[127:0] := lo[127:0] +dst[255:128] := hi[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX + Set + + + + Set packed __m256i vector "dst" with the supplied values. + +dst[127:0] := lo[127:0] +dst[255:128] := hi[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX + Load + + + + Load two 128-bit values (composed of 4 packed single-precision (32-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst". + "hiaddr" and "loaddr" do not need to be aligned on any particular boundary. + +dst[127:0] := MEM[loaddr+127:loaddr] +dst[255:128] := MEM[hiaddr+127:hiaddr] +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Load + + + + Load two 128-bit values (composed of 2 packed double-precision (64-bit) floating-point elements) from memory, and combine them into a 256-bit value in "dst". + "hiaddr" and "loaddr" do not need to be aligned on any particular boundary. + +dst[127:0] := MEM[loaddr+127:loaddr] +dst[255:128] := MEM[hiaddr+127:hiaddr] +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Load + + + + Load two 128-bit values (composed of integer data) from memory, and combine them into a 256-bit value in "dst". + "hiaddr" and "loaddr" do not need to be aligned on any particular boundary. + +dst[127:0] := MEM[loaddr+127:loaddr] +dst[255:128] := MEM[hiaddr+127:hiaddr] +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + + Store the high and low 128-bit halves (each composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory two different 128-bit locations. + "hiaddr" and "loaddr" do not need to be aligned on any particular boundary. + +MEM[loaddr+127:loaddr] := a[127:0] +MEM[hiaddr+127:hiaddr] := a[255:128] + +

immintrin.h

+ + + Floating Point + AVX + Store + + + + + Store the high and low 128-bit halves (each composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory two different 128-bit locations. + "hiaddr" and "loaddr" do not need to be aligned on any particular boundary. + +MEM[loaddr+127:loaddr] := a[127:0] +MEM[hiaddr+127:hiaddr] := a[255:128] + +

immintrin.h

+ + + Integer + AVX + Store + + + + + Store the high and low 128-bit halves (each composed of integer data) from "a" into memory two different 128-bit locations. + "hiaddr" and "loaddr" do not need to be aligned on any particular boundary. + +MEM[loaddr+127:loaddr] := a[127:0] +MEM[hiaddr+127:hiaddr] := a[255:128] + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ACOS(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ACOS(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ACOSH(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ACOSH(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ASIN(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ASIN(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ASINH(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ASINH(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ATAN(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ATAN(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians. + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ATANH(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ATANH(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CubeRoot(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := CubeRoot(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CDFNormal(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := CDFNormal(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := InverseCDFNormal(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := InverseCDFNormal(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]". + +DEFINE CEXP(a[31:0], b[31:0]) { + result[31:0] := POW(FP32(e), a[31:0]) * COS(b[31:0]) + result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0]) + RETURN result +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]". + +DEFINE CLOG(a[31:0], b[31:0]) { + result[31:0] := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0))) + result[63:32] := ATAN2(b, a) + RETURN result +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := COS(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := COS(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := COSD(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := COSD(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := COSH(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := COSH(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]". + +DEFINE CSQRT(a[31:0], b[31:0]) { + sign[31:0] := (b < 0.0) ? -FP32(1.0) : FP32(1.0) + result[31:0] := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0) + result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0) + RETURN result +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 31 + i := 8*j + IF b[i+7:i] == 0 + #DE + FI + dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 15 + i := 16*j + IF b[i+15:i] == 0 + #DE + FI + dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 7 + i := 32*j + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 3 + i := 64*j + IF b[i+63:i] == 0 + #DE + FI + dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 31 + i := 8*j + IF b[i+7:i] == 0 + #DE + FI + dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 15 + i := 16*j + IF b[i+15:i] == 0 + #DE + FI + dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 7 + i := 32*j + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 3 + i := 64*j + IF b[i+63:i] == 0 + #DE + FI + dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ERF(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ERF(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := 1.0 - ERF(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+63:i] := 1.0 - ERF(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i])) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i])) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := 1.0 / ERF(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Probability/Statistics + + + Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+63:i] := 1.0 / ERF(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := POW(e, a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := POW(FP32(e), a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := POW(10.0, a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := POW(FP32(10.0), a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := POW(2.0, a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := POW(e, a[i+63:i]) - 1.0 +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0 +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0)) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0)) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + + Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr". + FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := InvCubeRoot(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := InvCubeRoot(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := InvSQRT(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := InvSQRT(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := LOG(1.0 + a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := LOG(1.0 + a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + + Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := POW(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + + Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := POW(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 31 + i := 8*j + dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 15 + i := 16*j + dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 3 + i := 64*j + dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 31 + i := 8*j + dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 15 + i := 16*j + dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 3 + i := 64*j + dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SIN(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SIN(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + + Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SIN(a[i+63:i]) + MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + + Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SIN(a[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SIND(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SIND(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SINH(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SINH(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := CEIL(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := CEIL(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := FLOOR(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := FLOOR(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ROUND(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ROUND(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SQRT(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Elementary Math Functions + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SQRT(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := TAN(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := TAN(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := TAND(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := TAND(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := TANH(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Trigonometry + + + Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := TANH(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Miscellaneous + + + Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := TRUNCATE(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Miscellaneous + + + Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := TRUNCATE(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + AVX + Arithmetic + + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr". + FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + AVX + Convert + + + Copy the lower single-precision (32-bit) floating-point element of "a" to "dst". + +dst[31:0] := a[31:0] + + +

immintrin.h

+ + + Floating Point + AVX + Convert + + + Copy the lower double-precision (64-bit) floating-point element of "a" to "dst". + +dst[63:0] := a[63:0] + + +

immintrin.h

+ + + Integer + AVX + Convert + + + Copy the lower 32-bit integer in "a" to "dst". + +dst[31:0] := a[31:0] + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Extract an 8-bit integer from "a", selected with "index", and store the result in "dst". + +dst[7:0] := (a[255:0] >> (index[4:0] * 8))[7:0] + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Extract a 16-bit integer from "a", selected with "index", and store the result in "dst". + +dst[15:0] := (a[255:0] >> (index[3:0] * 16))[15:0] + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := ABS(a[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := ABS(a[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ABS(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := a[i+7:i] + b[i+7:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := a[i+15:i] + b[i+15:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst". + +FOR j := 0 to 1 + i := j*128 + tmp[255:0] := ((a[i+127:i] << 128)[255:0] OR b[i+127:i]) >> (imm8*8) + dst[i+127:i] := tmp[127:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Logical + + + + Compute the bitwise AND of 256 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[255:0] := (a[255:0] AND b[255:0]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Logical + + + + Compute the bitwise NOT of 256 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst". + +dst[255:0] := ((NOT a[255:0]) AND b[255:0]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Probability/Statistics + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Probability/Statistics + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + + Blend packed 16-bit integers from "a" and "b" within 128-bit lanes using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF imm8[j%8] + dst[i+15:i] := b[i+15:i] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + + Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF imm8[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + + Blend packed 32-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF imm8[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + + Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + IF mask[i+7] + dst[i+7:i] := b[i+7:i] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Swizzle + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Swizzle + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst". + +dst[127:0] := a[127:0] +dst[255:128] := a[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast 128 bits of integer data from "a" to all 128-bit lanes in "dst". + +dst[127:0] := a[127:0] +dst[255:128] := a[127:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Swizzle + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Swizzle + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ( a[i+63:i] > b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j:= 0 to 7 + i := 32*j + k := 16*j + dst[i+31:i] := SignExtend32(a[k+15:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j:= 0 to 3 + i := 64*j + k := 16*j + dst[i+63:i] := SignExtend64(a[k+15:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j:= 0 to 3 + i := 64*j + k := 32*j + dst[i+63:i] := SignExtend64(a[k+31:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + l := j*16 + dst[l+15:l] := SignExtend16(a[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 8*j + dst[i+31:i] := SignExtend32(a[k+7:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 8*j + dst[i+63:i] := SignExtend64(a[k+7:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 16*j + dst[i+31:i] := ZeroExtend32(a[k+15:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j:= 0 to 3 + i := 64*j + k := 16*j + dst[i+63:i] := ZeroExtend64(a[k+15:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j:= 0 to 3 + i := 64*j + k := 32*j + dst[i+63:i] := ZeroExtend64(a[k+31:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + l := j*16 + dst[l+15:l] := ZeroExtend16(a[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 8*j + dst[i+31:i] := ZeroExtend32(a[k+7:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Convert + + + Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 8*j + dst[i+63:i] := ZeroExtend64(a[k+7:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Extract 128 bits (composed of integer data) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst". + +dst[15:0] := a[31:16] + a[15:0] +dst[31:16] := a[63:48] + a[47:32] +dst[47:32] := a[95:80] + a[79:64] +dst[63:48] := a[127:112] + a[111:96] +dst[79:64] := b[31:16] + b[15:0] +dst[95:80] := b[63:48] + b[47:32] +dst[111:96] := b[95:80] + b[79:64] +dst[127:112] := b[127:112] + b[111:96] +dst[143:128] := a[159:144] + a[143:128] +dst[159:144] := a[191:176] + a[175:160] +dst[175:160] := a[223:208] + a[207:192] +dst[191:176] := a[255:240] + a[239:224] +dst[207:192] := b[159:144] + b[143:128] +dst[223:208] := b[191:176] + b[175:160] +dst[239:224] := b[223:208] + b[207:192] +dst[255:240] := b[255:240] + b[239:224] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst". + +dst[31:0] := a[63:32] + a[31:0] +dst[63:32] := a[127:96] + a[95:64] +dst[95:64] := b[63:32] + b[31:0] +dst[127:96] := b[127:96] + b[95:64] +dst[159:128] := a[191:160] + a[159:128] +dst[191:160] := a[255:224] + a[223:192] +dst[223:192] := b[191:160] + b[159:128] +dst[255:224] := b[255:224] + b[223:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst". + +dst[15:0] := Saturate16(a[31:16] + a[15:0]) +dst[31:16] := Saturate16(a[63:48] + a[47:32]) +dst[47:32] := Saturate16(a[95:80] + a[79:64]) +dst[63:48] := Saturate16(a[127:112] + a[111:96]) +dst[79:64] := Saturate16(b[31:16] + b[15:0]) +dst[95:80] := Saturate16(b[63:48] + b[47:32]) +dst[111:96] := Saturate16(b[95:80] + b[79:64]) +dst[127:112] := Saturate16(b[127:112] + b[111:96]) +dst[143:128] := Saturate16(a[159:144] + a[143:128]) +dst[159:144] := Saturate16(a[191:176] + a[175:160]) +dst[175:160] := Saturate16(a[223:208] + a[207:192]) +dst[191:176] := Saturate16(a[255:240] + a[239:224]) +dst[207:192] := Saturate16(b[159:144] + b[143:128]) +dst[223:208] := Saturate16(b[191:176] + b[175:160]) +dst[239:224] := Saturate16(b[223:208] + b[207:192]) +dst[255:240] := Saturate16(b[255:240] + b[239:224]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst". + +dst[15:0] := a[15:0] - a[31:16] +dst[31:16] := a[47:32] - a[63:48] +dst[47:32] := a[79:64] - a[95:80] +dst[63:48] := a[111:96] - a[127:112] +dst[79:64] := b[15:0] - b[31:16] +dst[95:80] := b[47:32] - b[63:48] +dst[111:96] := b[79:64] - b[95:80] +dst[127:112] := b[111:96] - b[127:112] +dst[143:128] := a[143:128] - a[159:144] +dst[159:144] := a[175:160] - a[191:176] +dst[175:160] := a[207:192] - a[223:208] +dst[191:176] := a[239:224] - a[255:240] +dst[207:192] := b[143:128] - b[159:144] +dst[223:208] := b[175:160] - b[191:176] +dst[239:224] := b[207:192] - b[223:208] +dst[255:240] := b[239:224] - b[255:240] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst". + +dst[31:0] := a[31:0] - a[63:32] +dst[63:32] := a[95:64] - a[127:96] +dst[95:64] := b[31:0] - b[63:32] +dst[127:96] := b[95:64] - b[127:96] +dst[159:128] := a[159:128] - a[191:160] +dst[191:160] := a[223:192] - a[255:224] +dst[223:192] := b[159:128] - b[191:160] +dst[255:224] := b[223:192] - b[255:224] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst". + +dst[15:0] := Saturate16(a[15:0] - a[31:16]) +dst[31:16] := Saturate16(a[47:32] - a[63:48]) +dst[47:32] := Saturate16(a[79:64] - a[95:80]) +dst[63:48] := Saturate16(a[111:96] - a[127:112]) +dst[79:64] := Saturate16(b[15:0] - b[31:16]) +dst[95:80] := Saturate16(b[47:32] - b[63:48]) +dst[111:96] := Saturate16(b[79:64] - b[95:80]) +dst[127:112] := Saturate16(b[111:96] - b[127:112]) +dst[143:128] := Saturate16(a[143:128] - a[159:144]) +dst[159:144] := Saturate16(a[175:160] - a[191:176]) +dst[175:160] := Saturate16(a[207:192] - a[223:208]) +dst[191:176] := Saturate16(a[239:224] - a[255:240]) +dst[207:192] := Saturate16(b[143:128] - b[159:144]) +dst[223:208] := Saturate16(b[175:160] - b[191:176]) +dst[239:224] := Saturate16(b[207:192] - b[223:208]) +dst[255:240] := Saturate16(b[239:224] - b[255:240]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + + Copy "a" to "dst", then insert 128 bits (composed of integer data) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE (imm8[0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + IF mask[i+63] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + IF mask[i+63] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:256] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + IF mask[i+31] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + IF mask[i+31] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:256] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + IF mask[i+31] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + IF mask[i+31] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:256] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + IF mask[i+63] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + IF mask[i+63] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:256] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + IF mask[i+63] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + IF mask[i+63] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:256] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF mask[i+31] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:64] := 0 +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF mask[i+31] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF mask[i+31] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:64] := 0 +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF mask[i+31] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + IF mask[i+63] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:128] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using "mask" (elements are copied from "src" when the highest bit is not set in the corresponding element). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + IF mask[i+63] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +mask[MAX:256] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element). + +FOR j := 0 to 3 + i := j*32 + IF mask[i+31] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + Load packed 32-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element). + +FOR j := 0 to 7 + i := j*32 + IF mask[i+31] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element). + +FOR j := 0 to 1 + i := j*64 + IF mask[i+63] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + + Load packed 64-bit integers from memory into "dst" using "mask" (elements are zeroed out when the highest bit is not set in the corresponding element). + +FOR j := 0 to 3 + i := j*64 + IF mask[i+63] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Store + + + + + Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element). + +FOR j := 0 to 3 + i := j*32 + IF mask[i+31] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX2 + Store + + + + + Store packed 32-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element). + +FOR j := 0 to 7 + i := j*32 + IF mask[i+31] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX2 + Store + + + + + Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element). + +FOR j := 0 to 1 + i := j*64 + IF mask[i+63] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX2 + Store + + + + + Store packed 64-bit integers from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element). + +FOR j := 0 to 3 + i := j*64 + IF mask[i+63] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Special Math Functions + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[j] := a[i+7] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". + Eight SADs are performed for each 128-bit lane using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8". + +DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) { + a_offset := imm8[2]*32 + b_offset := imm8[1:0]*32 + FOR j := 0 to 7 + i := j*8 + k := a_offset+i + l := b_offset + tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \ + ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24])) + ENDFOR + RETURN tmp[127:0] +} +dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0]) +dst[255:128] := MPSADBW(a[255:128], b[255:128], imm8[5:3]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+31:i] * b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 15 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 15 + i := j*16 + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst". + +FOR j := 0 to 15 + i := j*16 + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 15 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Multiply the packed signed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst". + +FOR j := 0 to 7 + i := j*32 + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Logical + + + + Compute the bitwise OR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[255:0] := (a[255:0] OR b[255:0]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst". + +dst[7:0] := Saturate8(a[15:0]) +dst[15:8] := Saturate8(a[31:16]) +dst[23:16] := Saturate8(a[47:32]) +dst[31:24] := Saturate8(a[63:48]) +dst[39:32] := Saturate8(a[79:64]) +dst[47:40] := Saturate8(a[95:80]) +dst[55:48] := Saturate8(a[111:96]) +dst[63:56] := Saturate8(a[127:112]) +dst[71:64] := Saturate8(b[15:0]) +dst[79:72] := Saturate8(b[31:16]) +dst[87:80] := Saturate8(b[47:32]) +dst[95:88] := Saturate8(b[63:48]) +dst[103:96] := Saturate8(b[79:64]) +dst[111:104] := Saturate8(b[95:80]) +dst[119:112] := Saturate8(b[111:96]) +dst[127:120] := Saturate8(b[127:112]) +dst[135:128] := Saturate8(a[143:128]) +dst[143:136] := Saturate8(a[159:144]) +dst[151:144] := Saturate8(a[175:160]) +dst[159:152] := Saturate8(a[191:176]) +dst[167:160] := Saturate8(a[207:192]) +dst[175:168] := Saturate8(a[223:208]) +dst[183:176] := Saturate8(a[239:224]) +dst[191:184] := Saturate8(a[255:240]) +dst[199:192] := Saturate8(b[143:128]) +dst[207:200] := Saturate8(b[159:144]) +dst[215:208] := Saturate8(b[175:160]) +dst[223:216] := Saturate8(b[191:176]) +dst[231:224] := Saturate8(b[207:192]) +dst[239:232] := Saturate8(b[223:208]) +dst[247:240] := Saturate8(b[239:224]) +dst[255:248] := Saturate8(b[255:240]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst". + +dst[15:0] := Saturate16(a[31:0]) +dst[31:16] := Saturate16(a[63:32]) +dst[47:32] := Saturate16(a[95:64]) +dst[63:48] := Saturate16(a[127:96]) +dst[79:64] := Saturate16(b[31:0]) +dst[95:80] := Saturate16(b[63:32]) +dst[111:96] := Saturate16(b[95:64]) +dst[127:112] := Saturate16(b[127:96]) +dst[143:128] := Saturate16(a[159:128]) +dst[159:144] := Saturate16(a[191:160]) +dst[175:160] := Saturate16(a[223:192]) +dst[191:176] := Saturate16(a[255:224]) +dst[207:192] := Saturate16(b[159:128]) +dst[223:208] := Saturate16(b[191:160]) +dst[239:224] := Saturate16(b[223:192]) +dst[255:240] := Saturate16(b[255:224]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst". + +dst[7:0] := SaturateU8(a[15:0]) +dst[15:8] := SaturateU8(a[31:16]) +dst[23:16] := SaturateU8(a[47:32]) +dst[31:24] := SaturateU8(a[63:48]) +dst[39:32] := SaturateU8(a[79:64]) +dst[47:40] := SaturateU8(a[95:80]) +dst[55:48] := SaturateU8(a[111:96]) +dst[63:56] := SaturateU8(a[127:112]) +dst[71:64] := SaturateU8(b[15:0]) +dst[79:72] := SaturateU8(b[31:16]) +dst[87:80] := SaturateU8(b[47:32]) +dst[95:88] := SaturateU8(b[63:48]) +dst[103:96] := SaturateU8(b[79:64]) +dst[111:104] := SaturateU8(b[95:80]) +dst[119:112] := SaturateU8(b[111:96]) +dst[127:120] := SaturateU8(b[127:112]) +dst[135:128] := SaturateU8(a[143:128]) +dst[143:136] := SaturateU8(a[159:144]) +dst[151:144] := SaturateU8(a[175:160]) +dst[159:152] := SaturateU8(a[191:176]) +dst[167:160] := SaturateU8(a[207:192]) +dst[175:168] := SaturateU8(a[223:208]) +dst[183:176] := SaturateU8(a[239:224]) +dst[191:184] := SaturateU8(a[255:240]) +dst[199:192] := SaturateU8(b[143:128]) +dst[207:200] := SaturateU8(b[159:144]) +dst[215:208] := SaturateU8(b[175:160]) +dst[223:216] := SaturateU8(b[191:176]) +dst[231:224] := SaturateU8(b[207:192]) +dst[239:232] := SaturateU8(b[223:208]) +dst[247:240] := SaturateU8(b[239:224]) +dst[255:248] := SaturateU8(b[255:240]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst". + +dst[15:0] := SaturateU16(a[31:0]) +dst[31:16] := SaturateU16(a[63:32]) +dst[47:32] := SaturateU16(a[95:64]) +dst[63:48] := SaturateU16(a[127:96]) +dst[79:64] := SaturateU16(b[31:0]) +dst[95:80] := SaturateU16(b[63:32]) +dst[111:96] := SaturateU16(b[95:64]) +dst[127:112] := SaturateU16(b[127:96]) +dst[143:128] := SaturateU16(a[159:128]) +dst[159:144] := SaturateU16(a[191:160]) +dst[175:160] := SaturateU16(a[223:192]) +dst[191:176] := SaturateU16(a[255:224]) +dst[207:192] := SaturateU16(b[159:128]) +dst[223:208] := SaturateU16(b[191:160]) +dst[239:224] := SaturateU16(b[223:192]) +dst[255:240] := SaturateU16(b[255:224]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + + Shuffle 128-bits (composed of integer data) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src1, src2, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src1[127:0] + 1: tmp[127:0] := src1[255:128] + 2: tmp[127:0] := src2[127:0] + 3: tmp[127:0] := src2[255:128] + ESAC + IF control[3] + tmp[127:0] := 0 + FI + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[255:0], b[255:0], imm8[3:0]) +dst[255:128] := SELECT4(a[255:0], b[255:0], imm8[7:4]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX2 + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx". + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst". + +FOR j := 0 to 31 + i := j*8 + tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i]) +ENDFOR +FOR j := 0 to 3 + i := j*64 + dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \ + tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56] + dst[i+63:i+16] := 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Shuffle 8-bit integers in "a" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[3:0] := b[i+3:i] + dst[i+7:i] := a[index*8+7:index*8] + FI + IF b[128+i+7] == 1 + dst[128+i+7:128+i] := 0 + ELSE + index[3:0] := b[128+i+3:128+i] + dst[128+i+7:128+i] := a[128+index*8+7:128+index*8] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst". + +dst[63:0] := a[63:0] +dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +dst[191:128] := a[191:128] +dst[207:192] := (a >> (imm8[1:0] * 16))[207:192] +dst[223:208] := (a >> (imm8[3:2] * 16))[207:192] +dst[239:224] := (a >> (imm8[5:4] * 16))[207:192] +dst[255:240] := (a >> (imm8[7:6] * 16))[207:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst". + +dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +dst[127:64] := a[127:64] +dst[143:128] := (a >> (imm8[1:0] * 16))[143:128] +dst[159:144] := (a >> (imm8[3:2] * 16))[143:128] +dst[175:160] := (a >> (imm8[5:4] * 16))[143:128] +dst[191:176] := (a >> (imm8[7:6] * 16))[143:128] +dst[255:192] := a[255:192] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Negate packed signed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 31 + i := j*8 + IF b[i+7:i] < 0 + dst[i+7:i] := -(a[i+7:i]) + ELSE IF b[i+7:i] == 0 + dst[i+7:i] := 0 + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Negate packed signed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 15 + i := j*16 + IF b[i+15:i] < 0 + dst[i+15:i] := -(a[i+15:i]) + ELSE IF b[i+15:i] == 0 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Negate packed signed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 7 + i := j*32 + IF b[i+31:i] < 0 + dst[i+31:i] := -(a[i+31:i]) + ELSE IF b[i+31:i] == 0 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst". + +tmp := imm8[7:0] +IF tmp > 15 + tmp := 16 +FI +dst[127:0] := a[127:0] << (tmp*8) +dst[255:128] := a[255:128] << (tmp*8) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst". + +tmp := imm8[7:0] +IF tmp > 15 + tmp := 16 +FI +dst[127:0] := a[127:0] >> (tmp*8) +dst[255:128] := a[255:128] >> (tmp*8) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Shift + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Load + + + Load 256-bits of integer data from memory into "dst" using a non-temporal memory hint. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := a[i+7:i] - b[i+7:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := a[i+15:i] - b[i+15:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Arithmetic + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Logical + + + + Compute the bitwise XOR of 256 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[255:0] := (a[255:0] XOR b[255:0]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX2 + Swizzle + + + + Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Miscellaneous + + + + Unpack and interleave 32 bits from masks "a" and "b", and store the 64-bit result in "dst". + +dst[31:0] := b[31:0] +dst[63:32] := a[31:0] +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Miscellaneous + + + + Unpack and interleave 16 bits from masks "a" and "b", and store the 32-bit result in "dst". + +dst[15:0] := b[15:0] +dst[31:16] := a[15:0] +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +FOR i := 0 to 1 + tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ] + tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ] + tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ] + tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ] +ENDFOR +FOR j := 0 to 3 + i := j*64 + dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +FOR i := 0 to 1 + tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ] + tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ] + tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ] + tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ] +ENDFOR +FOR j := 0 to 3 + i := j*64 + tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +FOR i := 0 to 1 + tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ] + tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ] + tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ] + tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ] +ENDFOR +FOR j := 0 to 3 + i := j*64 + tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +FOR i := 0 to 3 + tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ] + tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ] + tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ] + tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ] +ENDFOR +FOR j := 0 to 7 + i := j*64 + dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +FOR i := 0 to 3 + tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ] + tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ] + tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ] + tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ] +ENDFOR +FOR j := 0 to 7 + i := j*64 + tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected from within 128-bit lanes according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +FOR i := 0 to 3 + tmp.m128[i].dword[0] := b.m128[i].dword[ imm8[1:0] ] + tmp.m128[i].dword[1] := b.m128[i].dword[ imm8[3:2] ] + tmp.m128[i].dword[2] := b.m128[i].dword[ imm8[5:4] ] + tmp.m128[i].dword[3] := b.m128[i].dword[ imm8[7:6] ] +ENDFOR +FOR j := 0 to 7 + i := j*64 + tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +tmp.dword[0] := b.dword[ imm8[1:0] ] +tmp.dword[1] := b.dword[ imm8[3:2] ] +tmp.dword[2] := b.dword[ imm8[5:4] ] +tmp.dword[3] := b.dword[ imm8[7:6] ] +FOR j := 0 to 1 + i := j*64 + dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +tmp.dword[0] := b.dword[ imm8[1:0] ] +tmp.dword[1] := b.dword[ imm8[3:2] ] +tmp.dword[2] := b.dword[ imm8[5:4] ] +tmp.dword[3] := b.dword[ imm8[7:6] ] +FOR j := 0 to 1 + i := j*64 + tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + Four SADs are performed on four 8-bit quadruplets for each 64-bit lane. The first two SADs use the lower 8-bit quadruplet of the lane from "a", and the last two SADs use the uppper 8-bit quadruplet of the lane from "a". Quadruplets from "b" are selected according to the control in "imm8", and each SAD in each 64-bit lane uses the selected quadruplet at 8-bit offsets. + +tmp.dword[0] := b.dword[ imm8[1:0] ] +tmp.dword[1] := b.dword[ imm8[3:2] ] +tmp.dword[2] := b.dword[ imm8[5:4] ] +tmp.dword[3] := b.dword[ imm8[7:6] ] +FOR j := 0 to 1 + i := j*64 + tmp_dst[i+15:i] := ABS(a[i+7:i] - tmp[i+7:i]) + ABS(a[i+15:i+8] - tmp[i+15:i+8]) +\ + ABS(a[i+23:i+16] - tmp[i+23:i+16]) + ABS(a[i+31:i+24] - tmp[i+31:i+24]) + + tmp_dst[i+31:i+16] := ABS(a[i+7:i] - tmp[i+15:i+8]) + ABS(a[i+15:i+8] - tmp[i+23:i+16]) +\ + ABS(a[i+23:i+16] - tmp[i+31:i+24]) + ABS(a[i+31:i+24] - tmp[i+39:i+32]) + + tmp_dst[i+47:i+32] := ABS(a[i+39:i+32] - tmp[i+23:i+16]) + ABS(a[i+47:i+40] - tmp[i+31:i+24]) +\ + ABS(a[i+55:i+48] - tmp[i+39:i+32]) + ABS(a[i+63:i+56] - tmp[i+47:i+40]) + + tmp_dst[i+63:i+48] := ABS(a[i+39:i+32] - tmp[i+31:i+24]) + ABS(a[i+47:i+40] - tmp[i+39:i+32]) +\ + ABS(a[i+55:i+48] - tmp[i+47:i+40]) + ABS(a[i+63:i+56] - tmp[i+55:i+48]) +ENDFOR +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + + Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + + Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + + Store packed 16-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*16 + IF k[j] + MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Load + + + + + Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Move + + + + + Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Store + + + + + Store packed 16-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 31 + i := j*16 + IF k[j] + MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512BW + Load + + + + Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Move + + + + Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + + Load packed 16-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + + Move packed 16-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + + Store packed 16-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*16 + IF k[j] + MEM[mem_addr+i+15:mem_addr+i] := a[i+15:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + Load packed 16-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+i+15:mem_addr+i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + Move packed 16-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + + Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + + Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + + Store packed 8-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 31 + i := j*8 + IF k[j] + MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Load + + + + + Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Move + + + + + Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Store + + + + + Store packed 8-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 63 + i := j*8 + IF k[j] + MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512BW + Load + + + + Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Move + + + + Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + + Load packed 8-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + + Move packed 8-bit integers from "a" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + + Store packed 8-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*8 + IF k[j] + MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + + Load packed 8-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+i+7:mem_addr+i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Move + + + + Move packed 8-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := ABS(a[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := ABS(a[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := ABS(a[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := ABS(a[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := ABS(a[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := ABS(a[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := ABS(a[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := ABS(a[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := ABS(a[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := ABS(a[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := ABS(a[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := ABS(a[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := ABS(a[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := ABS(a[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := Saturate16(a[31:0]) +tmp_dst[31:16] := Saturate16(a[63:32]) +tmp_dst[47:32] := Saturate16(a[95:64]) +tmp_dst[63:48] := Saturate16(a[127:96]) +tmp_dst[79:64] := Saturate16(b[31:0]) +tmp_dst[95:80] := Saturate16(b[63:32]) +tmp_dst[111:96] := Saturate16(b[95:64]) +tmp_dst[127:112] := Saturate16(b[127:96]) +tmp_dst[143:128] := Saturate16(a[159:128]) +tmp_dst[159:144] := Saturate16(a[191:160]) +tmp_dst[175:160] := Saturate16(a[223:192]) +tmp_dst[191:176] := Saturate16(a[255:224]) +tmp_dst[207:192] := Saturate16(b[159:128]) +tmp_dst[223:208] := Saturate16(b[191:160]) +tmp_dst[239:224] := Saturate16(b[223:192]) +tmp_dst[255:240] := Saturate16(b[255:224]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := Saturate16(a[31:0]) +tmp_dst[31:16] := Saturate16(a[63:32]) +tmp_dst[47:32] := Saturate16(a[95:64]) +tmp_dst[63:48] := Saturate16(a[127:96]) +tmp_dst[79:64] := Saturate16(b[31:0]) +tmp_dst[95:80] := Saturate16(b[63:32]) +tmp_dst[111:96] := Saturate16(b[95:64]) +tmp_dst[127:112] := Saturate16(b[127:96]) +tmp_dst[143:128] := Saturate16(a[159:128]) +tmp_dst[159:144] := Saturate16(a[191:160]) +tmp_dst[175:160] := Saturate16(a[223:192]) +tmp_dst[191:176] := Saturate16(a[255:224]) +tmp_dst[207:192] := Saturate16(b[159:128]) +tmp_dst[223:208] := Saturate16(b[191:160]) +tmp_dst[239:224] := Saturate16(b[223:192]) +tmp_dst[255:240] := Saturate16(b[255:224]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := Saturate16(a[31:0]) +tmp_dst[31:16] := Saturate16(a[63:32]) +tmp_dst[47:32] := Saturate16(a[95:64]) +tmp_dst[63:48] := Saturate16(a[127:96]) +tmp_dst[79:64] := Saturate16(b[31:0]) +tmp_dst[95:80] := Saturate16(b[63:32]) +tmp_dst[111:96] := Saturate16(b[95:64]) +tmp_dst[127:112] := Saturate16(b[127:96]) +tmp_dst[143:128] := Saturate16(a[159:128]) +tmp_dst[159:144] := Saturate16(a[191:160]) +tmp_dst[175:160] := Saturate16(a[223:192]) +tmp_dst[191:176] := Saturate16(a[255:224]) +tmp_dst[207:192] := Saturate16(b[159:128]) +tmp_dst[223:208] := Saturate16(b[191:160]) +tmp_dst[239:224] := Saturate16(b[223:192]) +tmp_dst[255:240] := Saturate16(b[255:224]) +tmp_dst[271:256] := Saturate16(a[287:256]) +tmp_dst[287:272] := Saturate16(a[319:288]) +tmp_dst[303:288] := Saturate16(a[351:320]) +tmp_dst[319:304] := Saturate16(a[383:352]) +tmp_dst[335:320] := Saturate16(b[287:256]) +tmp_dst[351:336] := Saturate16(b[319:288]) +tmp_dst[367:352] := Saturate16(b[351:320]) +tmp_dst[383:368] := Saturate16(b[383:352]) +tmp_dst[399:384] := Saturate16(a[415:384]) +tmp_dst[415:400] := Saturate16(a[447:416]) +tmp_dst[431:416] := Saturate16(a[479:448]) +tmp_dst[447:432] := Saturate16(a[511:480]) +tmp_dst[463:448] := Saturate16(b[415:384]) +tmp_dst[479:464] := Saturate16(b[447:416]) +tmp_dst[495:480] := Saturate16(b[479:448]) +tmp_dst[511:496] := Saturate16(b[511:480]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := Saturate16(a[31:0]) +tmp_dst[31:16] := Saturate16(a[63:32]) +tmp_dst[47:32] := Saturate16(a[95:64]) +tmp_dst[63:48] := Saturate16(a[127:96]) +tmp_dst[79:64] := Saturate16(b[31:0]) +tmp_dst[95:80] := Saturate16(b[63:32]) +tmp_dst[111:96] := Saturate16(b[95:64]) +tmp_dst[127:112] := Saturate16(b[127:96]) +tmp_dst[143:128] := Saturate16(a[159:128]) +tmp_dst[159:144] := Saturate16(a[191:160]) +tmp_dst[175:160] := Saturate16(a[223:192]) +tmp_dst[191:176] := Saturate16(a[255:224]) +tmp_dst[207:192] := Saturate16(b[159:128]) +tmp_dst[223:208] := Saturate16(b[191:160]) +tmp_dst[239:224] := Saturate16(b[223:192]) +tmp_dst[255:240] := Saturate16(b[255:224]) +tmp_dst[271:256] := Saturate16(a[287:256]) +tmp_dst[287:272] := Saturate16(a[319:288]) +tmp_dst[303:288] := Saturate16(a[351:320]) +tmp_dst[319:304] := Saturate16(a[383:352]) +tmp_dst[335:320] := Saturate16(b[287:256]) +tmp_dst[351:336] := Saturate16(b[319:288]) +tmp_dst[367:352] := Saturate16(b[351:320]) +tmp_dst[383:368] := Saturate16(b[383:352]) +tmp_dst[399:384] := Saturate16(a[415:384]) +tmp_dst[415:400] := Saturate16(a[447:416]) +tmp_dst[431:416] := Saturate16(a[479:448]) +tmp_dst[447:432] := Saturate16(a[511:480]) +tmp_dst[463:448] := Saturate16(b[415:384]) +tmp_dst[479:464] := Saturate16(b[447:416]) +tmp_dst[495:480] := Saturate16(b[479:448]) +tmp_dst[511:496] := Saturate16(b[511:480]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst". + +dst[15:0] := Saturate16(a[31:0]) +dst[31:16] := Saturate16(a[63:32]) +dst[47:32] := Saturate16(a[95:64]) +dst[63:48] := Saturate16(a[127:96]) +dst[79:64] := Saturate16(b[31:0]) +dst[95:80] := Saturate16(b[63:32]) +dst[111:96] := Saturate16(b[95:64]) +dst[127:112] := Saturate16(b[127:96]) +dst[143:128] := Saturate16(a[159:128]) +dst[159:144] := Saturate16(a[191:160]) +dst[175:160] := Saturate16(a[223:192]) +dst[191:176] := Saturate16(a[255:224]) +dst[207:192] := Saturate16(b[159:128]) +dst[223:208] := Saturate16(b[191:160]) +dst[239:224] := Saturate16(b[223:192]) +dst[255:240] := Saturate16(b[255:224]) +dst[271:256] := Saturate16(a[287:256]) +dst[287:272] := Saturate16(a[319:288]) +dst[303:288] := Saturate16(a[351:320]) +dst[319:304] := Saturate16(a[383:352]) +dst[335:320] := Saturate16(b[287:256]) +dst[351:336] := Saturate16(b[319:288]) +dst[367:352] := Saturate16(b[351:320]) +dst[383:368] := Saturate16(b[383:352]) +dst[399:384] := Saturate16(a[415:384]) +dst[415:400] := Saturate16(a[447:416]) +dst[431:416] := Saturate16(a[479:448]) +dst[447:432] := Saturate16(a[511:480]) +dst[463:448] := Saturate16(b[415:384]) +dst[479:464] := Saturate16(b[447:416]) +dst[495:480] := Saturate16(b[479:448]) +dst[511:496] := Saturate16(b[511:480]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[7:0] := Saturate8(a[15:0]) +tmp_dst[15:8] := Saturate8(a[31:16]) +tmp_dst[23:16] := Saturate8(a[47:32]) +tmp_dst[31:24] := Saturate8(a[63:48]) +tmp_dst[39:32] := Saturate8(a[79:64]) +tmp_dst[47:40] := Saturate8(a[95:80]) +tmp_dst[55:48] := Saturate8(a[111:96]) +tmp_dst[63:56] := Saturate8(a[127:112]) +tmp_dst[71:64] := Saturate8(b[15:0]) +tmp_dst[79:72] := Saturate8(b[31:16]) +tmp_dst[87:80] := Saturate8(b[47:32]) +tmp_dst[95:88] := Saturate8(b[63:48]) +tmp_dst[103:96] := Saturate8(b[79:64]) +tmp_dst[111:104] := Saturate8(b[95:80]) +tmp_dst[119:112] := Saturate8(b[111:96]) +tmp_dst[127:120] := Saturate8(b[127:112]) +tmp_dst[135:128] := Saturate8(a[143:128]) +tmp_dst[143:136] := Saturate8(a[159:144]) +tmp_dst[151:144] := Saturate8(a[175:160]) +tmp_dst[159:152] := Saturate8(a[191:176]) +tmp_dst[167:160] := Saturate8(a[207:192]) +tmp_dst[175:168] := Saturate8(a[223:208]) +tmp_dst[183:176] := Saturate8(a[239:224]) +tmp_dst[191:184] := Saturate8(a[255:240]) +tmp_dst[199:192] := Saturate8(b[143:128]) +tmp_dst[207:200] := Saturate8(b[159:144]) +tmp_dst[215:208] := Saturate8(b[175:160]) +tmp_dst[223:216] := Saturate8(b[191:176]) +tmp_dst[231:224] := Saturate8(b[207:192]) +tmp_dst[239:232] := Saturate8(b[223:208]) +tmp_dst[247:240] := Saturate8(b[239:224]) +tmp_dst[255:248] := Saturate8(b[255:240]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[7:0] := Saturate8(a[15:0]) +tmp_dst[15:8] := Saturate8(a[31:16]) +tmp_dst[23:16] := Saturate8(a[47:32]) +tmp_dst[31:24] := Saturate8(a[63:48]) +tmp_dst[39:32] := Saturate8(a[79:64]) +tmp_dst[47:40] := Saturate8(a[95:80]) +tmp_dst[55:48] := Saturate8(a[111:96]) +tmp_dst[63:56] := Saturate8(a[127:112]) +tmp_dst[71:64] := Saturate8(b[15:0]) +tmp_dst[79:72] := Saturate8(b[31:16]) +tmp_dst[87:80] := Saturate8(b[47:32]) +tmp_dst[95:88] := Saturate8(b[63:48]) +tmp_dst[103:96] := Saturate8(b[79:64]) +tmp_dst[111:104] := Saturate8(b[95:80]) +tmp_dst[119:112] := Saturate8(b[111:96]) +tmp_dst[127:120] := Saturate8(b[127:112]) +tmp_dst[135:128] := Saturate8(a[143:128]) +tmp_dst[143:136] := Saturate8(a[159:144]) +tmp_dst[151:144] := Saturate8(a[175:160]) +tmp_dst[159:152] := Saturate8(a[191:176]) +tmp_dst[167:160] := Saturate8(a[207:192]) +tmp_dst[175:168] := Saturate8(a[223:208]) +tmp_dst[183:176] := Saturate8(a[239:224]) +tmp_dst[191:184] := Saturate8(a[255:240]) +tmp_dst[199:192] := Saturate8(b[143:128]) +tmp_dst[207:200] := Saturate8(b[159:144]) +tmp_dst[215:208] := Saturate8(b[175:160]) +tmp_dst[223:216] := Saturate8(b[191:176]) +tmp_dst[231:224] := Saturate8(b[207:192]) +tmp_dst[239:232] := Saturate8(b[223:208]) +tmp_dst[247:240] := Saturate8(b[239:224]) +tmp_dst[255:248] := Saturate8(b[255:240]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[7:0] := Saturate8(a[15:0]) +tmp_dst[15:8] := Saturate8(a[31:16]) +tmp_dst[23:16] := Saturate8(a[47:32]) +tmp_dst[31:24] := Saturate8(a[63:48]) +tmp_dst[39:32] := Saturate8(a[79:64]) +tmp_dst[47:40] := Saturate8(a[95:80]) +tmp_dst[55:48] := Saturate8(a[111:96]) +tmp_dst[63:56] := Saturate8(a[127:112]) +tmp_dst[71:64] := Saturate8(b[15:0]) +tmp_dst[79:72] := Saturate8(b[31:16]) +tmp_dst[87:80] := Saturate8(b[47:32]) +tmp_dst[95:88] := Saturate8(b[63:48]) +tmp_dst[103:96] := Saturate8(b[79:64]) +tmp_dst[111:104] := Saturate8(b[95:80]) +tmp_dst[119:112] := Saturate8(b[111:96]) +tmp_dst[127:120] := Saturate8(b[127:112]) +tmp_dst[135:128] := Saturate8(a[143:128]) +tmp_dst[143:136] := Saturate8(a[159:144]) +tmp_dst[151:144] := Saturate8(a[175:160]) +tmp_dst[159:152] := Saturate8(a[191:176]) +tmp_dst[167:160] := Saturate8(a[207:192]) +tmp_dst[175:168] := Saturate8(a[223:208]) +tmp_dst[183:176] := Saturate8(a[239:224]) +tmp_dst[191:184] := Saturate8(a[255:240]) +tmp_dst[199:192] := Saturate8(b[143:128]) +tmp_dst[207:200] := Saturate8(b[159:144]) +tmp_dst[215:208] := Saturate8(b[175:160]) +tmp_dst[223:216] := Saturate8(b[191:176]) +tmp_dst[231:224] := Saturate8(b[207:192]) +tmp_dst[239:232] := Saturate8(b[223:208]) +tmp_dst[247:240] := Saturate8(b[239:224]) +tmp_dst[255:248] := Saturate8(b[255:240]) +tmp_dst[263:256] := Saturate8(a[271:256]) +tmp_dst[271:264] := Saturate8(a[287:272]) +tmp_dst[279:272] := Saturate8(a[303:288]) +tmp_dst[287:280] := Saturate8(a[319:304]) +tmp_dst[295:288] := Saturate8(a[335:320]) +tmp_dst[303:296] := Saturate8(a[351:336]) +tmp_dst[311:304] := Saturate8(a[367:352]) +tmp_dst[319:312] := Saturate8(a[383:368]) +tmp_dst[327:320] := Saturate8(b[271:256]) +tmp_dst[335:328] := Saturate8(b[287:272]) +tmp_dst[343:336] := Saturate8(b[303:288]) +tmp_dst[351:344] := Saturate8(b[319:304]) +tmp_dst[359:352] := Saturate8(b[335:320]) +tmp_dst[367:360] := Saturate8(b[351:336]) +tmp_dst[375:368] := Saturate8(b[367:352]) +tmp_dst[383:376] := Saturate8(b[383:368]) +tmp_dst[391:384] := Saturate8(a[399:384]) +tmp_dst[399:392] := Saturate8(a[415:400]) +tmp_dst[407:400] := Saturate8(a[431:416]) +tmp_dst[415:408] := Saturate8(a[447:432]) +tmp_dst[423:416] := Saturate8(a[463:448]) +tmp_dst[431:424] := Saturate8(a[479:464]) +tmp_dst[439:432] := Saturate8(a[495:480]) +tmp_dst[447:440] := Saturate8(a[511:496]) +tmp_dst[455:448] := Saturate8(b[399:384]) +tmp_dst[463:456] := Saturate8(b[415:400]) +tmp_dst[471:464] := Saturate8(b[431:416]) +tmp_dst[479:472] := Saturate8(b[447:432]) +tmp_dst[487:480] := Saturate8(b[463:448]) +tmp_dst[495:488] := Saturate8(b[479:464]) +tmp_dst[503:496] := Saturate8(b[495:480]) +tmp_dst[511:504] := Saturate8(b[511:496]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[7:0] := Saturate8(a[15:0]) +tmp_dst[15:8] := Saturate8(a[31:16]) +tmp_dst[23:16] := Saturate8(a[47:32]) +tmp_dst[31:24] := Saturate8(a[63:48]) +tmp_dst[39:32] := Saturate8(a[79:64]) +tmp_dst[47:40] := Saturate8(a[95:80]) +tmp_dst[55:48] := Saturate8(a[111:96]) +tmp_dst[63:56] := Saturate8(a[127:112]) +tmp_dst[71:64] := Saturate8(b[15:0]) +tmp_dst[79:72] := Saturate8(b[31:16]) +tmp_dst[87:80] := Saturate8(b[47:32]) +tmp_dst[95:88] := Saturate8(b[63:48]) +tmp_dst[103:96] := Saturate8(b[79:64]) +tmp_dst[111:104] := Saturate8(b[95:80]) +tmp_dst[119:112] := Saturate8(b[111:96]) +tmp_dst[127:120] := Saturate8(b[127:112]) +tmp_dst[135:128] := Saturate8(a[143:128]) +tmp_dst[143:136] := Saturate8(a[159:144]) +tmp_dst[151:144] := Saturate8(a[175:160]) +tmp_dst[159:152] := Saturate8(a[191:176]) +tmp_dst[167:160] := Saturate8(a[207:192]) +tmp_dst[175:168] := Saturate8(a[223:208]) +tmp_dst[183:176] := Saturate8(a[239:224]) +tmp_dst[191:184] := Saturate8(a[255:240]) +tmp_dst[199:192] := Saturate8(b[143:128]) +tmp_dst[207:200] := Saturate8(b[159:144]) +tmp_dst[215:208] := Saturate8(b[175:160]) +tmp_dst[223:216] := Saturate8(b[191:176]) +tmp_dst[231:224] := Saturate8(b[207:192]) +tmp_dst[239:232] := Saturate8(b[223:208]) +tmp_dst[247:240] := Saturate8(b[239:224]) +tmp_dst[255:248] := Saturate8(b[255:240]) +tmp_dst[263:256] := Saturate8(a[271:256]) +tmp_dst[271:264] := Saturate8(a[287:272]) +tmp_dst[279:272] := Saturate8(a[303:288]) +tmp_dst[287:280] := Saturate8(a[319:304]) +tmp_dst[295:288] := Saturate8(a[335:320]) +tmp_dst[303:296] := Saturate8(a[351:336]) +tmp_dst[311:304] := Saturate8(a[367:352]) +tmp_dst[319:312] := Saturate8(a[383:368]) +tmp_dst[327:320] := Saturate8(b[271:256]) +tmp_dst[335:328] := Saturate8(b[287:272]) +tmp_dst[343:336] := Saturate8(b[303:288]) +tmp_dst[351:344] := Saturate8(b[319:304]) +tmp_dst[359:352] := Saturate8(b[335:320]) +tmp_dst[367:360] := Saturate8(b[351:336]) +tmp_dst[375:368] := Saturate8(b[367:352]) +tmp_dst[383:376] := Saturate8(b[383:368]) +tmp_dst[391:384] := Saturate8(a[399:384]) +tmp_dst[399:392] := Saturate8(a[415:400]) +tmp_dst[407:400] := Saturate8(a[431:416]) +tmp_dst[415:408] := Saturate8(a[447:432]) +tmp_dst[423:416] := Saturate8(a[463:448]) +tmp_dst[431:424] := Saturate8(a[479:464]) +tmp_dst[439:432] := Saturate8(a[495:480]) +tmp_dst[447:440] := Saturate8(a[511:496]) +tmp_dst[455:448] := Saturate8(b[399:384]) +tmp_dst[463:456] := Saturate8(b[415:400]) +tmp_dst[471:464] := Saturate8(b[431:416]) +tmp_dst[479:472] := Saturate8(b[447:432]) +tmp_dst[487:480] := Saturate8(b[463:448]) +tmp_dst[495:488] := Saturate8(b[479:464]) +tmp_dst[503:496] := Saturate8(b[495:480]) +tmp_dst[511:504] := Saturate8(b[511:496]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst". + +dst[7:0] := Saturate8(a[15:0]) +dst[15:8] := Saturate8(a[31:16]) +dst[23:16] := Saturate8(a[47:32]) +dst[31:24] := Saturate8(a[63:48]) +dst[39:32] := Saturate8(a[79:64]) +dst[47:40] := Saturate8(a[95:80]) +dst[55:48] := Saturate8(a[111:96]) +dst[63:56] := Saturate8(a[127:112]) +dst[71:64] := Saturate8(b[15:0]) +dst[79:72] := Saturate8(b[31:16]) +dst[87:80] := Saturate8(b[47:32]) +dst[95:88] := Saturate8(b[63:48]) +dst[103:96] := Saturate8(b[79:64]) +dst[111:104] := Saturate8(b[95:80]) +dst[119:112] := Saturate8(b[111:96]) +dst[127:120] := Saturate8(b[127:112]) +dst[135:128] := Saturate8(a[143:128]) +dst[143:136] := Saturate8(a[159:144]) +dst[151:144] := Saturate8(a[175:160]) +dst[159:152] := Saturate8(a[191:176]) +dst[167:160] := Saturate8(a[207:192]) +dst[175:168] := Saturate8(a[223:208]) +dst[183:176] := Saturate8(a[239:224]) +dst[191:184] := Saturate8(a[255:240]) +dst[199:192] := Saturate8(b[143:128]) +dst[207:200] := Saturate8(b[159:144]) +dst[215:208] := Saturate8(b[175:160]) +dst[223:216] := Saturate8(b[191:176]) +dst[231:224] := Saturate8(b[207:192]) +dst[239:232] := Saturate8(b[223:208]) +dst[247:240] := Saturate8(b[239:224]) +dst[255:248] := Saturate8(b[255:240]) +dst[263:256] := Saturate8(a[271:256]) +dst[271:264] := Saturate8(a[287:272]) +dst[279:272] := Saturate8(a[303:288]) +dst[287:280] := Saturate8(a[319:304]) +dst[295:288] := Saturate8(a[335:320]) +dst[303:296] := Saturate8(a[351:336]) +dst[311:304] := Saturate8(a[367:352]) +dst[319:312] := Saturate8(a[383:368]) +dst[327:320] := Saturate8(b[271:256]) +dst[335:328] := Saturate8(b[287:272]) +dst[343:336] := Saturate8(b[303:288]) +dst[351:344] := Saturate8(b[319:304]) +dst[359:352] := Saturate8(b[335:320]) +dst[367:360] := Saturate8(b[351:336]) +dst[375:368] := Saturate8(b[367:352]) +dst[383:376] := Saturate8(b[383:368]) +dst[391:384] := Saturate8(a[399:384]) +dst[399:392] := Saturate8(a[415:400]) +dst[407:400] := Saturate8(a[431:416]) +dst[415:408] := Saturate8(a[447:432]) +dst[423:416] := Saturate8(a[463:448]) +dst[431:424] := Saturate8(a[479:464]) +dst[439:432] := Saturate8(a[495:480]) +dst[447:440] := Saturate8(a[511:496]) +dst[455:448] := Saturate8(b[399:384]) +dst[463:456] := Saturate8(b[415:400]) +dst[471:464] := Saturate8(b[431:416]) +dst[479:472] := Saturate8(b[447:432]) +dst[487:480] := Saturate8(b[463:448]) +dst[495:488] := Saturate8(b[479:464]) +dst[503:496] := Saturate8(b[495:480]) +dst[511:504] := Saturate8(b[511:496]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := SaturateU16(a[31:0]) +tmp_dst[31:16] := SaturateU16(a[63:32]) +tmp_dst[47:32] := SaturateU16(a[95:64]) +tmp_dst[63:48] := SaturateU16(a[127:96]) +tmp_dst[79:64] := SaturateU16(b[31:0]) +tmp_dst[95:80] := SaturateU16(b[63:32]) +tmp_dst[111:96] := SaturateU16(b[95:64]) +tmp_dst[127:112] := SaturateU16(b[127:96]) +tmp_dst[143:128] := SaturateU16(a[159:128]) +tmp_dst[159:144] := SaturateU16(a[191:160]) +tmp_dst[175:160] := SaturateU16(a[223:192]) +tmp_dst[191:176] := SaturateU16(a[255:224]) +tmp_dst[207:192] := SaturateU16(b[159:128]) +tmp_dst[223:208] := SaturateU16(b[191:160]) +tmp_dst[239:224] := SaturateU16(b[223:192]) +tmp_dst[255:240] := SaturateU16(b[255:224]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := SaturateU16(a[31:0]) +tmp_dst[31:16] := SaturateU16(a[63:32]) +tmp_dst[47:32] := SaturateU16(a[95:64]) +tmp_dst[63:48] := SaturateU16(a[127:96]) +tmp_dst[79:64] := SaturateU16(b[31:0]) +tmp_dst[95:80] := SaturateU16(b[63:32]) +tmp_dst[111:96] := SaturateU16(b[95:64]) +tmp_dst[127:112] := SaturateU16(b[127:96]) +tmp_dst[143:128] := SaturateU16(a[159:128]) +tmp_dst[159:144] := SaturateU16(a[191:160]) +tmp_dst[175:160] := SaturateU16(a[223:192]) +tmp_dst[191:176] := SaturateU16(a[255:224]) +tmp_dst[207:192] := SaturateU16(b[159:128]) +tmp_dst[223:208] := SaturateU16(b[191:160]) +tmp_dst[239:224] := SaturateU16(b[223:192]) +tmp_dst[255:240] := SaturateU16(b[255:224]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := SaturateU16(a[31:0]) +tmp_dst[31:16] := SaturateU16(a[63:32]) +tmp_dst[47:32] := SaturateU16(a[95:64]) +tmp_dst[63:48] := SaturateU16(a[127:96]) +tmp_dst[79:64] := SaturateU16(b[31:0]) +tmp_dst[95:80] := SaturateU16(b[63:32]) +tmp_dst[111:96] := SaturateU16(b[95:64]) +tmp_dst[127:112] := SaturateU16(b[127:96]) +tmp_dst[143:128] := SaturateU16(a[159:128]) +tmp_dst[159:144] := SaturateU16(a[191:160]) +tmp_dst[175:160] := SaturateU16(a[223:192]) +tmp_dst[191:176] := SaturateU16(a[255:224]) +tmp_dst[207:192] := SaturateU16(b[159:128]) +tmp_dst[223:208] := SaturateU16(b[191:160]) +tmp_dst[239:224] := SaturateU16(b[223:192]) +tmp_dst[255:240] := SaturateU16(b[255:224]) +tmp_dst[271:256] := SaturateU16(a[287:256]) +tmp_dst[287:272] := SaturateU16(a[319:288]) +tmp_dst[303:288] := SaturateU16(a[351:320]) +tmp_dst[319:304] := SaturateU16(a[383:352]) +tmp_dst[335:320] := SaturateU16(b[287:256]) +tmp_dst[351:336] := SaturateU16(b[319:288]) +tmp_dst[367:352] := SaturateU16(b[351:320]) +tmp_dst[383:368] := SaturateU16(b[383:352]) +tmp_dst[399:384] := SaturateU16(a[415:384]) +tmp_dst[415:400] := SaturateU16(a[447:416]) +tmp_dst[431:416] := SaturateU16(a[479:448]) +tmp_dst[447:432] := SaturateU16(a[511:480]) +tmp_dst[463:448] := SaturateU16(b[415:384]) +tmp_dst[479:464] := SaturateU16(b[447:416]) +tmp_dst[495:480] := SaturateU16(b[479:448]) +tmp_dst[511:496] := SaturateU16(b[511:480]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := SaturateU16(a[31:0]) +tmp_dst[31:16] := SaturateU16(a[63:32]) +tmp_dst[47:32] := SaturateU16(a[95:64]) +tmp_dst[63:48] := SaturateU16(a[127:96]) +tmp_dst[79:64] := SaturateU16(b[31:0]) +tmp_dst[95:80] := SaturateU16(b[63:32]) +tmp_dst[111:96] := SaturateU16(b[95:64]) +tmp_dst[127:112] := SaturateU16(b[127:96]) +tmp_dst[143:128] := SaturateU16(a[159:128]) +tmp_dst[159:144] := SaturateU16(a[191:160]) +tmp_dst[175:160] := SaturateU16(a[223:192]) +tmp_dst[191:176] := SaturateU16(a[255:224]) +tmp_dst[207:192] := SaturateU16(b[159:128]) +tmp_dst[223:208] := SaturateU16(b[191:160]) +tmp_dst[239:224] := SaturateU16(b[223:192]) +tmp_dst[255:240] := SaturateU16(b[255:224]) +tmp_dst[271:256] := SaturateU16(a[287:256]) +tmp_dst[287:272] := SaturateU16(a[319:288]) +tmp_dst[303:288] := SaturateU16(a[351:320]) +tmp_dst[319:304] := SaturateU16(a[383:352]) +tmp_dst[335:320] := SaturateU16(b[287:256]) +tmp_dst[351:336] := SaturateU16(b[319:288]) +tmp_dst[367:352] := SaturateU16(b[351:320]) +tmp_dst[383:368] := SaturateU16(b[383:352]) +tmp_dst[399:384] := SaturateU16(a[415:384]) +tmp_dst[415:400] := SaturateU16(a[447:416]) +tmp_dst[431:416] := SaturateU16(a[479:448]) +tmp_dst[447:432] := SaturateU16(a[511:480]) +tmp_dst[463:448] := SaturateU16(b[415:384]) +tmp_dst[479:464] := SaturateU16(b[447:416]) +tmp_dst[495:480] := SaturateU16(b[479:448]) +tmp_dst[511:496] := SaturateU16(b[511:480]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst". + +dst[15:0] := SaturateU16(a[31:0]) +dst[31:16] := SaturateU16(a[63:32]) +dst[47:32] := SaturateU16(a[95:64]) +dst[63:48] := SaturateU16(a[127:96]) +dst[79:64] := SaturateU16(b[31:0]) +dst[95:80] := SaturateU16(b[63:32]) +dst[111:96] := SaturateU16(b[95:64]) +dst[127:112] := SaturateU16(b[127:96]) +dst[143:128] := SaturateU16(a[159:128]) +dst[159:144] := SaturateU16(a[191:160]) +dst[175:160] := SaturateU16(a[223:192]) +dst[191:176] := SaturateU16(a[255:224]) +dst[207:192] := SaturateU16(b[159:128]) +dst[223:208] := SaturateU16(b[191:160]) +dst[239:224] := SaturateU16(b[223:192]) +dst[255:240] := SaturateU16(b[255:224]) +dst[271:256] := SaturateU16(a[287:256]) +dst[287:272] := SaturateU16(a[319:288]) +dst[303:288] := SaturateU16(a[351:320]) +dst[319:304] := SaturateU16(a[383:352]) +dst[335:320] := SaturateU16(b[287:256]) +dst[351:336] := SaturateU16(b[319:288]) +dst[367:352] := SaturateU16(b[351:320]) +dst[383:368] := SaturateU16(b[383:352]) +dst[399:384] := SaturateU16(a[415:384]) +dst[415:400] := SaturateU16(a[447:416]) +dst[431:416] := SaturateU16(a[479:448]) +dst[447:432] := SaturateU16(a[511:480]) +dst[463:448] := SaturateU16(b[415:384]) +dst[479:464] := SaturateU16(b[447:416]) +dst[495:480] := SaturateU16(b[479:448]) +dst[511:496] := SaturateU16(b[511:480]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[7:0] := SaturateU8(a[15:0]) +tmp_dst[15:8] := SaturateU8(a[31:16]) +tmp_dst[23:16] := SaturateU8(a[47:32]) +tmp_dst[31:24] := SaturateU8(a[63:48]) +tmp_dst[39:32] := SaturateU8(a[79:64]) +tmp_dst[47:40] := SaturateU8(a[95:80]) +tmp_dst[55:48] := SaturateU8(a[111:96]) +tmp_dst[63:56] := SaturateU8(a[127:112]) +tmp_dst[71:64] := SaturateU8(b[15:0]) +tmp_dst[79:72] := SaturateU8(b[31:16]) +tmp_dst[87:80] := SaturateU8(b[47:32]) +tmp_dst[95:88] := SaturateU8(b[63:48]) +tmp_dst[103:96] := SaturateU8(b[79:64]) +tmp_dst[111:104] := SaturateU8(b[95:80]) +tmp_dst[119:112] := SaturateU8(b[111:96]) +tmp_dst[127:120] := SaturateU8(b[127:112]) +tmp_dst[135:128] := SaturateU8(a[143:128]) +tmp_dst[143:136] := SaturateU8(a[159:144]) +tmp_dst[151:144] := SaturateU8(a[175:160]) +tmp_dst[159:152] := SaturateU8(a[191:176]) +tmp_dst[167:160] := SaturateU8(a[207:192]) +tmp_dst[175:168] := SaturateU8(a[223:208]) +tmp_dst[183:176] := SaturateU8(a[239:224]) +tmp_dst[191:184] := SaturateU8(a[255:240]) +tmp_dst[199:192] := SaturateU8(b[143:128]) +tmp_dst[207:200] := SaturateU8(b[159:144]) +tmp_dst[215:208] := SaturateU8(b[175:160]) +tmp_dst[223:216] := SaturateU8(b[191:176]) +tmp_dst[231:224] := SaturateU8(b[207:192]) +tmp_dst[239:232] := SaturateU8(b[223:208]) +tmp_dst[247:240] := SaturateU8(b[239:224]) +tmp_dst[255:248] := SaturateU8(b[255:240]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[7:0] := SaturateU8(a[15:0]) +tmp_dst[15:8] := SaturateU8(a[31:16]) +tmp_dst[23:16] := SaturateU8(a[47:32]) +tmp_dst[31:24] := SaturateU8(a[63:48]) +tmp_dst[39:32] := SaturateU8(a[79:64]) +tmp_dst[47:40] := SaturateU8(a[95:80]) +tmp_dst[55:48] := SaturateU8(a[111:96]) +tmp_dst[63:56] := SaturateU8(a[127:112]) +tmp_dst[71:64] := SaturateU8(b[15:0]) +tmp_dst[79:72] := SaturateU8(b[31:16]) +tmp_dst[87:80] := SaturateU8(b[47:32]) +tmp_dst[95:88] := SaturateU8(b[63:48]) +tmp_dst[103:96] := SaturateU8(b[79:64]) +tmp_dst[111:104] := SaturateU8(b[95:80]) +tmp_dst[119:112] := SaturateU8(b[111:96]) +tmp_dst[127:120] := SaturateU8(b[127:112]) +tmp_dst[135:128] := SaturateU8(a[143:128]) +tmp_dst[143:136] := SaturateU8(a[159:144]) +tmp_dst[151:144] := SaturateU8(a[175:160]) +tmp_dst[159:152] := SaturateU8(a[191:176]) +tmp_dst[167:160] := SaturateU8(a[207:192]) +tmp_dst[175:168] := SaturateU8(a[223:208]) +tmp_dst[183:176] := SaturateU8(a[239:224]) +tmp_dst[191:184] := SaturateU8(a[255:240]) +tmp_dst[199:192] := SaturateU8(b[143:128]) +tmp_dst[207:200] := SaturateU8(b[159:144]) +tmp_dst[215:208] := SaturateU8(b[175:160]) +tmp_dst[223:216] := SaturateU8(b[191:176]) +tmp_dst[231:224] := SaturateU8(b[207:192]) +tmp_dst[239:232] := SaturateU8(b[223:208]) +tmp_dst[247:240] := SaturateU8(b[239:224]) +tmp_dst[255:248] := SaturateU8(b[255:240]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[7:0] := SaturateU8(a[15:0]) +tmp_dst[15:8] := SaturateU8(a[31:16]) +tmp_dst[23:16] := SaturateU8(a[47:32]) +tmp_dst[31:24] := SaturateU8(a[63:48]) +tmp_dst[39:32] := SaturateU8(a[79:64]) +tmp_dst[47:40] := SaturateU8(a[95:80]) +tmp_dst[55:48] := SaturateU8(a[111:96]) +tmp_dst[63:56] := SaturateU8(a[127:112]) +tmp_dst[71:64] := SaturateU8(b[15:0]) +tmp_dst[79:72] := SaturateU8(b[31:16]) +tmp_dst[87:80] := SaturateU8(b[47:32]) +tmp_dst[95:88] := SaturateU8(b[63:48]) +tmp_dst[103:96] := SaturateU8(b[79:64]) +tmp_dst[111:104] := SaturateU8(b[95:80]) +tmp_dst[119:112] := SaturateU8(b[111:96]) +tmp_dst[127:120] := SaturateU8(b[127:112]) +tmp_dst[135:128] := SaturateU8(a[143:128]) +tmp_dst[143:136] := SaturateU8(a[159:144]) +tmp_dst[151:144] := SaturateU8(a[175:160]) +tmp_dst[159:152] := SaturateU8(a[191:176]) +tmp_dst[167:160] := SaturateU8(a[207:192]) +tmp_dst[175:168] := SaturateU8(a[223:208]) +tmp_dst[183:176] := SaturateU8(a[239:224]) +tmp_dst[191:184] := SaturateU8(a[255:240]) +tmp_dst[199:192] := SaturateU8(b[143:128]) +tmp_dst[207:200] := SaturateU8(b[159:144]) +tmp_dst[215:208] := SaturateU8(b[175:160]) +tmp_dst[223:216] := SaturateU8(b[191:176]) +tmp_dst[231:224] := SaturateU8(b[207:192]) +tmp_dst[239:232] := SaturateU8(b[223:208]) +tmp_dst[247:240] := SaturateU8(b[239:224]) +tmp_dst[255:248] := SaturateU8(b[255:240]) +tmp_dst[263:256] := SaturateU8(a[271:256]) +tmp_dst[271:264] := SaturateU8(a[287:272]) +tmp_dst[279:272] := SaturateU8(a[303:288]) +tmp_dst[287:280] := SaturateU8(a[319:304]) +tmp_dst[295:288] := SaturateU8(a[335:320]) +tmp_dst[303:296] := SaturateU8(a[351:336]) +tmp_dst[311:304] := SaturateU8(a[367:352]) +tmp_dst[319:312] := SaturateU8(a[383:368]) +tmp_dst[327:320] := SaturateU8(b[271:256]) +tmp_dst[335:328] := SaturateU8(b[287:272]) +tmp_dst[343:336] := SaturateU8(b[303:288]) +tmp_dst[351:344] := SaturateU8(b[319:304]) +tmp_dst[359:352] := SaturateU8(b[335:320]) +tmp_dst[367:360] := SaturateU8(b[351:336]) +tmp_dst[375:368] := SaturateU8(b[367:352]) +tmp_dst[383:376] := SaturateU8(b[383:368]) +tmp_dst[391:384] := SaturateU8(a[399:384]) +tmp_dst[399:392] := SaturateU8(a[415:400]) +tmp_dst[407:400] := SaturateU8(a[431:416]) +tmp_dst[415:408] := SaturateU8(a[447:432]) +tmp_dst[423:416] := SaturateU8(a[463:448]) +tmp_dst[431:424] := SaturateU8(a[479:464]) +tmp_dst[439:432] := SaturateU8(a[495:480]) +tmp_dst[447:440] := SaturateU8(a[511:496]) +tmp_dst[455:448] := SaturateU8(b[399:384]) +tmp_dst[463:456] := SaturateU8(b[415:400]) +tmp_dst[471:464] := SaturateU8(b[431:416]) +tmp_dst[479:472] := SaturateU8(b[447:432]) +tmp_dst[487:480] := SaturateU8(b[463:448]) +tmp_dst[495:488] := SaturateU8(b[479:464]) +tmp_dst[503:496] := SaturateU8(b[495:480]) +tmp_dst[511:504] := SaturateU8(b[511:496]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[7:0] := SaturateU8(a[15:0]) +tmp_dst[15:8] := SaturateU8(a[31:16]) +tmp_dst[23:16] := SaturateU8(a[47:32]) +tmp_dst[31:24] := SaturateU8(a[63:48]) +tmp_dst[39:32] := SaturateU8(a[79:64]) +tmp_dst[47:40] := SaturateU8(a[95:80]) +tmp_dst[55:48] := SaturateU8(a[111:96]) +tmp_dst[63:56] := SaturateU8(a[127:112]) +tmp_dst[71:64] := SaturateU8(b[15:0]) +tmp_dst[79:72] := SaturateU8(b[31:16]) +tmp_dst[87:80] := SaturateU8(b[47:32]) +tmp_dst[95:88] := SaturateU8(b[63:48]) +tmp_dst[103:96] := SaturateU8(b[79:64]) +tmp_dst[111:104] := SaturateU8(b[95:80]) +tmp_dst[119:112] := SaturateU8(b[111:96]) +tmp_dst[127:120] := SaturateU8(b[127:112]) +tmp_dst[135:128] := SaturateU8(a[143:128]) +tmp_dst[143:136] := SaturateU8(a[159:144]) +tmp_dst[151:144] := SaturateU8(a[175:160]) +tmp_dst[159:152] := SaturateU8(a[191:176]) +tmp_dst[167:160] := SaturateU8(a[207:192]) +tmp_dst[175:168] := SaturateU8(a[223:208]) +tmp_dst[183:176] := SaturateU8(a[239:224]) +tmp_dst[191:184] := SaturateU8(a[255:240]) +tmp_dst[199:192] := SaturateU8(b[143:128]) +tmp_dst[207:200] := SaturateU8(b[159:144]) +tmp_dst[215:208] := SaturateU8(b[175:160]) +tmp_dst[223:216] := SaturateU8(b[191:176]) +tmp_dst[231:224] := SaturateU8(b[207:192]) +tmp_dst[239:232] := SaturateU8(b[223:208]) +tmp_dst[247:240] := SaturateU8(b[239:224]) +tmp_dst[255:248] := SaturateU8(b[255:240]) +tmp_dst[263:256] := SaturateU8(a[271:256]) +tmp_dst[271:264] := SaturateU8(a[287:272]) +tmp_dst[279:272] := SaturateU8(a[303:288]) +tmp_dst[287:280] := SaturateU8(a[319:304]) +tmp_dst[295:288] := SaturateU8(a[335:320]) +tmp_dst[303:296] := SaturateU8(a[351:336]) +tmp_dst[311:304] := SaturateU8(a[367:352]) +tmp_dst[319:312] := SaturateU8(a[383:368]) +tmp_dst[327:320] := SaturateU8(b[271:256]) +tmp_dst[335:328] := SaturateU8(b[287:272]) +tmp_dst[343:336] := SaturateU8(b[303:288]) +tmp_dst[351:344] := SaturateU8(b[319:304]) +tmp_dst[359:352] := SaturateU8(b[335:320]) +tmp_dst[367:360] := SaturateU8(b[351:336]) +tmp_dst[375:368] := SaturateU8(b[367:352]) +tmp_dst[383:376] := SaturateU8(b[383:368]) +tmp_dst[391:384] := SaturateU8(a[399:384]) +tmp_dst[399:392] := SaturateU8(a[415:400]) +tmp_dst[407:400] := SaturateU8(a[431:416]) +tmp_dst[415:408] := SaturateU8(a[447:432]) +tmp_dst[423:416] := SaturateU8(a[463:448]) +tmp_dst[431:424] := SaturateU8(a[479:464]) +tmp_dst[439:432] := SaturateU8(a[495:480]) +tmp_dst[447:440] := SaturateU8(a[511:496]) +tmp_dst[455:448] := SaturateU8(b[399:384]) +tmp_dst[463:456] := SaturateU8(b[415:400]) +tmp_dst[471:464] := SaturateU8(b[431:416]) +tmp_dst[479:472] := SaturateU8(b[447:432]) +tmp_dst[487:480] := SaturateU8(b[463:448]) +tmp_dst[495:488] := SaturateU8(b[479:464]) +tmp_dst[503:496] := SaturateU8(b[495:480]) +tmp_dst[511:504] := SaturateU8(b[511:496]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst". + +dst[7:0] := SaturateU8(a[15:0]) +dst[15:8] := SaturateU8(a[31:16]) +dst[23:16] := SaturateU8(a[47:32]) +dst[31:24] := SaturateU8(a[63:48]) +dst[39:32] := SaturateU8(a[79:64]) +dst[47:40] := SaturateU8(a[95:80]) +dst[55:48] := SaturateU8(a[111:96]) +dst[63:56] := SaturateU8(a[127:112]) +dst[71:64] := SaturateU8(b[15:0]) +dst[79:72] := SaturateU8(b[31:16]) +dst[87:80] := SaturateU8(b[47:32]) +dst[95:88] := SaturateU8(b[63:48]) +dst[103:96] := SaturateU8(b[79:64]) +dst[111:104] := SaturateU8(b[95:80]) +dst[119:112] := SaturateU8(b[111:96]) +dst[127:120] := SaturateU8(b[127:112]) +dst[135:128] := SaturateU8(a[143:128]) +dst[143:136] := SaturateU8(a[159:144]) +dst[151:144] := SaturateU8(a[175:160]) +dst[159:152] := SaturateU8(a[191:176]) +dst[167:160] := SaturateU8(a[207:192]) +dst[175:168] := SaturateU8(a[223:208]) +dst[183:176] := SaturateU8(a[239:224]) +dst[191:184] := SaturateU8(a[255:240]) +dst[199:192] := SaturateU8(b[143:128]) +dst[207:200] := SaturateU8(b[159:144]) +dst[215:208] := SaturateU8(b[175:160]) +dst[223:216] := SaturateU8(b[191:176]) +dst[231:224] := SaturateU8(b[207:192]) +dst[239:232] := SaturateU8(b[223:208]) +dst[247:240] := SaturateU8(b[239:224]) +dst[255:248] := SaturateU8(b[255:240]) +dst[263:256] := SaturateU8(a[271:256]) +dst[271:264] := SaturateU8(a[287:272]) +dst[279:272] := SaturateU8(a[303:288]) +dst[287:280] := SaturateU8(a[319:304]) +dst[295:288] := SaturateU8(a[335:320]) +dst[303:296] := SaturateU8(a[351:336]) +dst[311:304] := SaturateU8(a[367:352]) +dst[319:312] := SaturateU8(a[383:368]) +dst[327:320] := SaturateU8(b[271:256]) +dst[335:328] := SaturateU8(b[287:272]) +dst[343:336] := SaturateU8(b[303:288]) +dst[351:344] := SaturateU8(b[319:304]) +dst[359:352] := SaturateU8(b[335:320]) +dst[367:360] := SaturateU8(b[351:336]) +dst[375:368] := SaturateU8(b[367:352]) +dst[383:376] := SaturateU8(b[383:368]) +dst[391:384] := SaturateU8(a[399:384]) +dst[399:392] := SaturateU8(a[415:400]) +dst[407:400] := SaturateU8(a[431:416]) +dst[415:408] := SaturateU8(a[447:432]) +dst[423:416] := SaturateU8(a[463:448]) +dst[431:424] := SaturateU8(a[479:464]) +dst[439:432] := SaturateU8(a[495:480]) +dst[447:440] := SaturateU8(a[511:496]) +dst[455:448] := SaturateU8(b[399:384]) +dst[463:456] := SaturateU8(b[415:400]) +dst[471:464] := SaturateU8(b[431:416]) +dst[479:472] := SaturateU8(b[447:432]) +dst[487:480] := SaturateU8(b[463:448]) +dst[495:488] := SaturateU8(b[479:464]) +dst[503:496] := SaturateU8(b[495:480]) +dst[511:504] := SaturateU8(b[511:496]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + b[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + b[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := a[i+7:i] + b[i+7:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + b[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + b[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + b[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] + b[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + b[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + b[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := a[i+15:i] + b[i+15:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + b[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + b[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + b[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] + b[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*128 + tmp[255:0] := ((a[i+127:i] << 128)[255:0] OR b[i+127:i]) >> (imm8*8) + tmp_dst[i+127:i] := tmp[127:0] +ENDFOR +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*128 + tmp[255:0] := ((a[i+127:i] << 128)[255:0] OR b[i+127:i]) >> (imm8*8) + tmp_dst[i+127:i] := tmp[127:0] +ENDFOR +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst". + +FOR j := 0 to 3 + i := j*128 + tmp[255:0] := ((a[i+127:i] << 128)[255:0] OR b[i+127:i]) >> (imm8*8) + dst[i+127:i] := tmp[127:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*128 + tmp[255:0] := ((a[i+127:i] << 128)[255:0] OR b[i+127:i]) >> (imm8*8) + tmp_dst[i+127:i] := tmp[127:0] +ENDFOR +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*128 + tmp[255:0] := ((a[i+127:i] << 128)[255:0] OR b[i+127:i]) >> (imm8*8) + tmp_dst[i+127:i] := tmp[127:0] +ENDFOR +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[255:0] := ((a[127:0] << 128)[255:0] OR b[127:0]) >> (imm8*8) +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Concatenate pairs of 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[255:0] := ((a[127:0] << 128)[255:0] OR b[127:0]) >> (imm8*8) +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := b[i+7:i] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := b[i+7:i] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Blend packed 8-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := b[i+7:i] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := b[i+15:i] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := b[i+15:i] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Blend packed 16-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := b[i+15:i] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + + Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Set + + + + + Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Set + + + + Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + + Broadcast 8-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + Broadcast the low packed 8-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + Broadcast 8-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[7:0] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + Broadcast 16-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Set + + + + + Broadcast 16-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Set + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Set + + + + Broadcast the low packed 16-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + + Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed signed 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*8 + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 63 + i := j*8 + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + + Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*8 + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed unsigned 8-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] OP b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] == b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] >= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] > b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] <= b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] < b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 8-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ( a[i+7:i] != b[i+7:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + + Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed unsigned 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed unsigned 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*16 + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 31 + i := j*16 + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + + Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*16 + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + + Compare packed signed 16-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] OP b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] == b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] >= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] > b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] <= b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] < b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compare packed signed 16-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ( a[i+15:i] != b[i+15:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + off := 16*idx[i+3:i] + dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := idx[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + off := 16*idx[i+3:i] + dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + off := 16*idx[i+3:i] + dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + off := 16*idx[i+3:i] + dst[i+15:i] := idx[i+4] ? b[off+15:off] : a[off+15:off] +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + off := 16*idx[i+4:i] + dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := idx[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + off := 16*idx[i+4:i] + dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + off := 16*idx[i+4:i] + dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + off := 16*idx[i+4:i] + dst[i+15:i] := idx[i+5] ? b[off+15:off] : a[off+15:off] +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + off := 16*idx[i+2:i] + dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := idx[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + off := 16*idx[i+2:i] + dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + off := 16*idx[i+2:i] + dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + off := 16*idx[i+2:i] + dst[i+15:i] := idx[i+3] ? b[off+15:off] : a[off+15:off] +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + id := idx[i+3:i]*16 + IF k[j] + dst[i+15:i] := a[id+15:id] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + id := idx[i+3:i]*16 + IF k[j] + dst[i+15:i] := a[id+15:id] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + id := idx[i+3:i]*16 + dst[i+15:i] := a[id+15:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + id := idx[i+4:i]*16 + IF k[j] + dst[i+15:i] := a[id+15:id] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + id := idx[i+4:i]*16 + IF k[j] + dst[i+15:i] := a[id+15:id] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Shuffle 16-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + id := idx[i+4:i]*16 + dst[i+15:i] := a[id+15:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + id := idx[i+2:i]*16 + IF k[j] + dst[i+15:i] := a[id+15:id] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + id := idx[i+2:i]*16 + IF k[j] + dst[i+15:i] := a[id+15:id] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + Shuffle 16-bit integers in "a" using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + id := idx[i+2:i]*16 + dst[i+15:i] := a[id+15:id] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply packed unsigned 8-bit integers in "a" by packed signed 8-bit integers in "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a". + +FOR j := 0 to 31 + i := j*8 + IF a[i+7] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a". + +FOR j := 0 to 63 + i := j*8 + IF a[i+7] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 8-bit integer in "a". + +FOR j := 0 to 15 + i := j*8 + IF a[i+7] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := 0xFF + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := 0xFF + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + AVX512VL + Miscellaneous + + + Set each packed 8-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := 0xFF + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := 0xFFFF + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := 0xFFFF + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + Set each packed 16-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := 0xFFFF + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := 16*j + l := 8*j + dst[l+7:l] := Saturate8(a[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Store + + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := 16*j + l := 8*j + dst[l+7:l] := Saturate8(a[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Store + + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 16*j + l := 8*j + dst[l+7:l] := Saturate8(a[i+15:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Store + + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Convert packed signed 16-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := SignExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := SignExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + l := j*16 + dst[l+15:l] := SignExtend16(a[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := SignExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := SignExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := SignExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := SignExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := 16*j + l := 8*j + dst[l+7:l] := SaturateU8(a[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Store + + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := 16*j + l := 8*j + dst[l+7:l] := SaturateU8(a[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Store + + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 16*j + l := 8*j + dst[l+7:l] := SaturateU8(a[i+15:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Store + + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Convert packed unsigned 16-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a". + +FOR j := 0 to 15 + i := j*16 + IF a[i+15] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a". + +FOR j := 0 to 31 + i := j*16 + IF a[i+15] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 16-bit integer in "a". + +FOR j := 0 to 7 + i := j*16 + IF a[i+15] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 15 + i := 16*j + l := 8*j + dst[l+7:l] := Truncate8(a[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Store + + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 31 + i := 16*j + l := 8*j + dst[l+7:l] := Truncate8(a[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + Store + + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 16*j + l := 8*j + dst[l+7:l] := Truncate8(a[i+15:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+15:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + Store + + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+15:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Convert packed 16-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 16*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+15:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := ZeroExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := ZeroExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + l := j*16 + dst[l+15:l] := ZeroExtend16(a[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := ZeroExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Convert + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := ZeroExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := ZeroExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Convert + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*8 + l := j*16 + IF k[j] + dst[l+15:l] := ZeroExtend16(a[i+7:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst". + +FOR j := 0 to 31 + i := j*16 + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 31 + i := j*16 + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 31 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 31 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce eight unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst". + +FOR j := 0 to 63 + i := j*8 + tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i]) +ENDFOR +FOR j := 0 to 7 + i := j*64 + dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \ + tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56] + dst[i+63:i+16] := 0 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[4:0] := b[i+3:i] + (j & 0x10) + dst[i+7:i] := a[index*8+7:index*8] + FI + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[4:0] := b[i+3:i] + (j & 0x10) + dst[i+7:i] := a[index*8+7:index*8] + FI + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 8-bit integers in "a" within 128-bit lanes using the control in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[5:0] := b[i+3:i] + (j & 0x30) + dst[i+7:i] := a[index*8+7:index*8] + FI + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[5:0] := b[i+3:i] + (j & 0x30) + dst[i+7:i] := a[index*8+7:index*8] + FI + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[5:0] := b[i+3:i] + (j & 0x30) + dst[i+7:i] := a[index*8+7:index*8] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[3:0] := b[i+3:i] + dst[i+7:i] := a[index*8+7:index*8] + FI + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[3:0] := b[i+3:i] + dst[i+7:i] := a[index*8+7:index*8] + FI + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[63:0] := a[63:0] +tmp_dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +tmp_dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +tmp_dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +tmp_dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +tmp_dst[191:128] := a[191:128] +tmp_dst[207:192] := (a >> (imm8[1:0] * 16))[207:192] +tmp_dst[223:208] := (a >> (imm8[3:2] * 16))[207:192] +tmp_dst[239:224] := (a >> (imm8[5:4] * 16))[207:192] +tmp_dst[255:240] := (a >> (imm8[7:6] * 16))[207:192] +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[63:0] := a[63:0] +tmp_dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +tmp_dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +tmp_dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +tmp_dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +tmp_dst[191:128] := a[191:128] +tmp_dst[207:192] := (a >> (imm8[1:0] * 16))[207:192] +tmp_dst[223:208] := (a >> (imm8[3:2] * 16))[207:192] +tmp_dst[239:224] := (a >> (imm8[5:4] * 16))[207:192] +tmp_dst[255:240] := (a >> (imm8[7:6] * 16))[207:192] +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[63:0] := a[63:0] +tmp_dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +tmp_dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +tmp_dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +tmp_dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +tmp_dst[191:128] := a[191:128] +tmp_dst[207:192] := (a >> (imm8[1:0] * 16))[207:192] +tmp_dst[223:208] := (a >> (imm8[3:2] * 16))[207:192] +tmp_dst[239:224] := (a >> (imm8[5:4] * 16))[207:192] +tmp_dst[255:240] := (a >> (imm8[7:6] * 16))[207:192] +tmp_dst[319:256] := a[319:256] +tmp_dst[335:320] := (a >> (imm8[1:0] * 16))[335:320] +tmp_dst[351:336] := (a >> (imm8[3:2] * 16))[335:320] +tmp_dst[367:352] := (a >> (imm8[5:4] * 16))[335:320] +tmp_dst[383:368] := (a >> (imm8[7:6] * 16))[335:320] +tmp_dst[447:384] := a[447:384] +tmp_dst[463:448] := (a >> (imm8[1:0] * 16))[463:448] +tmp_dst[479:464] := (a >> (imm8[3:2] * 16))[463:448] +tmp_dst[495:480] := (a >> (imm8[5:4] * 16))[463:448] +tmp_dst[511:496] := (a >> (imm8[7:6] * 16))[463:448] +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[63:0] := a[63:0] +tmp_dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +tmp_dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +tmp_dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +tmp_dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +tmp_dst[191:128] := a[191:128] +tmp_dst[207:192] := (a >> (imm8[1:0] * 16))[207:192] +tmp_dst[223:208] := (a >> (imm8[3:2] * 16))[207:192] +tmp_dst[239:224] := (a >> (imm8[5:4] * 16))[207:192] +tmp_dst[255:240] := (a >> (imm8[7:6] * 16))[207:192] +tmp_dst[319:256] := a[319:256] +tmp_dst[335:320] := (a >> (imm8[1:0] * 16))[335:320] +tmp_dst[351:336] := (a >> (imm8[3:2] * 16))[335:320] +tmp_dst[367:352] := (a >> (imm8[5:4] * 16))[335:320] +tmp_dst[383:368] := (a >> (imm8[7:6] * 16))[335:320] +tmp_dst[447:384] := a[447:384] +tmp_dst[463:448] := (a >> (imm8[1:0] * 16))[463:448] +tmp_dst[479:464] := (a >> (imm8[3:2] * 16))[463:448] +tmp_dst[495:480] := (a >> (imm8[5:4] * 16))[463:448] +tmp_dst[511:496] := (a >> (imm8[7:6] * 16))[463:448] +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the high 64 bits of 128-bit lanes of "dst", with the low 64 bits of 128-bit lanes being copied from from "a" to "dst". + +dst[63:0] := a[63:0] +dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +dst[191:128] := a[191:128] +dst[207:192] := (a >> (imm8[1:0] * 16))[207:192] +dst[223:208] := (a >> (imm8[3:2] * 16))[207:192] +dst[239:224] := (a >> (imm8[5:4] * 16))[207:192] +dst[255:240] := (a >> (imm8[7:6] * 16))[207:192] +dst[319:256] := a[319:256] +dst[335:320] := (a >> (imm8[1:0] * 16))[335:320] +dst[351:336] := (a >> (imm8[3:2] * 16))[335:320] +dst[367:352] := (a >> (imm8[5:4] * 16))[335:320] +dst[383:368] := (a >> (imm8[7:6] * 16))[335:320] +dst[447:384] := a[447:384] +dst[463:448] := (a >> (imm8[1:0] * 16))[463:448] +dst[479:464] := (a >> (imm8[3:2] * 16))[463:448] +dst[495:480] := (a >> (imm8[5:4] * 16))[463:448] +dst[511:496] := (a >> (imm8[7:6] * 16))[463:448] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[63:0] := a[63:0] +tmp_dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +tmp_dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +tmp_dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +tmp_dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[63:0] := a[63:0] +tmp_dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +tmp_dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +tmp_dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +tmp_dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +tmp_dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +tmp_dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +tmp_dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +tmp_dst[127:64] := a[127:64] +tmp_dst[143:128] := (a >> (imm8[1:0] * 16))[143:128] +tmp_dst[159:144] := (a >> (imm8[3:2] * 16))[143:128] +tmp_dst[175:160] := (a >> (imm8[5:4] * 16))[143:128] +tmp_dst[191:176] := (a >> (imm8[7:6] * 16))[143:128] +tmp_dst[255:192] := a[255:192] +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +tmp_dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +tmp_dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +tmp_dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +tmp_dst[127:64] := a[127:64] +tmp_dst[143:128] := (a >> (imm8[1:0] * 16))[143:128] +tmp_dst[159:144] := (a >> (imm8[3:2] * 16))[143:128] +tmp_dst[175:160] := (a >> (imm8[5:4] * 16))[143:128] +tmp_dst[191:176] := (a >> (imm8[7:6] * 16))[143:128] +tmp_dst[255:192] := a[255:192] +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +tmp_dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +tmp_dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +tmp_dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +tmp_dst[127:64] := a[127:64] +tmp_dst[143:128] := (a >> (imm8[1:0] * 16))[143:128] +tmp_dst[159:144] := (a >> (imm8[3:2] * 16))[143:128] +tmp_dst[175:160] := (a >> (imm8[5:4] * 16))[143:128] +tmp_dst[191:176] := (a >> (imm8[7:6] * 16))[143:128] +tmp_dst[255:192] := a[255:192] +tmp_dst[271:256] := (a >> (imm8[1:0] * 16))[271:256] +tmp_dst[287:272] := (a >> (imm8[3:2] * 16))[271:256] +tmp_dst[303:288] := (a >> (imm8[5:4] * 16))[271:256] +tmp_dst[319:304] := (a >> (imm8[7:6] * 16))[271:256] +tmp_dst[383:320] := a[383:320] +tmp_dst[399:384] := (a >> (imm8[1:0] * 16))[399:384] +tmp_dst[415:400] := (a >> (imm8[3:2] * 16))[399:384] +tmp_dst[431:416] := (a >> (imm8[5:4] * 16))[399:384] +tmp_dst[447:432] := (a >> (imm8[7:6] * 16))[399:384] +tmp_dst[511:448] := a[511:448] +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +tmp_dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +tmp_dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +tmp_dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +tmp_dst[127:64] := a[127:64] +tmp_dst[143:128] := (a >> (imm8[1:0] * 16))[143:128] +tmp_dst[159:144] := (a >> (imm8[3:2] * 16))[143:128] +tmp_dst[175:160] := (a >> (imm8[5:4] * 16))[143:128] +tmp_dst[191:176] := (a >> (imm8[7:6] * 16))[143:128] +tmp_dst[255:192] := a[255:192] +tmp_dst[271:256] := (a >> (imm8[1:0] * 16))[271:256] +tmp_dst[287:272] := (a >> (imm8[3:2] * 16))[271:256] +tmp_dst[303:288] := (a >> (imm8[5:4] * 16))[271:256] +tmp_dst[319:304] := (a >> (imm8[7:6] * 16))[271:256] +tmp_dst[383:320] := a[383:320] +tmp_dst[399:384] := (a >> (imm8[1:0] * 16))[399:384] +tmp_dst[415:400] := (a >> (imm8[3:2] * 16))[399:384] +tmp_dst[431:416] := (a >> (imm8[5:4] * 16))[399:384] +tmp_dst[447:432] := (a >> (imm8[7:6] * 16))[399:384] +tmp_dst[511:448] := a[511:448] +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of "a" using the control in "imm8". Store the results in the low 64 bits of 128-bit lanes of "dst", with the high 64 bits of 128-bit lanes being copied from from "a" to "dst". + +dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +dst[127:64] := a[127:64] +dst[143:128] := (a >> (imm8[1:0] * 16))[143:128] +dst[159:144] := (a >> (imm8[3:2] * 16))[143:128] +dst[175:160] := (a >> (imm8[5:4] * 16))[143:128] +dst[191:176] := (a >> (imm8[7:6] * 16))[143:128] +dst[255:192] := a[255:192] +dst[271:256] := (a >> (imm8[1:0] * 16))[271:256] +dst[287:272] := (a >> (imm8[3:2] * 16))[271:256] +dst[303:288] := (a >> (imm8[5:4] * 16))[271:256] +dst[319:304] := (a >> (imm8[7:6] * 16))[271:256] +dst[383:320] := a[383:320] +dst[399:384] := (a >> (imm8[1:0] * 16))[399:384] +dst[415:400] := (a >> (imm8[3:2] * 16))[399:384] +dst[431:416] := (a >> (imm8[5:4] * 16))[399:384] +dst[447:432] := (a >> (imm8[7:6] * 16))[399:384] +dst[511:448] := a[511:448] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +tmp_dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +tmp_dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +tmp_dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +tmp_dst[127:64] := a[127:64] +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst", using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +tmp_dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +tmp_dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +tmp_dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +tmp_dst[127:64] := a[127:64] +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift 128-bit lanes in "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst". + +tmp := imm8[7:0] +IF tmp > 15 + tmp := 16 +FI +dst[127:0] := a[127:0] << (tmp*8) +dst[255:128] := a[255:128] << (tmp*8) +dst[383:256] := a[383:256] << (tmp*8) +dst[511:384] := a[511:384] << (tmp*8) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0) + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift 128-bit lanes in "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst". + +tmp := imm8[7:0] +IF tmp > 15 + tmp := 16 +FI +dst[127:0] := a[127:0] >> (tmp*8) +dst[255:128] := a[255:128] >> (tmp*8) +dst[383:256] := a[383:256] >> (tmp*8) +dst[511:384] := a[511:384] >> (tmp*8) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF count[i+15:i] < 16 + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Shift + + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] - b[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] - b[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] - b[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] - b[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := a[i+7:i] - b[i+7:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] - b[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[i+7:i] - b[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] - b[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] - b[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] - b[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] - b[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Arithmetic + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := a[i+15:i] - b[i+15:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] - b[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Arithmetic + + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[i+15:i] - b[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 31 + i := j*8 + k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 63 + i := j*8 + k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise AND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 15 + i := j*8 + k[j] := ((a[i+7:i] AND b[i+7:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 15 + i := j*16 + k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 31 + i := j*16 + k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise AND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 7 + i := j*16 + k[j] := ((a[i+15:i] AND b[i+15:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 31 + i := j*8 + IF k1[j] + k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 31 + i := j*8 + k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 63 + i := j*8 + IF k1[j] + k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 63 + i := j*8 + k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 15 + i := j*8 + IF k1[j] + k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise NAND of packed 8-bit integers in "a" and "b", producing intermediate 8-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 15 + i := j*8 + k[j] := ((a[i+7:i] AND b[i+7:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 15 + i := j*16 + IF k1[j] + k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 15 + i := j*16 + k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + + Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 31 + i := j*16 + IF k1[j] + k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512BW + Compare + + + + Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 31 + i := j*16 + k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + + Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 7 + i := j*16 + IF k1[j] + k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512BW + Compare + + + + Compute the bitwise NAND of packed 16-bit integers in "a" and "b", producing intermediate 16-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 7 + i := j*16 + k[j] := ((a[i+15:i] AND b[i+15:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Unpack and interleave 8-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_BYTES(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_HIGH_BYTES(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_HIGH_BYTES(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Unpack and interleave 16-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_WORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_HIGH_WORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_HIGH_WORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128]) +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384]) +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Unpack and interleave 8-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_BYTES(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_BYTES(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_BYTES(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := tmp_dst[i+7:i] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128]) +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + + Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384]) +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Miscellaneous + + + + Unpack and interleave 16-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_WORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_WORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_WORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + + Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Miscellaneous + + + + + Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := tmp_dst[i+15:i] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Store + + + + Store 512-bits (composed of 32 packed 16-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512BW + Store + + + + Store 512-bits (composed of 64 packed 8-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + Store 256-bits (composed of 16 packed 16-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + Store 256-bits (composed of 32 packed 8-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + Store 128-bits (composed of 8 packed 16-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Store + + + + Store 128-bits (composed of 16 packed 8-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

immintrin.h

+ + + Integer + AVX512BW + Load + + + Load 512-bits (composed of 32 packed 16-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512BW + Load + + + Load 512-bits (composed of 64 packed 8-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + Load 256-bits (composed of 16 packed 16-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + Load 256-bits (composed of 32 packed 8-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + Load 128-bits (composed of 8 packed 16-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512BW + Load + + + Load 128-bits (composed of 16 packed 8-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Add 32-bit masks in "a" and "b", and store the result in "k". + +k[31:0] := a[31:0] + b[31:0] +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Add 64-bit masks in "a" and "b", and store the result in "k". + +k[63:0] := a[63:0] + b[63:0] +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise AND of 32-bit masks "a" and "b", and store the result in "k". + +k[31:0] := a[31:0] AND b[31:0] +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise AND of 64-bit masks "a" and "b", and store the result in "k". + +k[63:0] := a[63:0] AND b[63:0] +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise NOT of 32-bit masks "a" and then AND with "b", and store the result in "k". + +k[31:0] := (NOT a[31:0]) AND b[31:0] +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise NOT of 64-bit masks "a" and then AND with "b", and store the result in "k". + +k[63:0] := (NOT a[63:0]) AND b[63:0] +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + Compute the bitwise NOT of 32-bit mask "a", and store the result in "k". + +k[31:0] := NOT a[31:0] +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + Compute the bitwise NOT of 64-bit mask "a", and store the result in "k". + +k[63:0] := NOT a[63:0] +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise OR of 32-bit masks "a" and "b", and store the result in "k". + +k[31:0] := a[31:0] OR b[31:0] +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise OR of 64-bit masks "a" and "b", and store the result in "k". + +k[63:0] := a[63:0] OR b[63:0] +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise XNOR of 32-bit masks "a" and "b", and store the result in "k". + +k[31:0] := NOT (a[31:0] XOR b[31:0]) +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise XNOR of 64-bit masks "a" and "b", and store the result in "k". + +k[63:0] := NOT (a[63:0] XOR b[63:0]) +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise XOR of 32-bit masks "a" and "b", and store the result in "k". + +k[31:0] := a[31:0] XOR b[31:0] +k[MAX:32] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise XOR of 64-bit masks "a" and "b", and store the result in "k". + +k[63:0] := a[63:0] XOR b[63:0] +k[MAX:64] := 0 + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Shift the bits of 32-bit mask "a" left by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 31 + k[31:0] := a[31:0] << count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Shift the bits of 64-bit mask "a" left by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 63 + k[63:0] := a[63:0] << count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Shift the bits of 32-bit mask "a" right by "count" while shifting in zeros, and store the least significant 32 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 31 + k[31:0] := a[31:0] >> count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Shift the bits of 64-bit mask "a" right by "count" while shifting in zeros, and store the least significant 64 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 63 + k[63:0] := a[63:0] >> count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Load + + + Load 32-bit mask from memory into "k". + +k[31:0] := MEM[mem_addr+31:mem_addr] + + +

immintrin.h

+ + + Mask + AVX512BW + Load + + + Load 64-bit mask from memory into "k". + +k[63:0] := MEM[mem_addr+63:mem_addr] + + +

immintrin.h

+ + + Mask + AVX512BW + Store + + + + Store 32-bit mask from "a" into memory. + +MEM[mem_addr+31:mem_addr] := a[31:0] + + +

immintrin.h

+ + + Mask + AVX512BW + Store + + + + Store 64-bit mask from "a" into memory. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + + Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones". + +tmp[31:0] := a[31:0] OR b[31:0] +IF tmp[31:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +IF tmp[31:0] == 0xFFFFFFFF + MEM[all_ones+7:all_ones] := 1 +ELSE + MEM[all_ones+7:all_ones] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[31:0] := a[31:0] OR b[31:0] +IF tmp[31:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise OR of 32-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst". + +tmp[31:0] := a[31:0] OR b[31:0] +IF tmp[31:0] == 0xFFFFFFFF + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + + Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones". + +tmp[63:0] := a[63:0] OR b[63:0] +IF tmp[63:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +IF tmp[7:0] == 0xFFFFFFFFFFFFFFFF + MEM[all_ones+7:all_ones] := 1 +ELSE + MEM[all_ones+7:all_ones] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[63:0] := a[63:0] OR b[63:0] +IF tmp[63:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise OR of 64-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst". + +tmp[63:0] := a[63:0] OR b[63:0] +IF tmp[63:0] == 0xFFFFFFFFFFFFFFFF + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + + Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not". + +tmp1[31:0] := a[31:0] AND b[31:0] +IF tmp1[31:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +tmp2[31:0] := (NOT a[31:0]) AND b[31:0] +IF tmp2[31:0] == 0x0 + MEM[and_not+7:and_not] := 1 +ELSE + MEM[and_not+7:and_not] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise AND of 32-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". + +tmp[31:0] := a[31:0] AND b[31:0] +IF tmp[31:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise NOT of 32-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[31:0] := (NOT a[31:0]) AND b[31:0] +IF tmp[31:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + + Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not". + +tmp1[63:0] := a[63:0] AND b[63:0] +IF tmp1[63:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +tmp2[63:0] := (NOT a[63:0]) AND b[63:0] +IF tmp2[63:0] == 0x0 + MEM[and_not+7:and_not] := 1 +ELSE + MEM[and_not+7:and_not] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise AND of 64-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". + +tmp[63:0] := a[63:0] AND b[63:0] +IF tmp[63:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512BW + Mask + + + + Compute the bitwise NOT of 64-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[63:0] := (NOT a[63:0]) AND b[63:0] +IF tmp[63:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + AVX512BW + Mask + + + Convert 32-bit mask "a" into an integer value, and store the result in "dst". + +dst := ZeroExtend32(a[31:0]) + + +

immintrin.h

+ + + AVX512BW + Mask + + + Convert 64-bit mask "a" into an integer value, and store the result in "dst". + +dst := ZeroExtend64(a[63:0]) + + +

immintrin.h

+ + + AVX512BW + Mask + + + Convert integer value "a" into an 32-bit mask, and store the result in "k". + +k := ZeroExtend32(a[31:0]) + + +

immintrin.h

+ + + AVX512BW + Mask + + + Convert integer value "a" into an 64-bit mask, and store the result in "k". + +k := ZeroExtend64(a[63:0]) + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Miscellaneous + + + Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ZeroExtend64(k[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Miscellaneous + + + Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ZeroExtend64(k[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Miscellaneous + + + Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ZeroExtend32(k[15:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Miscellaneous + + + Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ZeroExtend32(k[15:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 7 + i := j*32 + FOR k := 0 to j-1 + m := k*32 + dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 7 + i := j*32 + IF k[j] + FOR l := 0 to j-1 + m := l*32 + dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 7 + i := j*32 + IF k[j] + FOR l := 0 to j-1 + m := l*32 + dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 3 + i := j*32 + FOR k := 0 to j-1 + m := k*32 + dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 3 + i := j*32 + IF k[j] + FOR l := 0 to j-1 + m := l*32 + dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 3 + i := j*32 + IF k[j] + FOR l := 0 to j-1 + m := l*32 + dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 3 + i := j*64 + FOR k := 0 to j-1 + m := k*64 + dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 3 + i := j*64 + IF k[j] + FOR l := 0 to j-1 + m := l*64 + dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 3 + i := j*64 + IF k[j] + FOR l := 0 to j-1 + m := l*64 + dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 1 + i := j*64 + FOR k := 0 to j-1 + m := k*64 + dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 1 + i := j*64 + IF k[j] + FOR l := 0 to j-1 + m := l*64 + dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Compare + + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 1 + i := j*64 + IF k[j] + FOR l := 0 to j-1 + m := l*64 + dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512CD + Bit Manipulation + + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Swizzle + + + Broadcast the low 8-bits from input mask "k" to all 64-bit elements of "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ZeroExtend64(k[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Swizzle + + + Broadcast the low 16-bits from input mask "k" to all 32-bit elements of "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ZeroExtend32(k[15:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Compare + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 15 + i := j*32 + FOR k := 0 to j-1 + m := k*32 + dst[i+k] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Compare + + + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 15 + i := j*32 + IF k[j] + FOR l := 0 to j-1 + m := l*32 + dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Compare + + + + Test each 32-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 15 + i := j*32 + IF k[j] + FOR l := 0 to j-1 + m := l*32 + dst[i+l] := (a[i+31:i] == a[m+31:m]) ? 1 : 0 + ENDFOR + dst[i+31:i+j] := 0 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Compare + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit. Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 7 + i := j*64 + FOR k := 0 to j-1 + m := k*64 + dst[i+k] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Compare + + + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 7 + i := j*64 + IF k[j] + FOR l := 0 to j-1 + m := l*64 + dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Compare + + + + Test each 64-bit element of "a" for equality with all other elements in "a" closer to the least significant bit using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). Each element's comparison forms a zero extended bit vector in "dst". + +FOR j := 0 to 7 + i := j*64 + IF k[j] + FOR l := 0 to j-1 + m := l*64 + dst[i+l] := (a[i+63:i] == a[m+63:m]) ? 1 : 0 + ENDFOR + dst[i+63:i+j] := 0 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Bit Manipulation + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Bit Manipulation + + + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Bit Manipulation + + + + Counts the number of leading zero bits in each packed 32-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp := 31 + dst[i+31:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+31:i] := dst[i+31:i] + 1 + OD + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Bit Manipulation + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Bit Manipulation + + + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512CD + Bit Manipulation + + + + Counts the number of leading zero bits in each packed 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp := 63 + dst[i+63:i] := 0 + DO WHILE (tmp >= 0 AND a[i+tmp] == 0) + tmp := tmp - 1 + dst[i+63:i] := dst[i+63:i] + 1 + OD + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*32 + n := (j % 2)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + n := (j % 2)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Broadcast the lower 2 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + n := (j % 8)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 8)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Broadcast the 8 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 8)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*64 + n := (j % 2)*64 + dst[i+63:i] := a[n+63:n] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + n := (j % 2)*64 + dst[i+63:i] := a[n+63:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Broadcast the 2 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst. + +FOR j := 0 to 7 + i := j*32 + n := (j % 2)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst. + +FOR j := 0 to 15 + i := j*32 + n := (j % 2)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst. + +FOR j := 0 to 3 + i := j*32 + n := (j % 2)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + Broadcast the lower 2 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + n := (j % 2)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + n := (j % 8)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 8)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + Broadcast the 8 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 8)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*64 + n := (j % 2)*64 + dst[i+63:i] := a[n+63:n] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + + Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + n := (j % 2)*64 + dst[i+63:i] := a[n+63:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + Broadcast the 2 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 2)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed signed 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_Int64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_FP64_To_UInt64_Truncate(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_Int64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 64-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_FP32_To_UInt64_Truncate(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512DQ + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_Int64_To_FP32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[255:0] := a[255:0] +1: dst[255:0] := a[511:256] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[1:0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +2: dst[127:0] := a[383:256] +3: dst[127:0] := a[511:384] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + + Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[255:0] := a[255:0] +1: dst[255:0] := a[511:256] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + + + + Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + + + Extract 256 bits (composed of 8 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + + Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + + + Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + + Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[1:0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +2: dst[127:0] := a[383:256] +3: dst[127:0] := a[511:384] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + + + + Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + + + Extract 128 bits (composed of 2 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k". + [fpclass_note] + FOR j := 0 to 3 + i := j*64 + k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + + Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + [fpclass_note] + FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k". + [fpclass_note] + FOR j := 0 to 7 + i := j*64 + k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + + Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + [fpclass_note] + FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k". + [fpclass_note] + FOR j := 0 to 1 + i := j*64 + k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + + Test packed double-precision (64-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + [fpclass_note] + FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := CheckFPClass_FP64(a[i+63:i], imm8[7:0]) + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k". + [fpclass_note] + FOR j := 0 to 7 + i := j*32 + k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0]) +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + + Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + [fpclass_note] + FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0]) + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k". + [fpclass_note] + FOR j := 0 to 15 + i := j*32 + k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0]) +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + + Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + [fpclass_note] + FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0]) + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k". + [fpclass_note] + FOR j := 0 to 3 + i := j*32 + k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0]) +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + + + Test packed single-precision (32-bit) floating-point elements in "a" for special categories specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + [fpclass_note] + FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := CheckFPClass_FP32(a[i+31:i], imm8[7:0]) + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k". + [fpclass_note] + k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0]) +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + + Test the lower double-precision (64-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). + [fpclass_note] + IF k1[0] + k[0] := CheckFPClass_FP64(a[63:0], imm8[7:0]) +ELSE + k[0] := 0 +FI +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k. + [fpclass_note] + k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0]) +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512DQ + Miscellaneous + + + + + Test the lower single-precision (32-bit) floating-point element in "a" for special categories specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). + [fpclass_note] + IF k1[0] + k[0] := CheckFPClass_FP32(a[31:0], imm8[7:0]) +ELSE + k[0] := 0 +FI +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Copy "a" to "dst", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE (imm8[0]) OF +0: dst[255:0] := b[255:0] +1: dst[511:256] := b[255:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 8 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE imm8[0] OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Copy "a" to "dst", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE imm8[1:0] OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +2: dst[383:256] := b[127:0] +3: dst[511:384] := b[127:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + Copy "a" to "dst", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE imm8[0] OF +0: dst[255:0] := b[255:0] +1: dst[511:256] := b[255:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 8 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + + Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE imm8[0] OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + Copy "a" to "dst", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE imm8[1:0] OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +2: dst[383:256] := b[127:0] +3: dst[511:384] := b[127:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512DQ + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 2 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] OR b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] OR b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a". + +FOR j := 0 to 7 + i := j*32 + IF a[i+31] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512DQ + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a". + +FOR j := 0 to 15 + i := j*32 + IF a[i+31] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 32-bit integer in "a". + +FOR j := 0 to 3 + i := j*32 + IF a[i+31] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := 0xFFFFFFFF + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := 0xFFFFFFFF + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + Set each packed 32-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := 0xFFFFFFFF + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := 0xFFFFFFFFFFFFFFFF + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Miscellaneous + + + Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := 0xFFFFFFFFFFFFFFFF + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Miscellaneous + + + Set each packed 64-bit integer in "dst" to all ones or all zeros based on the value of the corresponding bit in "k". + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := 0xFFFFFFFFFFFFFFFF + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a". + +FOR j := 0 to 3 + i := j*64 + IF a[i+63] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512DQ + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a". + +FOR j := 0 to 7 + i := j*64 + IF a[i+63] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512DQ + Miscellaneous + + + Set each bit of mask register "k" based on the most significant bit of the corresponding packed 64-bit integer in "a". + +FOR j := 0 to 1 + i := j*64 + IF a[i+63] + k[j] := 1 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Arithmetic + + + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Arithmetic + + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Arithmetic + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst". + +FOR j := 0 to 3 + i := j*64 + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Arithmetic + + + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Arithmetic + + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512DQ + Arithmetic + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst". + +FOR j := 0 to 7 + i := j*64 + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Arithmetic + + + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Arithmetic + + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512DQ + Arithmetic + + + + Multiply the packed 64-bit integers in "a" and "b", producing intermediate 128-bit integers, and store the low 64 bits of the intermediate integers in "dst". + +FOR j := 0 to 1 + i := j*64 + tmp[127:0] := a[i+63:i] * b[i+63:i] + dst[i+63:i] := tmp[63:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := RANGE(a[i+63:i], b[i+63:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[63:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := RANGE(a[i+31:i], b[i+31:i], imm8[1:0], imm8[3:2]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[63:0], src2[63:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src1[63:0] : src2[63:0] + 1: tmp[63:0] := (src1[63:0] <= src2[63:0]) ? src2[63:0] : src1[63:0] + 2: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src1[63:0] : src2[63:0] + 3: tmp[63:0] := (ABS(src1[63:0]) <= ABS(src2[63:0])) ? src2[63:0] : src1[63:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[63:0] := (src1[63] << 63) OR (tmp[62:0]) + 1: dst[63:0] := tmp[63:0] + 2: dst[63:0] := (0 << 63) OR (tmp[62:0]) + 3: dst[63:0] := (1 << 63) OR (tmp[62:0]) + ESAC + + RETURN dst +} +dst[63:0] := RANGE(a[63:0], b[63:0], imm8[1:0], imm8[3:2]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[31:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[31:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[31:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[31:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +IF k[0] + dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Calculate the max, min, absolute max, or absolute min (depending on control in "imm8") for the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + imm8[1:0] specifies the operation control: 00 = min, 01 = max, 10 = absolute max, 11 = absolute min. + imm8[3:2] specifies the sign control: 00 = sign from a, 01 = sign from compare result, 10 = clear sign bit, 11 = set sign bit. [sae_note] + +DEFINE RANGE(src1[31:0], src2[31:0], opCtl[1:0], signSelCtl[1:0]) { + CASE opCtl[1:0] OF + 0: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src1[31:0] : src2[31:0] + 1: tmp[31:0] := (src1[31:0] <= src2[31:0]) ? src2[31:0] : src1[31:0] + 2: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src1[31:0] : src2[31:0] + 3: tmp[31:0] := (ABS(src1[31:0]) <= ABS(src2[31:0])) ? src2[31:0] : src1[31:0] + ESAC + + CASE signSelCtl[1:0] OF + 0: dst[31:0] := (src1[31] << 31) OR (tmp[30:0]) + 1: dst[31:0] := tmp[31:0] + 2: dst[31:0] := (0 << 31) OR (tmp[30:0]) + 3: dst[31:0] := (1 << 31) OR (tmp[30:0]) + ESAC + + RETURN dst +} +dst[31:0] := RANGE(a[31:0], b[31:0], imm8[1:0], imm8[3:2]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Extract the reduced argument of packed double-precision (64-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ReduceArgumentPD(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + RETURN tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Miscellaneous + + + + Extract the reduced argument of packed single-precision (32-bit) floating-point elements in "a" by the number of bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ReduceArgumentPS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + + Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of the lower double-precision (64-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPD(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + tmp[63:0] := src1[63:0] - tmp[63:0] + IF IsInf(tmp[63:0]) + tmp[63:0] := FP64(0.0) + FI + RETURN tmp[63:0] +} +dst[63:0] := ReduceArgumentPD(b[63:0], imm8[7:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + + Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + + Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Miscellaneous + + + + + + Extract the reduced argument of the lower single-precision (32-bit) floating-point element in "b" by the number of bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note] + +DEFINE ReduceArgumentPS(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + tmp[31:0] := src1[31:0] - tmp[31:0] + IF IsInf(tmp[31:0]) + tmp[31:0] := FP32(0.0) + FI + RETURN tmp[31:0] +} +dst[31:0] := ReduceArgumentPS(b[31:0], imm8[7:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512DQ + Logical + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512DQ + Logical + + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Add 8-bit masks in "a" and "b", and store the result in "k". + +k[7:0] := a[7:0] + b[7:0] +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Add 16-bit masks in "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] + b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise AND of 8-bit masks "a" and "b", and store the result in "k". + +k[7:0] := a[7:0] AND b[7:0] +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise NOT of 8-bit masks "a" and then AND with "b", and store the result in "k". + +k[7:0] := (NOT a[7:0]) AND b[7:0] +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + Compute the bitwise NOT of 8-bit mask "a", and store the result in "k". + +k[7:0] := NOT a[7:0] +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise OR of 8-bit masks "a" and "b", and store the result in "k". + +k[7:0] := a[7:0] OR b[7:0] +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise XNOR of 8-bit masks "a" and "b", and store the result in "k". + +k[7:0] := NOT (a[7:0] XOR b[7:0]) +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise XOR of 8-bit masks "a" and "b", and store the result in "k". + +k[7:0] := a[7:0] XOR b[7:0] +k[MAX:8] := 0 + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Shift the bits of 8-bit mask "a" left by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 7 + k[7:0] := a[7:0] << count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Shift the bits of 8-bit mask "a" right by "count" while shifting in zeros, and store the least significant 8 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 7 + k[7:0] := a[7:0] >> count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Load + + + Load 8-bit mask from memory into "k". + +k[7:0] := MEM[mem_addr+7:mem_addr] + + +

immintrin.h

+ + + Mask + AVX512DQ + Store + + + + Store 8-bit mask from "a" into memory. + +MEM[mem_addr+7:mem_addr] := a[7:0] + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + + Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones". + +tmp[7:0] := a[7:0] OR b[7:0] +IF tmp[7:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +IF tmp[7:0] == 0xFF + MEM[all_ones+7:all_ones] := 1 +ELSE + MEM[all_ones+7:all_ones] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[7:0] := a[7:0] OR b[7:0] +IF tmp[7:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise OR of 8-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst". + +tmp[7:0] := a[7:0] OR b[7:0] +IF tmp[7:0] == 0xFF + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + + Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not". + +tmp1[7:0] := a[7:0] AND b[7:0] +IF tmp1[7:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +tmp2[7:0] := (NOT a[7:0]) AND b[7:0] +IF tmp2[7:0] == 0x0 + MEM[and_not+7:and_not] := 1 +ELSE + MEM[and_not+7:and_not] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise AND of 8-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". + +tmp[7:0] := a[7:0] AND b[7:0] +IF tmp[7:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise NOT of 8-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[7:0] := (NOT a[7:0]) AND b[7:0] +IF tmp[7:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + + Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". Compute the bitwise NOT of "a" and then AND with "b", if the result is all zeros, store 1 in "and_not", otherwise store 0 in "and_not". + +tmp1[15:0] := a[15:0] AND b[15:0] +IF tmp1[15:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +tmp2[15:0] := (NOT a[15:0]) AND b[15:0] +IF tmp2[15:0] == 0x0 + MEM[and_not+7:and_not] := 1 +ELSE + MEM[and_not+7:and_not] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise AND of 16-bit masks "a" and "b", and if the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". + +tmp[15:0] := a[15:0] AND b[15:0] +IF tmp[15:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512DQ + Mask + + + + Compute the bitwise NOT of 16-bit mask "a" and then AND with "b", if the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[15:0] := (NOT a[15:0]) AND b[15:0] +IF tmp[15:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + AVX512DQ + Mask + + + Convert 8-bit mask "a" into an integer value, and store the result in "dst". + +dst := ZeroExtend32(a[7:0]) + + +

immintrin.h

+ + + AVX512DQ + Mask + + + Convert integer value "a" into an 8-bit mask, and store the result in "k". + +k := a[7:0] + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23. [sae_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23. [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(2.0, a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-23. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(2.0, a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(2.0, a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(2.0, a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(2.0, a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-23. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(2.0, a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +dst[63:0] := (1.0 / b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. + +dst[63:0] := (1.0 / b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[63:0] := (1.0 / b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[63:0] := (1.0 / b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[63:0] := (1.0 / b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[63:0] := (1.0 / b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst". The maximum relative error for this approximation is less than 2^-28, and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +dst[31:0] := (1.0 / b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. + +dst[31:0] := (1.0 / b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[31:0] := (1.0 / b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[31:0] := (1.0 / b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[31:0] := (1.0 / b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[31:0] := (1.0 / b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / a[i+63:i]) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / a[i+63:i]) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +dst[63:0] := (1.0 / SQRT(b[63:0])) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. + +dst[63:0] := (1.0 / SQRT(b[63:0])) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[63:0] := (1.0 / SQRT(b[63:0])) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[63:0] := (1.0 / SQRT(b[63:0])) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[63:0] := (1.0 / SQRT(b[63:0])) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[63:0] := (1.0 / SQRT(b[63:0])) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +dst[31:0] := (1.0 / SQRT(b[31:0])) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. + +dst[31:0] := (1.0 / SQRT(b[31:0])) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[31:0] := (1.0 / SQRT(b[31:0])) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[31:0] := (1.0 / SQRT(b[31:0])) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +IF k[0] + dst[31:0] := (1.0 / SQRT(b[31:0])) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-28. + +IF k[0] + dst[31:0] := (1.0 / SQRT(b[31:0])) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst". The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512ER + Elementary Math Functions + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-28. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + AVX512VL + Arithmetic + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst". + +temp[511:256] := a[255:0] +temp[255:0] := b[255:0] +temp[511:0] := temp[511:0] >> (32*imm8[2:0]) +dst[255:0] := temp[255:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + + Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +temp[511:256] := a[255:0] +temp[255:0] := b[255:0] +temp[511:0] := temp[511:0] >> (32*imm8[2:0]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := temp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 32 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +temp[511:256] := a[255:0] +temp[255:0] := b[255:0] +temp[511:0] := temp[511:0] >> (32*imm8[2:0]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := temp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst". + +temp[255:128] := a[127:0] +temp[127:0] := b[127:0] +temp[255:0] := temp[255:0] >> (32*imm8[1:0]) +dst[127:0] := temp[127:0] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + + Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +temp[255:128] := a[127:0] +temp[127:0] := b[127:0] +temp[255:0] := temp[255:0] >> (32*imm8[1:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := temp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 16 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +temp[255:128] := a[127:0] +temp[127:0] := b[127:0] +temp[255:0] := temp[255:0] >> (32*imm8[1:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := temp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst". + +temp[511:256] := a[255:0] +temp[255:0] := b[255:0] +temp[511:0] := temp[511:0] >> (64*imm8[1:0]) +dst[255:0] := temp[255:0] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + + Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +temp[511:256] := a[255:0] +temp[255:0] := b[255:0] +temp[511:0] := temp[511:0] >> (64*imm8[1:0]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := temp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + Concatenate "a" and "b" into a 64-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 32 bytes (4 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +temp[511:256] := a[255:0] +temp[255:0] := b[255:0] +temp[511:0] := temp[511:0] >> (64*imm8[1:0]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := temp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst". + +temp[255:128] := a[127:0] +temp[127:0] := b[127:0] +temp[255:0] := temp[255:0] >> (64*imm8[0]) +dst[127:0] := temp[127:0] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + + Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +temp[255:128] := a[127:0] +temp[127:0] := b[127:0] +temp[255:0] := temp[255:0] >> (64*imm8[0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := temp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + AVX512VL + Miscellaneous + + + + + + Concatenate "a" and "b" into a 32-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 16 bytes (2 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +temp[255:128] := a[127:0] +temp[127:0] := b[127:0] +temp[255:0] := temp[255:0] >> (64*imm8[0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := temp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*32 + n := (j % 4)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*32 + n := (j % 4)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 3 + i := j*64 + k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*32 + k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 64 +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[255:m] := src[255:m] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 64 +m := base_addr +FOR j := 0 to 3 + i := j*64 + IF k[j] + MEM[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 64 +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[255:m] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 64 +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[127:m] := src[127:m] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 64 +m := base_addr +FOR j := 0 to 1 + i := j*64 + IF k[j] + MEM[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 64 +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[127:m] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 32 +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[255:m] := src[255:m] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 32 +m := base_addr +FOR j := 0 to 7 + i := j*32 + IF k[j] + MEM[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 32 +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[255:m] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 32 +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[127:m] := src[127:m] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 32 +m := base_addr +FOR j := 0 to 3 + i := j*32 + IF k[j] + MEM[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 32 +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[127:m] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF k[j] + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) + ELSE + dst[m+63:m] := src[m+63:m] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF k[j] + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) + ELSE + dst[m+63:m] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF k[j] + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) + ELSE + dst[m+63:m] := src[m+63:m] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF k[j] + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) + ELSE + dst[m+63:m] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +FOR j := 0 to 7 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +FOR j := 0 to 7 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +FOR j := 0 to 3 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +FOR j := 0 to 3 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +FOR j := 0 to 3 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +FOR j := 0 to 3 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_Int32_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN: j := 0 + SNAN_TOKEN: j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE (imm8[0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8". + +dst[255:0] := a[255:0] +CASE (imm8[0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[255:0] := a[255:0] +CASE (imm8[0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +ESAC +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[63:0] := a[63:0] +tmp[127:64] := a[63:0] +tmp[191:128] := a[191:128] +tmp[255:192] := a[191:128] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[63:0] := a[63:0] +tmp[127:64] := a[63:0] +tmp[191:128] := a[191:128] +tmp[255:192] := a[191:128] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[63:0] := a[63:0] +tmp[127:64] := a[63:0] +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[63:0] := a[63:0] +tmp[127:64] := a[63:0] +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + + Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 32-bit integers from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + + Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 32-bit integers from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + + Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 64-bit integers from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + + Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 64-bit integers from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Move + + + + Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 32-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 32-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 64-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Store packed 64-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[31:0] := a[63:32] +tmp[63:32] := a[63:32] +tmp[95:64] := a[127:96] +tmp[127:96] := a[127:96] +tmp[159:128] := a[191:160] +tmp[191:160] := a[191:160] +tmp[223:192] := a[255:224] +tmp[255:224] := a[255:224] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[31:0] := a[63:32] +tmp[63:32] := a[63:32] +tmp[95:64] := a[127:96] +tmp[127:96] := a[127:96] +tmp[159:128] := a[191:160] +tmp[191:160] := a[191:160] +tmp[223:192] := a[255:224] +tmp[255:224] := a[255:224] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[31:0] := a[63:32] +tmp[63:32] := a[63:32] +tmp[95:64] := a[127:96] +tmp[127:96] := a[127:96] +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[31:0] := a[63:32] +tmp[63:32] := a[63:32] +tmp[95:64] := a[127:96] +tmp[127:96] := a[127:96] +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[31:0] := a[31:0] +tmp[63:32] := a[31:0] +tmp[95:64] := a[95:64] +tmp[127:96] := a[95:64] +tmp[159:128] := a[159:128] +tmp[191:160] := a[159:128] +tmp[223:192] := a[223:192] +tmp[255:224] := a[223:192] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[31:0] := a[31:0] +tmp[63:32] := a[31:0] +tmp[95:64] := a[95:64] +tmp[127:96] := a[95:64] +tmp[159:128] := a[159:128] +tmp[191:160] := a[159:128] +tmp[223:192] := a[223:192] +tmp[255:224] := a[223:192] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[31:0] := a[31:0] +tmp[63:32] := a[31:0] +tmp[95:64] := a[95:64] +tmp[127:96] := a[95:64] +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Move + + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[31:0] := a[31:0] +tmp[63:32] := a[31:0] +tmp[95:64] := a[95:64] +tmp[127:96] := a[95:64] +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). RM. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ABS(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ABS(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] :=0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] AND b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] AND b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] AND b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] AND b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] AND b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] AND b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] AND b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] AND b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + + Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + + Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + + Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + + Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Set + + + + Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*32 + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*32 + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 3 + i := j*64 + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 1 + i := j*64 + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + + Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 32 +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[255:m] := src[255:m] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 32 +m := base_addr +FOR j := 0 to 7 + i := j*32 + IF k[j] + MEM[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 32 +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[255:m] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 32 +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[127:m] := src[127:m] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 32 +m := base_addr +FOR j := 0 to 3 + i := j*32 + IF k[j] + MEM[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 32 +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[127:m] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 64 +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[255:m] := src[255:m] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 64 +m := base_addr +FOR j := 0 to 3 + i := j*64 + IF k[j] + MEM[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 64 +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[255:m] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 64 +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[127:m] := src[127:m] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 64 +m := base_addr +FOR j := 0 to 1 + i := j*64 + IF k[j] + MEM[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 64 +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[127:m] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := idx[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off] +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + IF k[j] + dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := idx[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + IF k[j] + dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + IF k[j] + dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 32-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off] +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := idx[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off] +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set) + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + IF k[j] + dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := idx[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + IF k[j] + dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + IF k[j] + dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off] +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := idx[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := (idx[i+3]) ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + off := idx[i+2:i]*32 + dst[i+31:i] := idx[i+3] ? b[off+31:off] : a[off+31:off] +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + IF k[j] + dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := idx[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + IF k[j] + dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + IF k[j] + dst[i+31:i] := (idx[i+2]) ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + off := idx[i+1:i]*32 + dst[i+31:i] := idx[i+2] ? b[off+31:off] : a[off+31:off] +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := idx[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := (idx[i+2]) ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + off := idx[i+1:i]*64 + dst[i+63:i] := idx[i+2] ? b[off+63:off] : a[off+63:off] +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + IF k[j] + dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := idx[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + IF k[j] + dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + IF k[j] + dst[i+63:i] := (idx[i+1]) ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 64-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + off := idx[i]*64 + dst[i+63:i] := idx[i+1] ? b[off+63:off] : a[off+63:off] +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], b[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], b[33:32]) +tmp_dst[95:64] := SELECT4(a[127:0], b[65:64]) +tmp_dst[127:96] := SELECT4(a[127:0], b[97:96]) +tmp_dst[159:128] := SELECT4(a[255:128], b[129:128]) +tmp_dst[191:160] := SELECT4(a[255:128], b[161:160]) +tmp_dst[223:192] := SELECT4(a[255:128], b[193:192]) +tmp_dst[255:224] := SELECT4(a[255:128], b[225:224]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], b[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], b[33:32]) +tmp_dst[95:64] := SELECT4(a[127:0], b[65:64]) +tmp_dst[127:96] := SELECT4(a[127:0], b[97:96]) +tmp_dst[159:128] := SELECT4(a[255:128], b[129:128]) +tmp_dst[191:160] := SELECT4(a[255:128], b[161:160]) +tmp_dst[223:192] := SELECT4(a[255:128], b[193:192]) +tmp_dst[255:224] := SELECT4(a[255:128], b[225:224]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], b[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], b[33:32]) +tmp_dst[95:64] := SELECT4(a[127:0], b[65:64]) +tmp_dst[127:96] := SELECT4(a[127:0], b[97:96]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], b[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], b[33:32]) +tmp_dst[95:64] := SELECT4(a[127:0], b[65:64]) +tmp_dst[127:96] := SELECT4(a[127:0], b[97:96]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + id := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + id := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + id := idx[i+1:i]*64 + dst[i+63:i] := a[id+63:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx". + +FOR j := 0 to 7 + i := j*32 + id := idx[i+2:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" across lanes lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + id := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + id := idx[i+1:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Shuffle 64-bit integers in "a" across lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + id := idx[i+1:i]*64 + dst[i+63:i] := a[id+63:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 8*j + dst[k+7:k] := Truncate8(a[i+31:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 8*j + dst[k+7:k] := Truncate8(a[i+31:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 16*j + dst[k+15:k] := Truncate16(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 16*j + dst[k+15:k] := Truncate16(a[i+31:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 8*j + dst[k+7:k] := Truncate8(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 8*j + dst[k+7:k] := Truncate8(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 32*j + dst[k+31:k] := Truncate32(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Truncate32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Truncate32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 32*j + dst[k+31:k] := Truncate32(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Truncate32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Truncate32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 16*j + dst[k+15:k] := Truncate16(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 16*j + dst[k+15:k] := Truncate16(a[i+63:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 8*j + dst[k+7:k] := Saturate8(a[i+31:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 8*j + dst[k+7:k] := Saturate8(a[i+31:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 16*j + dst[k+15:k] := Saturate16(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 16*j + dst[k+15:k] := Saturate16(a[i+31:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 8*j + dst[k+7:k] := Saturate8(a[i+63:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 8*j + dst[k+7:k] := Saturate8(a[i+63:i]) +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 32*j + dst[k+31:k] := Saturate32(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Saturate32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Saturate32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 32*j + dst[k+31:k] := Saturate32(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Saturate32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Saturate32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 16*j + dst[k+15:k] := Saturate16(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 16*j + dst[k+15:k] := Saturate16(a[i+63:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + l := j*16 + IF k[j] + dst[i+31:i] := SignExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + l := j*16 + IF k[j] + dst[i+31:i] := SignExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Sign extend packed 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 8*j + dst[k+7:k] := SaturateU8(a[i+31:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 8*j + dst[k+7:k] := SaturateU8(a[i+31:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 16*j + dst[k+15:k] := SaturateU16(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 16*j + dst[k+15:k] := SaturateU16(a[i+31:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 8*j + dst[k+7:k] := SaturateU8(a[i+63:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 8*j + dst[k+7:k] := SaturateU8(a[i+63:i]) +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 32*j + dst[k+31:k] := SaturateU32(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := SaturateU32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := SaturateU32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 32*j + dst[k+31:k] := SaturateU32(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := SaturateU32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := SaturateU32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := 64*j + k := 16*j + dst[k+15:k] := SaturateU16(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 16*j + dst[k+15:k] := SaturateU16(a[i+63:i]) +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 8-bit integers in th elow 4 bytes of "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 8-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 8-bit integers in the low 2 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 16-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + + Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Convert + + + + Zero extend packed unsigned 16-bit integers in the low 4 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + + + + Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + FOR h := 0 to 31 + index[2:0] := (src[i+h] << 2) OR (a[i+h] << 1) OR b[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + FOR h := 0 to 31 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst". + +FOR j := 0 to 7 + i := j*32 + FOR h := 0 to 31 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + FOR h := 0 to 31 + index[2:0] := (src[i+h] << 2) OR (a[i+h] << 1) OR b[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + FOR h := 0 to 31 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst". + +FOR j := 0 to 3 + i := j*32 + FOR h := 0 to 31 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + FOR h := 0 to 63 + index[2:0] := (src[i+h] << 2) OR (a[i+h] << 1) OR b[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + FOR h := 0 to 63 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst". + +FOR j := 0 to 3 + i := j*64 + FOR h := 0 to 63 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + FOR h := 0 to 63 + index[2:0] := (src[i+h] << 2) OR (a[i+h] << 1) OR b[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + FOR h := 0 to 63 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst". + +FOR j := 0 to 1 + i := j*64 + FOR h := 0 to 63 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 7 + i := j*32 + k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 3 + i := j*32 + k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 3 + i := j*64 + k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 1 + i := j*64 + k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 7 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 7 + i := j*32 + k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 3 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 3 + i := j*32 + k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 3 + i := j*64 + IF k1[j] + k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 3 + i := j*64 + k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:4] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + + Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 1 + i := j*64 + IF k1[j] + k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512VL + AVX512F + Compare + + + + Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 1 + i := j*64 + k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:2] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := (1.0 / a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (1.0 / a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 3 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Store + + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 1 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst". + +dst.m128[0] := a.m128[imm8[0]] +dst.m128[1] := b.m128[imm8[1]] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst". + +dst.m128[0] := a.m128[imm8[0]] +dst.m128[1] := b.m128[imm8[1]] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst". + +dst.m128[0] := a.m128[imm8[0]] +dst.m128[1] := b.m128[imm8[1]] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst.m128[0] := a.m128[imm8[0]] +tmp_dst.m128[1] := b.m128[imm8[1]] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512VL + AVX512F + Miscellaneous + + + + + Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst". + +dst.m128[0] := a.m128[imm8[0]] +dst.m128[1] := b.m128[imm8[1]] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192] +tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192] +tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192] +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Elementary Math Functions + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Arithmetic + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512VL + AVX512F + Miscellaneous + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 256-bits (composed of 4 packed 64-bit integers) from "a" into memory. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 256-bits (composed of 8 packed 32-bit integers) from "a" into memory. + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+255:mem_addr] := a[255:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 128-bits (composed of 2 packed 64-bit integers) from "a" into memory. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Store + + + + Store 128-bits (composed of 4 packed 32-bit integers) from "a" into memory. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 256-bits (composed of 4 packed 64-bit integers) from memory into "dst". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 256-bits (composed of 8 packed 32-bit integers) from memory into "dst". + "mem_addr" must be aligned on a 32-byte boundary or a general-protection exception may be generated. + +dst[255:0] := MEM[mem_addr+255:mem_addr] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 128-bits (composed of 2 packed 64-bit integers) from memory into "dst". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[127:0] := MEM[mem_addr+127:mem_addr] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Load + + + Load 128-bits (composed of 4 packed 32-bit integers) from memory into "dst". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[127:0] := MEM[mem_addr+127:mem_addr] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := a[i+63:i] OR b[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := a[i+31:i] OR b[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] OR b[i+63:i] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + AVX512F + Logical + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] OR b[i+31:i] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + VAES + Cryptography + + + + Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"." + FOR j := 0 to 3 + i := j*128 + a[i+127:i] := ShiftRows(a[i+127:i]) + a[i+127:i] := SubBytes(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + VAES + Cryptography + + + + Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"." + FOR j := 0 to 3 + i := j*128 + a[i+127:i] := ShiftRows(a[i+127:i]) + a[i+127:i] := SubBytes(a[i+127:i]) + a[i+127:i] := MixColumns(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + VAES + Cryptography + + + + Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst". + FOR j := 0 to 3 + i := j*128 + a[i+127:i] := InvShiftRows(a[i+127:i]) + a[i+127:i] := InvSubBytes(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + VAES + Cryptography + + + + Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst". + FOR j := 0 to 3 + i := j*128 + a[i+127:i] := InvShiftRows(a[i+127:i]) + a[i+127:i] := InvSubBytes(a[i+127:i]) + a[i+127:i] := InvMixColumns(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] AND b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k". + +k[15:0] := (NOT a[15:0]) AND b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + Compute the bitwise NOT of 16-bit mask "a", and store the result in "k". + +k[15:0] := NOT a[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] OR b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := NOT (a[15:0] XOR b[15:0]) +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] XOR b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Shift the bits of 16-bit mask "a" left by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 15 + k[15:0] := a[15:0] << count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Shift the bits of 16-bit mask "a" right by "count" while shifting in zeros, and store the least significant 16 bits of the result in "k". + +k[MAX:0] := 0 +IF count[7:0] <= 15 + k[15:0] := a[15:0] >> count[7:0] +FI + + +

immintrin.h

+ + + Mask + AVX512F + Load + + + Load 16-bit mask from memory into "k". + +k[15:0] := MEM[mem_addr+15:mem_addr] + + +

immintrin.h

+ + + Mask + AVX512F + Store + + + + Store 16-bit mask from "a" into memory. + +MEM[mem_addr+15:mem_addr] := a[15:0] + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + + Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all zeros, store 1 in "dst", otherwise store 0 in "dst". If the result is all ones, store 1 in "all_ones", otherwise store 0 in "all_ones". + +tmp[15:0] := a[15:0] OR b[15:0] +IF tmp[15:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI +IF tmp[15:0] == 0xFFFF + MEM[all_ones+7:all_ones] := 1 +ELSE + MEM[all_ones+7:all_ones] := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all zeroes, store 1 in "dst", otherwise store 0 in "dst". + +tmp[15:0] := a[15:0] OR b[15:0] +IF tmp[15:0] == 0x0 + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise OR of 16-bit masks "a" and "b". If the result is all ones, store 1 in "dst", otherwise store 0 in "dst". + +tmp[15:0] := a[15:0] OR b[15:0] +IF tmp[15:0] == 0xFFFF + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + AVX512F + Mask + + + Convert 16-bit mask "a" into an integer value, and store the result in "dst". + +dst := ZeroExtend32(a[15:0]) + + +

immintrin.h

+ + + AVX512F + Mask + + + Convert integer value "a" into an 16-bit mask, and store the result in "k". + +k := ZeroExtend16(a[15:0]) + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k". + +k[15:0] := (NOT a[15:0]) AND b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] AND b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + Copy 16-bit mask "a" to "k". + +k[15:0] := a[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + Compute the bitwise NOT of 16-bit mask "a", and store the result in "k". + +k[15:0] := NOT a[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] OR b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Unpack and interleave 8 bits from masks "a" and "b", and store the 16-bit result in "k". + +k[7:0] := b[7:0] +k[15:8] := a[7:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := NOT (a[15:0] XOR b[15:0]) +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] XOR b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := a[63:0] + b[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] + b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] + b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] + b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] + b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := a[31:0] + b[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] + b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] + b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] + b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] + b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Miscellaneous + + + + + + Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and stores the low 64 bytes (16 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +temp[1023:512] := a[511:0] +temp[511:0] := b[511:0] +temp[1023:0] := temp[1023:0] >> (32*imm8[3:0]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := temp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Miscellaneous + + + + + Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 64 bytes (8 elements) in "dst". + +temp[1023:512] := a[511:0] +temp[511:0] := b[511:0] +temp[1023:0] := temp[1023:0] >> (64*imm8[2:0]) +dst[511:0] := temp[511:0] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Miscellaneous + + + + + + + Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and store the low 64 bytes (8 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +temp[1023:512] := a[511:0] +temp[511:0] := b[511:0] +temp[1023:0] := temp[1023:0] >> (64*imm8[2:0]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := temp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Miscellaneous + + + + + + Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 64-bit elements, and stores the low 64 bytes (8 elements) in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +temp[1023:512] := a[511:0] +temp[511:0] := b[511:0] +temp[1023:0] := temp[1023:0] >> (64*imm8[2:0]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := temp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + n := (j % 4)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Broadcast the 4 packed single-precision (32-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + n := (j % 4)*64 + dst[i+63:i] := a[n+63:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 4)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Broadcast the 4 packed double-precision (64-bit) floating-point elements from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 4)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + n := (j % 4)*32 + dst[i+31:i] := a[n+31:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Broadcast the 4 packed 32-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + n := (j % 4)*32 + IF k[j] + dst[i+31:i] := a[n+31:n] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + n := (j % 4)*64 + dst[i+63:i] := a[n+63:n] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 4)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Broadcast the 4 packed 64-bit integers from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + n := (j % 4)*64 + IF k[j] + dst[i+63:i] := a[n+63:n] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Broadcast the low double-precision (64-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Broadcast the low single-precision (32-bit) floating-point element from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0 +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0 +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +IF k1[0] + k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0 +ELSE + k[0] := 0 +FI +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +IF k1[0] + k[0] := ( a[63:0] OP b[63:0] ) ? 1 : 0 +ELSE + k[0] := 0 +FI +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0 +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0 +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +IF k1[0] + k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0 +ELSE + k[0] := 0 +FI +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F + Compare + + + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and store the result in mask vector "k" using zeromask "k1" (the element is zeroed out when mask bit 0 is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +IF k1[0] + k[0] := ( a[31:0] OP b[31:0] ) ? 1 : 0 +ELSE + k[0] := 0 +FI +k[MAX:1] := 0 + + +

immintrin.h

+ + + Floating Point + Flag + AVX512F + Compare + + + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +RETURN ( a[63:0] OP b[63:0] ) ? 1 : 0 + + +

immintrin.h

+ + + Floating Point + Flag + AVX512F + Compare + + + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" based on the comparison operand specified by "imm8", and return the boolean result (0 or 1). [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +RETURN ( a[31:0] OP b[31:0] ) ? 1 : 0 + + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 64 +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[511:m] := src[511:m] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + Swizzle + + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 64 +m := base_addr +FOR j := 0 to 7 + i := j*64 + IF k[j] + MEM[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Contiguously store the active double-precision (64-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 64 +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[511:m] := 0 +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 32 +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[511:m] := src[511:m] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + Swizzle + + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 32 +m := base_addr +FOR j := 0 to 15 + i := j*32 + IF k[j] + MEM[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Contiguously store the active single-precision (32-bit) floating-point elements in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 32 +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[511:m] := 0 +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + m := j*64 + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) + ELSE + dst[m+63:m] := src[m+63:m] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) + ELSE + dst[m+63:m] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_FP32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". [sae_note] + +FOR j := 0 to 15 + i := j*32 + m := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + m := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + m := j*16 + IF k[j] + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := Convert_FP32_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". [sae_note] + +FOR j := 0 to 15 + i := 16*j + l := 32*j + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := 16*j + l := 32*j + IF k[j] + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + [round_note] + +dst[31:0] := Convert_FP64_To_Int32(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + [round_note] + +dst[63:0] := Convert_FP64_To_Int64(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + [round_note] + +dst[31:0] := Convert_FP64_To_Int32(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + [round_note] + +dst[63:0] := Convert_FP64_To_Int64(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP64_To_Int32(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + +dst[63:0] := Convert_FP64_To_Int64(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := Convert_FP64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + + Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := Convert_FP64_To_FP32(b[63:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := Convert_FP64_To_FP32(b[63:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := Convert_FP64_To_FP32(b[63:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := Convert_FP64_To_FP32(b[63:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst". + [round_note] + +dst[31:0] := Convert_FP64_To_UInt32(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst". + [round_note] + +dst[63:0] := Convert_FP64_To_UInt64(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP64_To_UInt32(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst". + +dst[63:0] := Convert_FP64_To_UInt64(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := Convert_Int64_To_FP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := Convert_Int64_To_FP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the signed 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_Int32_To_FP64(b[31:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_Int64_To_FP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := Convert_Int64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := Convert_Int64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [sae_note] + +dst[63:0] := Convert_FP32_To_FP64(b[31:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + + Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [sae_note] + +IF k[0] + dst[63:0] := Convert_FP32_To_FP64(b[31:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := Convert_FP32_To_FP64(b[31:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + + Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [sae_note] + +IF k[0] + dst[63:0] := Convert_FP32_To_FP64(b[31:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + + Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := Convert_FP32_To_FP64(b[31:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + [round_note] + +dst[31:0] := Convert_FP32_To_Int32(a[31:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + [round_note] + +dst[63:0] := Convert_FP32_To_Int64(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + [round_note] + +dst[31:0] := Convert_FP32_To_Int32(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + [round_note] + +dst[63:0] := Convert_FP32_To_Int64(a[31:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_Int32(a[31:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + +dst[63:0] := Convert_FP32_To_Int64(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst". + [round_note] + +dst[31:0] := Convert_FP32_To_UInt32(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst". + [round_note] + +dst[63:0] := Convert_FP32_To_UInt64(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_UInt32(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer, and store the result in "dst". + +dst[63:0] := Convert_FP32_To_UInt64(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[k+63:k]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 32*j + l := 64*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[l+63:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". [sae_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP32_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed double-precision (32-bit) floating-point elements in "a" to packed unsigned 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_FP64_To_UInt32_Truncate(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + +dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[31:0] := Convert_FP64_To_UInt32_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[63:0] := Convert_FP64_To_UInt64_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP64_To_UInt32_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst". + +dst[63:0] := Convert_FP64_To_UInt64_Truncate(a[63:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + +dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[31:0] := Convert_FP32_To_UInt32_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst". + [sae_note] + +dst[63:0] := Convert_FP32_To_UInt64_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_UInt32_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to an unsigned 64-bit integer with truncation, and store the result in "dst". + +dst[63:0] := Convert_FP32_To_UInt64_Truncate(a[31:0]) + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + l := j*32 + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[i+63:i] := Convert_Int64_To_FP64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + + Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert the unsigned 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := Convert_Int64_To_FP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the unsigned 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_Int32_To_FP64(b[31:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the unsigned 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_Int64_To_FP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert the unsigned 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + + Convert the unsigned 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := Convert_Int64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the unsigned 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F + Convert + + + + Convert the unsigned 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + dst[i+63:i] := a[i+63:i] / b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", =and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := 64*j + dst[i+63:i] := a[i+63:i] / b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := 64*j + IF k[j] + dst[i+63:i] := a[i+63:i] / b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := a[i+31:i] / b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := a[i+31:i] / b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := a[i+31:i] / b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := a[63:0] / b[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] / b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] / b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] / b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] / b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := a[31:0] / b[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] / b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] / b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] / b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] / b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + Swizzle + + + + + Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Load contiguous active double-precision (64-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + Swizzle + + + + Load contiguous active double-precision (64-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + Swizzle + + + + + Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Load contiguous active single-precision (32-bit) floating-point elements from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + Swizzle + + + + Load contiguous active single-precision (32-bit) floating-point elements from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[1:0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +2: dst[127:0] := a[383:256] +3: dst[127:0] := a[511:384] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[255:0] := a[255:0] +1: dst[255:0] := a[511:256] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Extract 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[1:0] OF +0: dst[127:0] := a[127:0] +1: dst[127:0] := a[255:128] +2: dst[127:0] := a[383:256] +3: dst[127:0] := a[511:384] +ESAC +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Extract 128 bits (composed of 4 packed 32-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[1:0] OF +0: tmp[127:0] := a[127:0] +1: tmp[127:0] := a[255:128] +2: tmp[127:0] := a[383:256] +3: tmp[127:0] := a[511:384] +ESAC +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the result in "dst". + +CASE imm8[0] OF +0: dst[255:0] := a[255:0] +1: dst[255:0] := a[511:256] +ESAC +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Extract 256 bits (composed of 4 packed 64-bit integers) from "a", selected with "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +CASE imm8[0] OF +0: tmp[255:0] := a[255:0] +1: tmp[255:0] := a[511:256] +ESAC +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up packed double-precision (64-bit) floating-point elements in "a" and "b" using packed 64-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FIXUPIMMPD(a[i+63:i], b[i+63:i], c[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up packed single-precision (32-bit) floating-point elements in "a" and "b" using packed 32-bit integers in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FIXUPIMMPD(a[i+31:i], b[i+31:i], c[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +IF k[0] + dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0]) +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +IF k[0] + dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0]) +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +IF k[0] + dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up the lower double-precision (64-bit) floating-point elements in "a" and "b" using the lower 64-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[63:0], src2[63:0], src3[63:0], imm8[7:0]) { + tsrc[63:0] := ((src2[62:52] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[63:0] + CASE(tsrc[63:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[63:0] := src1[63:0] + 1 : dest[63:0] := tsrc[63:0] + 2 : dest[63:0] := QNaN(tsrc[63:0]) + 3 : dest[63:0] := QNAN_Indefinite + 4 : dest[63:0] := -INF + 5 : dest[63:0] := +INF + 6 : dest[63:0] := tsrc.sign? -INF : +INF + 7 : dest[63:0] := -0 + 8 : dest[63:0] := +0 + 9 : dest[63:0] := -1 + 10: dest[63:0] := +1 + 11: dest[63:0] := 1/2 + 12: dest[63:0] := 90.0 + 13: dest[63:0] := PI/2 + 14: dest[63:0] := MAX_FLOAT + 15: dest[63:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[63:0] +} +IF k[0] + dst[63:0] := FIXUPIMMPD(a[63:0], b[63:0], c[63:0], imm8[7:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +IF k[0] + dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0]) +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +IF k[0] + dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0]) +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". "imm8" is used to set the required flags reporting. + [sae_note] + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +IF k[0] + dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Fix up the lower single-precision (32-bit) floating-point elements in "a" and "b" using the lower 32-bit integer in "c", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". "imm8" is used to set the required flags reporting. + enum TOKEN_TYPE { + QNAN_TOKEN := 0, \ + SNAN_TOKEN := 1, \ + ZERO_VALUE_TOKEN := 2, \ + ONE_VALUE_TOKEN := 3, \ + NEG_INF_TOKEN := 4, \ + POS_INF_TOKEN := 5, \ + NEG_VALUE_TOKEN := 6, \ + POS_VALUE_TOKEN := 7 +} +DEFINE FIXUPIMMPD(src1[31:0], src2[31:0], src3[31:0], imm8[7:0]) { + tsrc[31:0] := ((src2[30:23] == 0) AND (MXCSR.DAZ == 1)) ? 0.0 : src2[31:0] + CASE(tsrc[31:0]) OF + QNAN_TOKEN:j := 0 + SNAN_TOKEN:j := 1 + ZERO_VALUE_TOKEN: j := 2 + ONE_VALUE_TOKEN: j := 3 + NEG_INF_TOKEN: j := 4 + POS_INF_TOKEN: j := 5 + NEG_VALUE_TOKEN: j := 6 + POS_VALUE_TOKEN: j := 7 + ESAC + + token_response[3:0] := src3[3+4*j:4*j] + + CASE(token_response[3:0]) OF + 0 : dest[31:0] := src1[31:0] + 1 : dest[31:0] := tsrc[31:0] + 2 : dest[31:0] := QNaN(tsrc[31:0]) + 3 : dest[31:0] := QNAN_Indefinite + 4 : dest[31:0] := -INF + 5 : dest[31:0] := +INF + 6 : dest[31:0] := tsrc.sign? -INF : +INF + 7 : dest[31:0] := -0 + 8 : dest[31:0] := +0 + 9 : dest[31:0] := -1 + 10: dest[31:0] := +1 + 11: dest[31:0] := 1/2 + 12: dest[31:0] := 90.0 + 13: dest[31:0] := PI/2 + 14: dest[31:0] := MAX_FLOAT + 15: dest[31:0] := -MAX_FLOAT + ESAC + + CASE(tsrc[31:0]) OF + ZERO_VALUE_TOKEN: + IF (imm8[0]) #ZE; FI + ZERO_VALUE_TOKEN: + IF (imm8[1]) #IE; FI + ONE_VALUE_TOKEN: + IF (imm8[2]) #ZE; FI + ONE_VALUE_TOKEN: + IF (imm8[3]) #IE; FI + SNAN_TOKEN: + IF (imm8[4]) #IE; FI + NEG_INF_TOKEN: + IF (imm8[5]) #IE; FI + NEG_VALUE_TOKEN: + IF (imm8[6]) #IE; FI + POS_INF_TOKEN: + IF (imm8[7]) #IE; FI + ESAC + RETURN dest[31:0] +} +IF k[0] + dst[31:0] := FIXUPIMMPD(a[31:0], b[31:0], c[31:0], imm8[7:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "a" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "c" to the upper element of "dst". + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := c[63:0] +FI +dst[127:64] := c[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := a[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", subtract the lower element in "c" from the negated intermediate result, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "c" to the upper elements of "dst". + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := c[31:0] +FI +dst[127:32] := c[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using writemask "k" (the element is copied from "c" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := a[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + + + Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + [sae_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + [sae_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + [sae_note] + dst[63:0] := ConvertExpFP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + dst[63:0] := ConvertExpFP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + [sae_note] + IF k[0] + dst[63:0] := ConvertExpFP64(b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + IF k[0] + dst[63:0] := ConvertExpFP64(b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + [sae_note] + IF k[0] + dst[63:0] := ConvertExpFP64(b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Convert the exponent of the lower double-precision (64-bit) floating-point element in "b" to a double-precision (64-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + IF k[0] + dst[63:0] := ConvertExpFP64(b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + [sae_note] + dst[31:0] := ConvertExpFP32(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + dst[31:0] := ConvertExpFP32(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + [sae_note] + IF k[0] + dst[31:0] := ConvertExpFP32(b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + IF k[0] + dst[31:0] := ConvertExpFP32(b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + [sae_note] + IF k[0] + dst[31:0] := ConvertExpFP32(b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Convert the exponent of the lower single-precision (32-bit) floating-point element in "b" to a single-precision (32-bit) floating-point number representing the integer exponent, store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "floor(log2(x))" for the lower element. + IF k[0] + dst[31:0] := ConvertExpFP32(b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + + Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + IF k[0] + dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + IF k[0] + dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + IF k[0] + dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + IF k[0] + dst[63:0] := GetNormalizedMantissa(b[63:0], sc, interv) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + + Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + IF k[0] + dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + IF k[0] + dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + IF k[0] + dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Normalize the mantissas of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + IF k[0] + dst[31:0] := GetNormalizedMantissa(b[31:0], sc, interv) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Copy "a" to "dst", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +2: dst[383:256] := b[127:0] +3: dst[511:384] := b[127:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Copy "a" to "dst", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE (imm8[0]) OF +0: dst[255:0] := b[255:0] +1: dst[511:256] := b[255:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 4 packed double-precision (64-bit) floating-point elements) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Copy "a" to "dst", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: dst[127:0] := b[127:0] +1: dst[255:128] := b[127:0] +2: dst[383:256] := b[127:0] +3: dst[511:384] := b[127:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Copy "a" to "tmp", then insert 128 bits (composed of 4 packed 32-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[1:0]) OF +0: tmp[127:0] := b[127:0] +1: tmp[255:128] := b[127:0] +2: tmp[383:256] := b[127:0] +3: tmp[511:384] := b[127:0] +ESAC +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Copy "a" to "dst", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "dst" at the location specified by "imm8". + +dst[511:0] := a[511:0] +CASE (imm8[0]) OF +0: dst[255:0] := b[255:0] +1: dst[511:256] := b[255:0] +ESAC +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Copy "a" to "tmp", then insert 256 bits (composed of 4 packed 64-bit integers) from "b" into "tmp" at the location specified by "imm8". Store "tmp" to "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[511:0] := a[511:0] +CASE (imm8[0]) OF +0: tmp[255:0] := b[255:0] +1: tmp[511:256] := b[255:0] +ESAC +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". [sae_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note] + +IF k[0] + dst[63:0] := MAX(a[63:0], b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := MAX(a[63:0], b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note] + +IF k[0] + dst[63:0] := MAX(a[63:0], b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := MAX(a[63:0], b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [sae_note] + +dst[63:0] := MAX(a[63:0], b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +IF k[0] + dst[31:0] := MAX(a[31:0], b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := MAX(a[31:0], b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +IF k[0] + dst[31:0] := MAX(a[31:0], b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := MAX(a[31:0], b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +dst[31:0] := MAX(a[31:0], b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [sae_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". [sae_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note] + +IF k[0] + dst[63:0] := MIN(a[63:0], b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := MIN(a[63:0], b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [sae_note] + +IF k[0] + dst[63:0] := MIN(a[63:0], b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := MIN(a[63:0], b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" , and copy the upper element from "a" to the upper element of "dst". [sae_note] + +dst[63:0] := MIN(a[63:0], b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +IF k[0] + dst[31:0] := MIN(a[31:0], b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := MIN(a[31:0], b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +IF k[0] + dst[31:0] := MIN(a[31:0], b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := MIN(a[31:0], b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [sae_note] + +dst[31:0] := MIN(a[31:0], b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + Move packed double-precision (64-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + Move packed single-precision (32-bit) floating-point elements from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[63:0] := a[63:0] +tmp[127:64] := a[63:0] +tmp[191:128] := a[191:128] +tmp[255:192] := a[191:128] +tmp[319:256] := a[319:256] +tmp[383:320] := a[319:256] +tmp[447:384] := a[447:384] +tmp[511:448] := a[447:384] +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[63:0] := a[63:0] +tmp[127:64] := a[63:0] +tmp[191:128] := a[191:128] +tmp[255:192] := a[191:128] +tmp[319:256] := a[319:256] +tmp[383:320] := a[319:256] +tmp[447:384] := a[447:384] +tmp[511:448] := a[447:384] +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + Duplicate even-indexed double-precision (64-bit) floating-point elements from "a", and store the results in "dst". + +dst[63:0] := a[63:0] +dst[127:64] := a[63:0] +dst[191:128] := a[191:128] +dst[255:192] := a[191:128] +dst[319:256] := a[319:256] +dst[383:320] := a[319:256] +dst[447:384] := a[447:384] +dst[511:448] := a[447:384] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Move + + + + Move packed 32-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Move + + + + Move packed 64-bit integers from "a" into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + Load 512-bits of integer data from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + Store packed 32-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + Load packed 32-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + Store 512-bits of integer data from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + Store packed 64-bit integers from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + Load packed 64-bit integers from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + Load 512-bits of integer data from memory into "dst" using a non-temporal memory hint. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + Store 512-bits of integer data from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper element of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +IF k[0] + dst[63:0] := MEM[mem_addr+63:mem_addr] +ELSE + dst[63:0] := src[63:0] +FI +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + + Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + Store the lower double-precision (64-bit) floating-point element from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +IF k[0] + MEM[mem_addr+63:mem_addr] := a[63:0] +FI + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper element of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +IF k[0] + dst[63:0] := MEM[mem_addr+63:mem_addr] +ELSE + dst[63:0] := 0 +FI +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[31:0] := a[63:32] +tmp[63:32] := a[63:32] +tmp[95:64] := a[127:96] +tmp[127:96] := a[127:96] +tmp[159:128] := a[191:160] +tmp[191:160] := a[191:160] +tmp[223:192] := a[255:224] +tmp[255:224] := a[255:224] +tmp[287:256] := a[319:288] +tmp[319:288] := a[319:288] +tmp[351:320] := a[383:352] +tmp[383:352] := a[383:352] +tmp[415:384] := a[447:416] +tmp[447:416] := a[447:416] +tmp[479:448] := a[511:480] +tmp[511:480] := a[511:480] +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[31:0] := a[63:32] +tmp[63:32] := a[63:32] +tmp[95:64] := a[127:96] +tmp[127:96] := a[127:96] +tmp[159:128] := a[191:160] +tmp[191:160] := a[191:160] +tmp[223:192] := a[255:224] +tmp[255:224] := a[255:224] +tmp[287:256] := a[319:288] +tmp[319:288] := a[319:288] +tmp[351:320] := a[383:352] +tmp[383:352] := a[383:352] +tmp[415:384] := a[447:416] +tmp[447:416] := a[447:416] +tmp[479:448] := a[511:480] +tmp[511:480] := a[511:480] +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst". + +dst[31:0] := a[63:32] +dst[63:32] := a[63:32] +dst[95:64] := a[127:96] +dst[127:96] := a[127:96] +dst[159:128] := a[191:160] +dst[191:160] := a[191:160] +dst[223:192] := a[255:224] +dst[255:224] := a[255:224] +dst[287:256] := a[319:288] +dst[319:288] := a[319:288] +dst[351:320] := a[383:352] +dst[383:352] := a[383:352] +dst[415:384] := a[447:416] +dst[447:416] := a[447:416] +dst[479:448] := a[511:480] +dst[511:480] := a[511:480] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp[31:0] := a[31:0] +tmp[63:32] := a[31:0] +tmp[95:64] := a[95:64] +tmp[127:96] := a[95:64] +tmp[159:128] := a[159:128] +tmp[191:160] := a[159:128] +tmp[223:192] := a[223:192] +tmp[255:224] := a[223:192] +tmp[287:256] := a[287:256] +tmp[319:288] := a[287:256] +tmp[351:320] := a[351:320] +tmp[383:352] := a[351:320] +tmp[415:384] := a[415:384] +tmp[447:416] := a[415:384] +tmp[479:448] := a[479:448] +tmp[511:480] := a[479:448] +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp[31:0] := a[31:0] +tmp[63:32] := a[31:0] +tmp[95:64] := a[95:64] +tmp[127:96] := a[95:64] +tmp[159:128] := a[159:128] +tmp[191:160] := a[159:128] +tmp[223:192] := a[223:192] +tmp[255:224] := a[223:192] +tmp[287:256] := a[287:256] +tmp[319:288] := a[287:256] +tmp[351:320] := a[351:320] +tmp[383:352] := a[351:320] +tmp[415:384] := a[415:384] +tmp[447:416] := a[415:384] +tmp[479:448] := a[479:448] +tmp[511:480] := a[479:448] +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst". + +dst[31:0] := a[31:0] +dst[63:32] := a[31:0] +dst[95:64] := a[95:64] +dst[127:96] := a[95:64] +dst[159:128] := a[159:128] +dst[191:160] := a[159:128] +dst[223:192] := a[223:192] +dst[255:224] := a[223:192] +dst[287:256] := a[287:256] +dst[319:288] := a[287:256] +dst[351:320] := a[351:320] +dst[383:352] := a[351:320] +dst[415:384] := a[415:384] +dst[447:416] := a[415:384] +dst[479:448] := a[479:448] +dst[511:480] := a[479:448] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Load a single-precision (32-bit) floating-point element from memory into the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and set the upper elements of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +IF k[0] + dst[31:0] := MEM[mem_addr+31:mem_addr] +ELSE + dst[31:0] := src[31:0] +FI +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + + Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + Store the lower single-precision (32-bit) floating-point element from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +IF k[0] + MEM[mem_addr+31:mem_addr] := a[31:0] +FI + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + Load a single-precision (32-bit) floating-point element from memory into the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and set the upper elements of "dst" to zero. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +IF k[0] + dst[31:0] := MEM[mem_addr+31:mem_addr] +ELSE + dst[31:0] := 0 +FI +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Move + + + + + Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + Load 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + Load packed double-precision (64-bit) floating-point elements from memoy into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + Load 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Load + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] * b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] * b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] * b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] * b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := a[63:0] * b[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] * b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] * b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] * b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] * b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := a[31:0] * b[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ABS(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ABS(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + Compute the absolute value of packed signed 64-bit integers in "a", and store the unsigned results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] AND b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (NOT a[i+63:i]) AND b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] AND b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + Broadcast 8-bit integer "a" to all elements of "dst". + +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + Broadcast 32-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Broadcast the low packed 32-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + Broadcast 32-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[31:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + Broadcast 32-bit integer "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + Broadcast 64-bit integer "a" to all elements of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Broadcast the low packed 64-bit integer from "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + Broadcast 64-bit integer "a" to all elements of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[63:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + Broadcast 64-bit integer "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + + Broadcast the low packed 16-bit integer from "a" to all all elements of "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + + Compare packed signed 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed signed 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + + Compare packed unsigned 64-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] == b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] >= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] > b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] <= b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] < b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Compare + + + + + Compare packed unsigned 64-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] != b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 32 +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[511:m] := src[511:m] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + Swizzle + + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 32 +m := base_addr +FOR j := 0 to 15 + i := j*32 + IF k[j] + MEM[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Contiguously store the active 32-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 32 +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[m+size-1:m] := a[i+31:i] + m := m + size + FI +ENDFOR +dst[511:m] := 0 +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 64 +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[511:m] := src[511:m] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + Swizzle + + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 64 +m := base_addr +FOR j := 0 to 7 + i := j*64 + IF k[j] + MEM[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Contiguously store the active 64-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 64 +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[m+size-1:m] := a[i+63:i] + m := m + size + FI +ENDFOR +dst[511:m] := 0 +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := idx[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := (idx[i+4]) ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 32-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off] +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set) + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := idx[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := (idx[i+3]) ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off] +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := idx[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := (idx[i+4]) ? b[off+31:off] : a[off+31:off] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + off := idx[i+3:i]*32 + dst[i+31:i] := idx[i+4] ? b[off+31:off] : a[off+31:off] +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "idx" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := idx[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := (idx[i+3]) ? b[off+63:off] : a[off+63:off] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 64-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + off := idx[i+2:i]*64 + dst[i+63:i] := idx[i+3] ? b[off+63:off] : a[off+63:off] +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI +IF (imm8[4] == 0) tmp_dst[319:256] := a[319:256]; FI +IF (imm8[4] == 1) tmp_dst[319:256] := a[383:320]; FI +IF (imm8[5] == 0) tmp_dst[383:320] := a[319:256]; FI +IF (imm8[5] == 1) tmp_dst[383:320] := a[383:320]; FI +IF (imm8[6] == 0) tmp_dst[447:384] := a[447:384]; FI +IF (imm8[6] == 1) tmp_dst[447:384] := a[511:448]; FI +IF (imm8[7] == 0) tmp_dst[511:448] := a[447:384]; FI +IF (imm8[7] == 1) tmp_dst[511:448] := a[511:448]; FI +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI +IF (b[257] == 0) tmp_dst[319:256] := a[319:256]; FI +IF (b[257] == 1) tmp_dst[319:256] := a[383:320]; FI +IF (b[321] == 0) tmp_dst[383:320] := a[319:256]; FI +IF (b[321] == 1) tmp_dst[383:320] := a[383:320]; FI +IF (b[385] == 0) tmp_dst[447:384] := a[447:384]; FI +IF (b[385] == 1) tmp_dst[447:384] := a[511:448]; FI +IF (b[449] == 0) tmp_dst[511:448] := a[447:384]; FI +IF (b[449] == 1) tmp_dst[511:448] := a[511:448]; FI +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +IF (imm8[0] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (imm8[2] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (imm8[2] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (imm8[3] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (imm8[3] == 1) tmp_dst[255:192] := a[255:192]; FI +IF (imm8[4] == 0) tmp_dst[319:256] := a[319:256]; FI +IF (imm8[4] == 1) tmp_dst[319:256] := a[383:320]; FI +IF (imm8[5] == 0) tmp_dst[383:320] := a[319:256]; FI +IF (imm8[5] == 1) tmp_dst[383:320] := a[383:320]; FI +IF (imm8[6] == 0) tmp_dst[447:384] := a[447:384]; FI +IF (imm8[6] == 1) tmp_dst[447:384] := a[511:448]; FI +IF (imm8[7] == 0) tmp_dst[511:448] := a[447:384]; FI +IF (imm8[7] == 1) tmp_dst[511:448] := a[511:448]; FI +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +IF (b[1] == 0) tmp_dst[63:0] := a[63:0]; FI +IF (b[1] == 1) tmp_dst[63:0] := a[127:64]; FI +IF (b[65] == 0) tmp_dst[127:64] := a[63:0]; FI +IF (b[65] == 1) tmp_dst[127:64] := a[127:64]; FI +IF (b[129] == 0) tmp_dst[191:128] := a[191:128]; FI +IF (b[129] == 1) tmp_dst[191:128] := a[255:192]; FI +IF (b[193] == 0) tmp_dst[255:192] := a[191:128]; FI +IF (b[193] == 1) tmp_dst[255:192] := a[255:192]; FI +IF (b[257] == 0) tmp_dst[319:256] := a[319:256]; FI +IF (b[257] == 1) tmp_dst[319:256] := a[383:320]; FI +IF (b[321] == 0) tmp_dst[383:320] := a[319:256]; FI +IF (b[321] == 1) tmp_dst[383:320] := a[383:320]; FI +IF (b[385] == 0) tmp_dst[447:384] := a[447:384]; FI +IF (b[385] == 1) tmp_dst[447:384] := a[511:448]; FI +IF (b[449] == 0) tmp_dst[511:448] := a[447:384]; FI +IF (b[449] == 1) tmp_dst[511:448] := a[511:448]; FI +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +IF (imm8[0] == 0) dst[63:0] := a[63:0]; FI +IF (imm8[0] == 1) dst[63:0] := a[127:64]; FI +IF (imm8[1] == 0) dst[127:64] := a[63:0]; FI +IF (imm8[1] == 1) dst[127:64] := a[127:64]; FI +IF (imm8[2] == 0) dst[191:128] := a[191:128]; FI +IF (imm8[2] == 1) dst[191:128] := a[255:192]; FI +IF (imm8[3] == 0) dst[255:192] := a[191:128]; FI +IF (imm8[3] == 1) dst[255:192] := a[255:192]; FI +IF (imm8[4] == 0) dst[319:256] := a[319:256]; FI +IF (imm8[4] == 1) dst[319:256] := a[383:320]; FI +IF (imm8[5] == 0) dst[383:320] := a[319:256]; FI +IF (imm8[5] == 1) dst[383:320] := a[383:320]; FI +IF (imm8[6] == 0) dst[447:384] := a[447:384]; FI +IF (imm8[6] == 1) dst[447:384] := a[511:448]; FI +IF (imm8[7] == 0) dst[511:448] := a[447:384]; FI +IF (imm8[7] == 1) dst[511:448] := a[511:448]; FI +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst". + +IF (b[1] == 0) dst[63:0] := a[63:0]; FI +IF (b[1] == 1) dst[63:0] := a[127:64]; FI +IF (b[65] == 0) dst[127:64] := a[63:0]; FI +IF (b[65] == 1) dst[127:64] := a[127:64]; FI +IF (b[129] == 0) dst[191:128] := a[191:128]; FI +IF (b[129] == 1) dst[191:128] := a[255:192]; FI +IF (b[193] == 0) dst[255:192] := a[191:128]; FI +IF (b[193] == 1) dst[255:192] := a[255:192]; FI +IF (b[257] == 0) dst[319:256] := a[319:256]; FI +IF (b[257] == 1) dst[319:256] := a[383:320]; FI +IF (b[321] == 0) dst[383:320] := a[319:256]; FI +IF (b[321] == 1) dst[383:320] := a[383:320]; FI +IF (b[385] == 0) dst[447:384] := a[447:384]; FI +IF (b[385] == 1) dst[447:384] := a[511:448]; FI +IF (b[449] == 0) dst[511:448] := a[447:384]; FI +IF (b[449] == 1) dst[511:448] := a[511:448]; FI +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4]) +tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6]) +tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4]) +tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], b[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], b[33:32]) +tmp_dst[95:64] := SELECT4(a[127:0], b[65:64]) +tmp_dst[127:96] := SELECT4(a[127:0], b[97:96]) +tmp_dst[159:128] := SELECT4(a[255:128], b[129:128]) +tmp_dst[191:160] := SELECT4(a[255:128], b[161:160]) +tmp_dst[223:192] := SELECT4(a[255:128], b[193:192]) +tmp_dst[255:224] := SELECT4(a[255:128], b[225:224]) +tmp_dst[287:256] := SELECT4(a[383:256], b[257:256]) +tmp_dst[319:288] := SELECT4(a[383:256], b[289:288]) +tmp_dst[351:320] := SELECT4(a[383:256], b[321:320]) +tmp_dst[383:352] := SELECT4(a[383:256], b[353:352]) +tmp_dst[415:384] := SELECT4(a[511:384], b[385:384]) +tmp_dst[447:416] := SELECT4(a[511:384], b[417:416]) +tmp_dst[479:448] := SELECT4(a[511:384], b[449:448]) +tmp_dst[511:480] := SELECT4(a[511:384], b[481:480]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4]) +tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6]) +tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4]) +tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], b[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], b[33:32]) +tmp_dst[95:64] := SELECT4(a[127:0], b[65:64]) +tmp_dst[127:96] := SELECT4(a[127:0], b[97:96]) +tmp_dst[159:128] := SELECT4(a[255:128], b[129:128]) +tmp_dst[191:160] := SELECT4(a[255:128], b[161:160]) +tmp_dst[223:192] := SELECT4(a[255:128], b[193:192]) +tmp_dst[255:224] := SELECT4(a[255:128], b[225:224]) +tmp_dst[287:256] := SELECT4(a[383:256], b[257:256]) +tmp_dst[319:288] := SELECT4(a[383:256], b[289:288]) +tmp_dst[351:320] := SELECT4(a[383:256], b[321:320]) +tmp_dst[383:352] := SELECT4(a[383:256], b[353:352]) +tmp_dst[415:384] := SELECT4(a[511:384], b[385:384]) +tmp_dst[447:416] := SELECT4(a[511:384], b[417:416]) +tmp_dst[479:448] := SELECT4(a[511:384], b[449:448]) +tmp_dst[511:480] := SELECT4(a[511:384], b[481:480]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +dst[351:320] := SELECT4(a[383:256], imm8[5:4]) +dst[383:352] := SELECT4(a[383:256], imm8[7:6]) +dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +dst[479:448] := SELECT4(a[511:384], imm8[5:4]) +dst[511:480] := SELECT4(a[511:384], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], b[1:0]) +dst[63:32] := SELECT4(a[127:0], b[33:32]) +dst[95:64] := SELECT4(a[127:0], b[65:64]) +dst[127:96] := SELECT4(a[127:0], b[97:96]) +dst[159:128] := SELECT4(a[255:128], b[129:128]) +dst[191:160] := SELECT4(a[255:128], b[161:160]) +dst[223:192] := SELECT4(a[255:128], b[193:192]) +dst[255:224] := SELECT4(a[255:128], b[225:224]) +dst[287:256] := SELECT4(a[383:256], b[257:256]) +dst[319:288] := SELECT4(a[383:256], b[289:288]) +dst[351:320] := SELECT4(a[383:256], b[321:320]) +dst[383:352] := SELECT4(a[383:256], b[353:352]) +dst[415:384] := SELECT4(a[511:384], b[385:384]) +dst[447:416] := SELECT4(a[511:384], b[417:416]) +dst[479:448] := SELECT4(a[511:384], b[449:448]) +dst[511:480] := SELECT4(a[511:384], b[481:480]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0]) +tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2]) +tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4]) +tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + id := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0]) +tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2]) +tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4]) +tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + id := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +dst[319:256] := SELECT4(a[511:256], imm8[1:0]) +dst[383:320] := SELECT4(a[511:256], imm8[3:2]) +dst[447:384] := SELECT4(a[511:256], imm8[5:4]) +dst[511:448] := SELECT4(a[511:256], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle double-precision (64-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + id := idx[i+2:i]*64 + dst[i+63:i] := a[id+63:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Shuffle single-precision (32-bit) floating-point elements in "a" across lanes using the corresponding index in "idx". + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0]) +tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2]) +tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4]) +tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + id := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +tmp_dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +tmp_dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +tmp_dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +tmp_dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +tmp_dst[319:256] := SELECT4(a[511:256], imm8[1:0]) +tmp_dst[383:320] := SELECT4(a[511:256], imm8[3:2]) +tmp_dst[447:384] := SELECT4(a[511:256], imm8[5:4]) +tmp_dst[511:448] := SELECT4(a[511:256], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + id := idx[i+2:i]*64 + IF k[j] + dst[i+63:i] := a[id+63:id] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Shuffle 64-bit integers in "a" within 256-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[63:0] := src[63:0] + 1: tmp[63:0] := src[127:64] + 2: tmp[63:0] := src[191:128] + 3: tmp[63:0] := src[255:192] + ESAC + RETURN tmp[63:0] +} +dst[63:0] := SELECT4(a[255:0], imm8[1:0]) +dst[127:64] := SELECT4(a[255:0], imm8[3:2]) +dst[191:128] := SELECT4(a[255:0], imm8[5:4]) +dst[255:192] := SELECT4(a[255:0], imm8[7:6]) +dst[319:256] := SELECT4(a[511:256], imm8[1:0]) +dst[383:320] := SELECT4(a[511:256], imm8[3:2]) +dst[447:384] := SELECT4(a[511:256], imm8[5:4]) +dst[511:448] := SELECT4(a[511:256], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Shuffle 64-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + id := idx[i+2:i]*64 + dst[i+63:i] := a[id+63:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + Swizzle + + + + + Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Load contiguous active 32-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[m+31:m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + Swizzle + + + + Load contiguous active 32-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+m+31:mem_addr+m] + m := m + 32 + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + Swizzle + + + + + Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Load contiguous active 64-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[m+63:m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + Swizzle + + + + Load contiguous active 64-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+m+63:mem_addr+m] + m := m + 64 + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + + + Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + + + Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Load + + + + + + + Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + Compare packed signed 64-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Special Math Functions + + + + Compare packed unsigned 64-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 8*j + dst[k+7:k] := Truncate8(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed 32-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 16*j + dst[k+15:k] := Truncate16(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed 32-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 8*j + dst[k+7:k] := Truncate8(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Truncate8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 8-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Truncate8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[k+31:k] := Truncate32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Truncate32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := Truncate32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 32-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Truncate32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 16*j + dst[k+15:k] := Truncate16(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Truncate16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed 64-bit integers in "a" to packed 16-bit integers with truncation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Truncate16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 8*j + dst[k+7:k] := Saturate8(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 16*j + dst[k+15:k] := Saturate16(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed signed 32-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 8*j + dst[k+7:k] := Saturate8(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := Saturate8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 8-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := Saturate8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[k+31:k] := Saturate32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Saturate32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := Saturate32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 32-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := Saturate32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 16*j + dst[k+15:k] := Saturate16(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := Saturate16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed signed 64-bit integers in "a" to packed 16-bit integers with signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := Saturate16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 8*j + dst[i+31:i] := SignExtend32(a[k+7:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 8*j + dst[i+63:i] := SignExtend64(a[k+7:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[i+63:i] := SignExtend64(a[k+31:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 16*j + dst[i+31:i] := SignExtend32(a[k+15:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + l := j*16 + IF k[j] + dst[i+31:i] := SignExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := SignExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 16*j + dst[i+63:i] := SignExtend64(a[k+15:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := SignExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 8*j + dst[k+7:k] := SaturateU8(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+31:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed unsigned 32-bit integers in "a" to packed 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+31:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 16*j + dst[k+15:k] := SaturateU16(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+31:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed unsigned 32-bit integers in "a" to packed 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+31:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed unsigned 32-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+31:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 8*j + dst[k+7:k] := SaturateU8(a[i+63:i]) +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+63:i]) + ELSE + dst[l+7:l] := src[l+7:l] + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed 8-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + MEM[base_addr+l+7:base_addr+l] := SaturateU8(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 8-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[l+7:l] := SaturateU8(a[i+63:i]) + ELSE + dst[l+7:l] := 0 + FI +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[k+31:k] := SaturateU32(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := SaturateU32(a[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed 32-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + MEM[base_addr+l+31:base_addr+l] := SaturateU32(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 32-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[l+31:l] := SaturateU32(a[i+63:i]) + ELSE + dst[l+31:l] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 16*j + dst[k+15:k] := SaturateU16(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+63:i]) + ELSE + dst[l+15:l] := src[l+15:l] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + Store + + + + + Convert packed unsigned 64-bit integers in "a" to packed 16-bit integers with unsigned saturation, and store the active results (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + MEM[base_addr+l+15:base_addr+l] := SaturateU16(a[i+63:i]) + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Convert packed unsigned 64-bit integers in "a" to packed unsigned 16-bit integers with unsigned saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[l+15:l] := SaturateU16(a[i+63:i]) + ELSE + dst[l+15:l] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 8*j + dst[i+31:i] := ZeroExtend32(a[k+7:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 8*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+7:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 8*j + dst[i+63:i] := ZeroExtend64(a[k+7:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Zero extend packed unsigned 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 8*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+7:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 32*j + dst[i+63:i] := ZeroExtend64(a[k+31:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 32*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+31:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 15 + i := 32*j + k := 16*j + dst[i+31:i] := ZeroExtend32(a[k+15:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + l := 16*j + IF k[j] + dst[i+31:i] := ZeroExtend32(a[l+15:l]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := 64*j + k := 16*j + dst[i+63:i] := ZeroExtend64(a[k+15:k]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + + Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := 64*j + l := 16*j + IF k[j] + dst[i+63:i] := ZeroExtend64(a[l+15:l]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+31:i] * b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE LEFT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src << count) OR (src >> (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LEFT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the left by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE LEFT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src << count) OR (src >> (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := LEFT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in "imm8", and store the results in "dst". + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Miscellaneous + + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 32-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE RIGHT_ROTATE_DWORDS(src, count_src) { + count := count_src % 32 + RETURN (src >>count) OR (src << (32 - count)) +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RIGHT_ROTATE_DWORDS(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Rotate the bits in each packed 64-bit integer in "a" to the right by the number of bits specified in the corresponding element of "b", and store the results in "dst". + +DEFINE RIGHT_ROTATE_QWORDS(src, count_src) { + count := count_src % 64 + RETURN (src >> count) OR (src << (64 - count)) +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RIGHT_ROTATE_QWORDS(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + + Scatter 64-bit integers from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + + Scatter 32-bit integers from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + + Scatter 64-bit integers from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4]) +tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6]) +tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4]) +tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0x0) + ELSE + dst[i+63:i] := SignExtend64(a[i+63:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := SignExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := (a[i+63] ? 0xFFFFFFFFFFFFFFFF : 0) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Shift + + + + Shift packed 64-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF count[i+63:i] < 64 + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 32-bit granularity (32-bit elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + FOR h := 0 to 31 + index[2:0] := (src[i+h] << 2) OR (a[i+h] << 1) OR b[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 32-bit granularity (32-bit elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + FOR h := 0 to 31 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 32-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst". + +FOR j := 0 to 15 + i := j*32 + FOR h := 0 to 31 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "src", "a", and "b" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using writemask "k" at 64-bit granularity (64-bit elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + FOR h := 0 to 63 + index[2:0] := (src[i+h] << 2) OR (a[i+h] << 1) OR b[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst" using zeromask "k" at 64-bit granularity (64-bit elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + FOR h := 0 to 63 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + + Bitwise ternary logic that provides the capability to implement any three-operand binary function; the specific binary function is specified by value in "imm8". For each bit in each packed 64-bit integer, the corresponding bit from "a", "b", and "c" are used to form a 3 bit index into "imm8", and the value at that bit in "imm8" is written to the corresponding bit in "dst". + +FOR j := 0 to 7 + i := j*64 + FOR h := 0 to 63 + index[2:0] := (a[i+h] << 2) OR (b[i+h] << 1) OR c[i+h] + dst[i+h] := imm8[index[2:0]] + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Logical + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Logical + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 7 + i := j*64 + k[j] := ((a[i+63:i] AND b[i+63:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Logical + + + + + Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Logical + + + + Compute the bitwise NAND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 15 + i := j*32 + k[j] := ((a[i+31:i] AND b[i+31:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Logical + + + + + Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is zero. + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F + Logical + + + + Compute the bitwise NAND of packed 64-bit integers in "a" and "b", producing intermediate 64-bit values, and set the corresponding bit in result mask "k" if the intermediate value is zero. + +FOR j := 0 to 7 + i := j*64 + k[j] := ((a[i+63:i] AND b[i+63:i]) == 0) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Unpack and interleave 32-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Unpack and interleave 64-bit integers from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Unpack and interleave 32-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + Unpack and interleave 64-bit integers from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Logical + + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the approximate reciprocal of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[63:0] := (1.0 / b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[63:0] := (1.0 / b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14. + +dst[63:0] := (1.0 / b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[31:0] := (1.0 / b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[31:0] := (1.0 / b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14. + +dst[31:0] := (1.0 / b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Round packed double-precision (64-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RoundScaleFP64(a[i+63:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). [round_imm_note][sae_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Round packed single-precision (32-bit) floating-point elements in "a" to the number of fraction bits specified by "imm8", and store the results in "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RoundScaleFP32(a[i+31:i], imm8[7:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +IF k[0] + dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Round the lower double-precision (64-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". [round_imm_note] + +DEFINE RoundScaleFP64(src1[63:0], imm8[7:0]) { + m[63:0] := FP64(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[63:0] := POW(2.0, -m) * ROUND(POW(2.0, m) * src1[63:0], imm8[3:0]) + IF IsInf(tmp[63:0]) + tmp[63:0] := src1[63:0] + FI + RETURN tmp[63:0] +} +dst[63:0] := RoundScaleFP64(b[63:0], imm8[7:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + + Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +IF k[0] + dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note][sae_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Round the lower single-precision (32-bit) floating-point element in "b" to the number of fraction bits specified by "imm8", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". [round_imm_note] + +DEFINE RoundScaleFP32(src1[31:0], imm8[7:0]) { + m[31:0] := FP32(imm8[7:4]) // number of fraction bits after the binary point to be preserved + tmp[31:0] := POW(FP32(2.0), -m) * ROUND(POW(FP32(2.0), m) * src1[31:0], imm8[3:0]) + IF IsInf(tmp[31:0]) + tmp[31:0] := src1[31:0] + FI + RETURN tmp[31:0] +} +dst[31:0] := RoundScaleFP32(b[31:0], imm8[7:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the approximate reciprocal square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / SQRT(a[i+63:i])) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 2^-14. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[63:0] := (1.0 / SQRT(b[63:0])) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[63:0] := (1.0 / SQRT(b[63:0])) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". The maximum relative error for this approximation is less than 2^-14. + +dst[63:0] := (1.0 / SQRT(b[63:0])) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[31:0] := (1.0 / SQRT(b[31:0])) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14. + +IF k[0] + dst[31:0] := (1.0 / SQRT(b[31:0])) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 2^-14. + +dst[31:0] := (1.0 / SQRT(b[31:0])) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SCALE(a[i+63:0], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", and store the results in "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[31:0] +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SCALE(a[i+31:0], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +IF k[0] + dst[63:0] := SCALE(a[63:0], b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +IF k[0] + dst[63:0] := SCALE(a[63:0], b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +IF k[0] + dst[63:0] := SCALE(a[63:0], b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +IF k[0] + dst[63:0] := SCALE(a[63:0], b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +dst[63:0] := SCALE(a[63:0], b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Scale the packed double-precision (64-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[63:0] := tmp_src1[63:0] * POW(2.0, FLOOR(tmp_src2[63:0])) + RETURN dst[63:0] +} +dst[63:0] := SCALE(a[63:0], b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[63:0] +} +IF k[0] + dst[31:0] := SCALE(a[31:0], b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[63:0] +} +IF k[0] + dst[31:0] := SCALE(a[31:0], b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[63:0] +} +IF k[0] + dst[31:0] := SCALE(a[31:0], b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[63:0] +} +IF k[0] + dst[31:0] := SCALE(a[31:0], b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[63:0] +} +dst[31:0] := SCALE(a[31:0], b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Miscellaneous + + + + Scale the packed single-precision (32-bit) floating-point elements in "a" using values from "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + DEFINE SCALE(src1, src2) { + IF (src2 == NaN) + IF (src2 == SNaN) + RETURN QNAN(src2) + FI + ELSE IF (src1 == NaN) + IF (src1 == SNaN) + RETURN QNAN(src1) + FI + IF (src2 != INF) + RETURN QNAN(src1) + FI + ELSE + tmp_src2 := src2 + tmp_src1 := src1 + IF (IS_DENORMAL(src2) AND MXCSR.DAZ) + tmp_src2 := 0 + FI + IF (IS_DENORMAL(src1) AND MXCSR.DAZ) + tmp_src1 := 0 + FI + FI + dst[31:0] := tmp_src1[31:0] * POW(2.0, FLOOR(tmp_src2[31:0])) + RETURN dst[63:0] +} +dst[31:0] := SCALE(a[31:0], b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 32-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + + + Scatter double-precision (64-bit) floating-point elements from "a" into memory using 64-bit indices. 64-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Store + + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 64-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + + Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle 128-bits (composed of 4 single-precision (32-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + + Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle 128-bits (composed of 2 double-precision (64-bit) floating-point elements) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + + Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 128-bits (composed of 4 32-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + + Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + + Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp_dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +tmp_dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +tmp_dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +tmp_dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Swizzle + + + + + Shuffle 128-bits (composed of 2 64-bit integers) selected by "imm8" from "a" and "b", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +dst[127:0] := SELECT4(a[511:0], imm8[1:0]) +dst[255:128] := SELECT4(a[511:0], imm8[3:2]) +dst[383:256] := SELECT4(b[511:0], imm8[5:4]) +dst[511:384] := SELECT4(b[511:0], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + + Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192] +tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192] +tmp_dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320] +tmp_dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320] +tmp_dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448] +tmp_dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448] +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +tmp_dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +tmp_dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +tmp_dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192] +tmp_dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192] +tmp_dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320] +tmp_dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320] +tmp_dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448] +tmp_dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448] +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in "imm8", and store the results in "dst". + +dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] +dst[191:128] := (imm8[2] == 0) ? a[191:128] : a[255:192] +dst[255:192] := (imm8[3] == 0) ? b[191:128] : b[255:192] +dst[319:256] := (imm8[4] == 0) ? a[319:256] : a[383:320] +dst[383:320] := (imm8[5] == 0) ? b[319:256] : b[383:320] +dst[447:384] := (imm8[6] == 0) ? a[447:384] : a[511:448] +dst[511:448] := (imm8[7] == 0) ? b[447:384] : b[511:448] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6]) +tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +tmp_dst[351:320] := SELECT4(b[383:256], imm8[5:4]) +tmp_dst[383:352] := SELECT4(b[383:256], imm8[7:6]) +tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +tmp_dst[479:448] := SELECT4(b[511:384], imm8[5:4]) +tmp_dst[511:480] := SELECT4(b[511:384], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(b[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(b[255:128], imm8[7:6]) +tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +tmp_dst[351:320] := SELECT4(b[383:256], imm8[5:4]) +tmp_dst[383:352] := SELECT4(b[383:256], imm8[7:6]) +tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +tmp_dst[479:448] := SELECT4(b[511:384], imm8[5:4]) +tmp_dst[511:480] := SELECT4(b[511:384], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +dst[127:96] := SELECT4(b[127:0], imm8[7:6]) +dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +dst[223:192] := SELECT4(b[255:128], imm8[5:4]) +dst[255:224] := SELECT4(b[255:128], imm8[7:6]) +dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +dst[351:320] := SELECT4(b[383:256], imm8[5:4]) +dst[383:352] := SELECT4(b[383:256], imm8[7:6]) +dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +dst[479:448] := SELECT4(b[511:384], imm8[5:4]) +dst[511:480] := SELECT4(b[511:384], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note]. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SQRT(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + [round_note]. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SQRT(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SQRT(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + [round_note]. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SQRT(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + + Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := SQRT(b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := SQRT(b[63:0]) +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := SQRT(b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := SQRT(b[63:0]) +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := SQRT(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + + Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := SQRT(b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := SQRT(b[31:0]) +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := SQRT(b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := SQRT(b[31:0]) +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the square root of the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := SQRT(b[31:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] - b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] - b[63:0] +ELSE + dst[63:0] := src[63:0] +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + [round_note] + +IF k[0] + dst[63:0] := a[63:0] - b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper element from "a" to the upper element of "dst". + +IF k[0] + dst[63:0] := a[63:0] - b[63:0] +ELSE + dst[63:0] := 0 +FI +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := a[63:0] - b[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + + Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] - b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using writemask "k" (the element is copied from "src" when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] - b[31:0] +ELSE + dst[31:0] := src[31:0] +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + + Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +IF k[0] + dst[31:0] := a[31:0] - b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set), and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +IF k[0] + dst[31:0] := a[31:0] - b[31:0] +ELSE + dst[31:0] := 0 +FI +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Arithmetic + + + + + Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := a[31:0] - b[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_QWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_HIGH_QWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_HIGH_QWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_HIGH_DWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_HIGH_DWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_HIGH_DWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384]) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := tmp_dst[i+63:i] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_QWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_QWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_QWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +tmp_dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +tmp_dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +tmp_dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256]) +tmp_dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Swizzle + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) +dst[255:128] := INTERLEAVE_DWORDS(a[255:128], b[255:128]) +dst[383:256] := INTERLEAVE_DWORDS(a[383:256], b[383:256]) +dst[511:384] := INTERLEAVE_DWORDS(a[511:384], b[511:384]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are undefined. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are undefined. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m512d to type __m128d. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m512 to type __m128. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m512d to type __m256d. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m128 to type __m512; the upper 384 bits of the result are undefined. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m256 to type __m512; the upper 256 bits of the result are undefined. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m512 to type __m256. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F + Cast + + + Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are undefined. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F + Cast + + + Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are undefined. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F + Cast + + + Cast vector of type __m512i to type __m128i. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F + Cast + + + Cast vector of type __m512i to type __m256i. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m128d to type __m512d; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m128 to type __m512; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F + Cast + + + Cast vector of type __m128i to type __m512i; the upper 384 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m256d to type __m512d; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Cast + + + Cast vector of type __m256 to type __m512; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F + Cast + + + Cast vector of type __m256i to type __m512i; the upper 256 bits of the result are zeroed. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + Set packed 32-bit integers in "dst" with the repeated 4 element sequence. + +dst[31:0] := a +dst[63:32] := b +dst[95:64] := c +dst[127:96] := d +dst[159:128] := a +dst[191:160] := b +dst[223:192] := c +dst[255:224] := d +dst[287:256] := a +dst[319:288] := b +dst[351:320] := c +dst[383:352] := d +dst[415:384] := a +dst[447:416] := b +dst[479:448] := c +dst[511:480] := d +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + Set packed 64-bit integers in "dst" with the repeated 4 element sequence. + +dst[63:0] := a +dst[127:64] := b +dst[191:128] := c +dst[255:192] := d +dst[319:256] := a +dst[383:320] := b +dst[447:384] := c +dst[511:448] := d +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the repeated 4 element sequence. + +dst[63:0] := a +dst[127:64] := b +dst[191:128] := c +dst[255:192] := d +dst[319:256] := a +dst[383:320] := b +dst[447:384] := c +dst[511:448] := d +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the repeated 4 element sequence. + +dst[31:0] := a +dst[63:32] := b +dst[95:64] := c +dst[127:96] := d +dst[159:128] := a +dst[191:160] := b +dst[223:192] := c +dst[255:224] := d +dst[287:256] := a +dst[319:288] := b +dst[351:320] := c +dst[383:352] := d +dst[415:384] := a +dst[447:416] := b +dst[479:448] := c +dst[511:480] := d +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values. + +dst[7:0] := e0 +dst[15:8] := e1 +dst[23:16] := e2 +dst[31:24] := e3 +dst[39:32] := e4 +dst[47:40] := e5 +dst[55:48] := e6 +dst[63:56] := e7 +dst[71:64] := e8 +dst[79:72] := e9 +dst[87:80] := e10 +dst[95:88] := e11 +dst[103:96] := e12 +dst[111:104] := e13 +dst[119:112] := e14 +dst[127:120] := e15 +dst[135:128] := e16 +dst[143:136] := e17 +dst[151:144] := e18 +dst[159:152] := e19 +dst[167:160] := e20 +dst[175:168] := e21 +dst[183:176] := e22 +dst[191:184] := e23 +dst[199:192] := e24 +dst[207:200] := e25 +dst[215:208] := e26 +dst[223:216] := e27 +dst[231:224] := e28 +dst[239:232] := e29 +dst[247:240] := e30 +dst[255:248] := e31 +dst[263:256] := e32 +dst[271:264] := e33 +dst[279:272] := e34 +dst[287:280] := e35 +dst[295:288] := e36 +dst[303:296] := e37 +dst[311:304] := e38 +dst[319:312] := e39 +dst[327:320] := e40 +dst[335:328] := e41 +dst[343:336] := e42 +dst[351:344] := e43 +dst[359:352] := e44 +dst[367:360] := e45 +dst[375:368] := e46 +dst[383:376] := e47 +dst[391:384] := e48 +dst[399:392] := e49 +dst[407:400] := e50 +dst[415:408] := e51 +dst[423:416] := e52 +dst[431:424] := e53 +dst[439:432] := e54 +dst[447:440] := e55 +dst[455:448] := e56 +dst[463:456] := e57 +dst[471:464] := e58 +dst[479:472] := e59 +dst[487:480] := e60 +dst[495:488] := e61 +dst[503:496] := e62 +dst[511:504] := e63 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Set packed 16-bit integers in "dst" with the supplied values. + +dst[15:0] := e0 +dst[31:16] := e1 +dst[47:32] := e2 +dst[63:48] := e3 +dst[79:64] := e4 +dst[95:80] := e5 +dst[111:96] := e6 +dst[127:112] := e7 +dst[143:128] := e8 +dst[159:144] := e9 +dst[175:160] := e10 +dst[191:176] := e11 +dst[207:192] := e12 +dst[223:208] := e13 +dst[239:224] := e14 +dst[255:240] := e15 +dst[271:256] := e16 +dst[287:272] := e17 +dst[303:288] := e18 +dst[319:304] := e19 +dst[335:320] := e20 +dst[351:336] := e21 +dst[367:352] := e22 +dst[383:368] := e23 +dst[399:384] := e24 +dst[415:400] := e25 +dst[431:416] := e26 +dst[447:432] := e27 +dst[463:448] := e28 +dst[479:464] := e29 +dst[495:480] := e30 +dst[511:496] := e31 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + + + + + + + + + + + + + Set packed 32-bit integers in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 +dst[95:64] := e2 +dst[127:96] := e3 +dst[159:128] := e4 +dst[191:160] := e5 +dst[223:192] := e6 +dst[255:224] := e7 +dst[287:256] := e8 +dst[319:288] := e9 +dst[351:320] := e10 +dst[383:352] := e11 +dst[415:384] := e12 +dst[447:416] := e13 +dst[479:448] := e14 +dst[511:480] := e15 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + + + + + Set packed 64-bit integers in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 +dst[191:128] := e2 +dst[255:192] := e3 +dst[319:256] := e4 +dst[383:320] := e5 +dst[447:384] := e6 +dst[511:448] := e7 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 +dst[191:128] := e2 +dst[255:192] := e3 +dst[319:256] := e4 +dst[383:320] := e5 +dst[447:384] := e6 +dst[511:448] := e7 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + + + + + + + + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 +dst[95:64] := e2 +dst[127:96] := e3 +dst[159:128] := e4 +dst[191:160] := e5 +dst[223:192] := e6 +dst[255:224] := e7 +dst[287:256] := e8 +dst[319:288] := e9 +dst[351:320] := e10 +dst[383:352] := e11 +dst[415:384] := e12 +dst[447:416] := e13 +dst[479:448] := e14 +dst[511:480] := e15 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + Set packed 32-bit integers in "dst" with the repeated 4 element sequence in reverse order. + +dst[31:0] := d +dst[63:32] := c +dst[95:64] := b +dst[127:96] := a +dst[159:128] := d +dst[191:160] := c +dst[223:192] := b +dst[255:224] := a +dst[287:256] := d +dst[319:288] := c +dst[351:320] := b +dst[383:352] := a +dst[415:384] := d +dst[447:416] := c +dst[479:448] := b +dst[511:480] := a +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + Set packed 64-bit integers in "dst" with the repeated 4 element sequence in reverse order. + +dst[63:0] := d +dst[127:64] := c +dst[191:128] := b +dst[255:192] := a +dst[319:256] := d +dst[383:320] := c +dst[447:384] := b +dst[511:448] := a +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the repeated 4 element sequence in reverse order. + +dst[63:0] := d +dst[127:64] := c +dst[191:128] := b +dst[255:192] := a +dst[319:256] := d +dst[383:320] := c +dst[447:384] := b +dst[511:448] := a +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the repeated 4 element sequence in reverse order. + +dst[31:0] := d +dst[63:32] := c +dst[95:64] := b +dst[127:96] := a +dst[159:128] := d +dst[191:160] := c +dst[223:192] := b +dst[255:224] := a +dst[287:256] := d +dst[319:288] := c +dst[351:320] := b +dst[383:352] := a +dst[415:384] := d +dst[447:416] := c +dst[479:448] := b +dst[511:480] := a +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + + + + + + + + + + + + + Set packed 32-bit integers in "dst" with the supplied values in reverse order. + +dst[31:0] := e15 +dst[63:32] := e14 +dst[95:64] := e13 +dst[127:96] := e12 +dst[159:128] := e11 +dst[191:160] := e10 +dst[223:192] := e9 +dst[255:224] := e8 +dst[287:256] := e7 +dst[319:288] := e6 +dst[351:320] := e5 +dst[383:352] := e4 +dst[415:384] := e3 +dst[447:416] := e2 +dst[479:448] := e1 +dst[511:480] := e0 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Set + + + + + + + + + + Set packed 64-bit integers in "dst" with the supplied values in reverse order. + +dst[63:0] := e7 +dst[127:64] := e6 +dst[191:128] := e5 +dst[255:192] := e4 +dst[319:256] := e3 +dst[383:320] := e2 +dst[447:384] := e1 +dst[511:448] := e0 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order. + +dst[63:0] := e7 +dst[127:64] := e6 +dst[191:128] := e5 +dst[255:192] := e4 +dst[319:256] := e3 +dst[383:320] := e2 +dst[447:384] := e1 +dst[511:448] := e0 +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + + + + + + + + + + + + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order. + +dst[31:0] := e15 +dst[63:32] := e14 +dst[95:64] := e13 +dst[127:96] := e12 +dst[159:128] := e11 +dst[191:160] := e10 +dst[223:192] := e9 +dst[255:224] := e8 +dst[287:256] := e7 +dst[319:288] := e6 +dst[351:320] := e5 +dst[383:352] := e4 +dst[415:384] := e3 +dst[447:416] := e2 +dst[479:448] := e1 +dst[511:480] := e0 +dst[MAX:512] := 0 + +

immintrin.h

+ + + AVX512F + Set + + + Return vector of type __m512 with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + Return vector of type __m512i with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + Return vector of type __m512d with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F + Set + + Return vector of type __m512 with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + Integer + AVX512F + Set + + Return vector of type __m512i with all elements set to zero. + +dst[MAX:0] := 0 + + +

immintrin.h

+ + + AVX512F + General Support + + + Return vector of type __m512 with undefined elements. +

immintrin.h

+ + + Integer + AVX512F + General Support + + Return vector of type __m512i with undefined elements. +

immintrin.h

+ + + Floating Point + AVX512F + General Support + + Return vector of type __m512d with undefined elements. +

immintrin.h

+ + + Floating Point + AVX512F + General Support + + Return vector of type __m512 with undefined elements. +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ACOS(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ACOS(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ACOS(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ACOS(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ACOSH(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ACOSH(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ACOSH(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ACOSH(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ASIN(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ASIN(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ASIN(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ASIN(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ASINH(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ASINH(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ASINH(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ASINH(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" and store the results in "dst" expressed in radians. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ATAN(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ATAN(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" expressed in radians. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ATAN(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ATAN(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" and store the results in "dst" expressed in radians. + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ATANH(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" expressed in radians using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ATANH(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the inverse hyperblic tangent of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" expressed in radians. + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ATANH(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ATANH(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := CubeRoot(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := CubeRoot(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := CubeRoot(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := CubeRoot(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := CDFNormal(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := CDFNormal(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := CDFNormal(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := CDFNormal(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := InverseCDFNormal(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := InverseCDFNormal(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := InverseCDFNormal(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := InverseCDFNormal(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := CEIL(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := CEIL(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := CEIL(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := CEIL(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := COS(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := COS(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := COS(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := COS(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := COSD(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := COSD(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := COSD(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := COSD(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := COSH(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := COSH(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := COSH(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := COSH(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ERF(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ERF(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := 1.0 - ERF(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := 1.0 - ERF(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ERF(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ERF(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+63:i] := 1.0 - ERF(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+63:i] := 1.0 - ERF(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := 1.0 / ERF(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := 1.0 / ERF(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+63:i] := 1.0 / ERF(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+63:i] := 1.0 / ERF(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i])) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i])) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i])) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Probability/Statistics + + + + + Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(10.0, a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(10.0, a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(FP32(10.0), a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(10.0), a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(2.0, a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(2.0, a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(e, a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(e, a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(FP32(e), a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(e), a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(e, a[i+63:i]) - 1.0 +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(e, a[i+63:i]) - 1.0 + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0 +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := FLOOR(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FLOOR(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FLOOR(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FLOOR(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0)) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0)) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0)) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0)) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 15 + i := 32*j + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Divide packed signed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 63 + i := 8*j + IF b[i+7:i] == 0 + #DE + FI + dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 31 + i := 16*j + IF b[i+15:i] == 0 + #DE + FI + dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 7 + i := 64*j + IF b[i+63:i] == 0 + #DE + FI + dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := InvSQRT(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := InvSQRT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := InvSQRT(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := InvSQRT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 63 + i := 8*j + dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 31 + i := 16*j + dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 7 + i := 64*j + dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := LOG(1.0 + a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LOG(1.0 + a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LOG(1.0 + a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LOG(1.0 + a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := LOG(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LOG(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Rounds each packed double-precision (64-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := NearbyInt(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Rounds each packed double-precision (64-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := NearbyInt(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Rounds each packed single-precision (32-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := NearbyInt(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Rounds each packed single-precision (32-bit) floating-point element in "a" to the nearest integer value and stores the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := NearbyInt(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POW(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POW(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POW(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + + Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POW(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Computes the reciprocal of packed double-precision (64-bit) floating-point elements in "a", storing the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (1.0 / a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Computes the reciprocal of packed double-precision (64-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (1.0 / a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + Computes the reciprocal of packed single-precision (32-bit) floating-point elements in "a", storing the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Elementary Math Functions + + + + + Computes the reciprocal of packed single-precision (32-bit) floating-point elements in "a", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Rounds the packed double-precision (64-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := RoundToNearestEven(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Rounds the packed double-precision (64-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := RoundToNearestEven(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Rounds the packed single-precision (32-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := RoundToNearestEven(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Rounds the packed single-precision (32-bit) floating-point elements in "a" to the nearest even integer value and stores the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := RoundToNearestEven(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ROUND(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ROUND(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SIN(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SIN(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SIN(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SIN(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SINH(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SINH(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SINH(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SINH(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SIND(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SIND(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SIND(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SIND(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := TAN(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := TAN(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := TAN(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := TAN(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := TAND(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := TAND(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := TAND(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := TAND(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := TANH(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := TANH(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := TANH(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := TANH(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := TRUNCATE(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := TRUNCATE(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := TRUNCATE(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Special Math Functions + + + + + Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := TRUNCATE(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 15 + i := 32*j + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := 32*j + IF k[j] + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 63 + i := 8*j + IF b[i+7:i] == 0 + #DE + FI + dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 31 + i := 16*j + IF b[i+15:i] == 0 + #DE + FI + dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 7 + i := 64*j + IF b[i+63:i] == 0 + #DE + FI + dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 15 + i := 32*j + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := 32*j + IF k[j] + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 63 + i := 8*j + dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 31 + i := 16*j + dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Arithmetic + + + + Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 7 + i := 64*j + dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Performs bitwise OR between "k1" and "k2", storing the result in "dst". ZF flag is set if "dst" is 0. + dst[15:0] := k1[15:0] | k2[15:0] +IF dst == 0 + SetZF() +FI + + +

immintrin.h

+ + + Mask + AVX512F + Mask + + + + Performs bitwise OR between "k1" and "k2", storing the result in "dst". CF flag is set if "dst" consists of all 1's. + dst[15:0] := k1[15:0] | k2[15:0] +IF PopCount(dst[15:0]) == 16 + SetCF() +FI + + +

immintrin.h

+ + + AVX512F + Mask + + + Converts bit mask "k1" into an integer value, storing the results in "dst". + +dst := ZeroExtend32(k1) + + +

immintrin.h

+ + + AVX512F + Mask + + + Converts integer "mask" into bitmask, storing the result in "dst". + +dst := mask[15:0] + + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + Multiplies elements in packed 64-bit integer vectors "a" and "b" together, storing the lower 64 bits of the result in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] * b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + AVX512F + Store + + + + + + Multiplies elements in packed 64-bit integer vectors "a" and "b" together, storing the lower 64 bits of the result in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := SIN(a[i+63:i]) + MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 +cos_res[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + + + Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := SIN(a[i+63:i]) + MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i]) + ELSE + dst[i+63:i] := sin_src[i+63:i] + MEM[mem_addr+i+63:mem_addr+i] := cos_src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 +cos_res[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := SIN(a[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 +cos_res[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Trigonometry + + + + + + + Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", store the cosine into memory at "mem_addr". Elements are written to their respective locations using writemask "k" (elements are copied from "sin_src" or "cos_src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := SIN(a[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i]) + ELSE + dst[i+31:i] := sin_src[i+31:i] + MEM[mem_addr+i+31:mem_addr+i] := cos_src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 +cos_res[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Copy the lower single-precision (32-bit) floating-point element of "a" to "dst". + +dst[31:0] := a[31:0] + + +

immintrin.h

+ + + Floating Point + AVX512F + Convert + + + Copy the lower double-precision (64-bit) floating-point element of "a" to "dst". + +dst[63:0] := a[63:0] + + +

immintrin.h

+ + + Integer + AVX512F + Convert + + + Copy the lower 32-bit integer in "a" to "dst". + +dst[31:0] := a[31:0] + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Miscellaneous + + + + + Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 64 bytes (16 elements) in "dst". + +temp[1023:512] := a[511:0] +temp[511:0] := b[511:0] +temp[1023:0] := temp[1023:0] >> (32*imm8[3:0]) +dst[511:0] := temp[511:0] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Miscellaneous + + + + + + + Concatenate "a" and "b" into a 128-byte immediate result, shift the result right by "imm8" 32-bit elements, and store the low 64 bytes (16 elements) in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +temp[1023:512] := a[511:0] +temp[511:0] := b[511:0] +temp[1023:0] := temp[1023:0] >> (32*imm8[3:0]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := temp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Swizzle + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Swizzle + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] OP b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] == b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] <= b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] < b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] != b[i+63:i]) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := (!(a[i+63:i] <= b[i+63:i])) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k". + +FOR j := 0 to 7 + i := j*64 + k[j] := (!(a[i+63:i] < b[i+63:i])) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k". + FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k". + FOR j := 0 to 7 + i := j*64 + k[j] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 1 : 0 +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := ( a[i+63:i] OP b[i+63:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (a[i+63:i] == b[i+63:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (a[i+63:i] <= b[i+63:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (a[i+63:i] < b[i+63:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (a[i+63:i] != b[i+63:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (!(a[i+63:i] <= b[i+63:i])) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (!(a[i+63:i] < b[i+63:i])) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k1[j] + k[j] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:8] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 15 + i := j*32 + k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 15 + i := j*32 + k[j] := (a[i+31:i] OP b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := (a[i+31:i] == b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := (a[i+31:i] <= b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := (a[i+31:i] < b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := (a[i+31:i] != b[i+31:i]) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := (!(a[i+31:i] <= b[i+31:i])) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := (!(a[i+31:i] < b[i+31:i])) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k". + FOR j := 0 to 15 + i := j*32 + k[j] := ((a[i+31:i] != NaN) AND (b[i+31:i] != NaN)) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k". + FOR j := 0 to 15 + i := j*32 + k[j] := ((a[i+31:i] == NaN) OR (b[i+31:i] == NaN)) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). [sae_note] + CASE (imm8[4:0]) OF +0: OP := _CMP_EQ_OQ +1: OP := _CMP_LT_OS +2: OP := _CMP_LE_OS +3: OP := _CMP_UNORD_Q +4: OP := _CMP_NEQ_UQ +5: OP := _CMP_NLT_US +6: OP := _CMP_NLE_US +7: OP := _CMP_ORD_Q +8: OP := _CMP_EQ_UQ +9: OP := _CMP_NGE_US +10: OP := _CMP_NGT_US +11: OP := _CMP_FALSE_OQ +12: OP := _CMP_NEQ_OQ +13: OP := _CMP_GE_OS +14: OP := _CMP_GT_OS +15: OP := _CMP_TRUE_UQ +16: OP := _CMP_EQ_OS +17: OP := _CMP_LT_OQ +18: OP := _CMP_LE_OQ +19: OP := _CMP_UNORD_S +20: OP := _CMP_NEQ_US +21: OP := _CMP_NLT_UQ +22: OP := _CMP_NLE_UQ +23: OP := _CMP_ORD_S +24: OP := _CMP_EQ_US +25: OP := _CMP_NGE_UQ +26: OP := _CMP_NGT_UQ +27: OP := _CMP_FALSE_OS +28: OP := _CMP_NEQ_OS +29: OP := _CMP_GE_OQ +30: OP := _CMP_GT_OQ +31: OP := _CMP_TRUE_US +ESAC +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := (a[i+31:i] == b[i+31:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := (a[i+31:i] <= b[i+31:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := (a[i+31:i] < b[i+31:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := (a[i+31:i] != b[i+31:i]) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := (!(a[i+31:i] <= b[i+31:i])) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := (!(a[i+31:i] < b[i+31:i])) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] != NaN) AND (b[i+31:i] != NaN)) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] == NaN) OR (b[i+31:i] == NaN)) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := c[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + + + Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + [sae_note] + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision (64-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + [sae_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + [sae_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision (32-bit) floating-point number representing the integer exponent, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "floor(log2(x))" for each element. + [sae_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + + + Normalize the mantissas of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := GetNormalizedMantissa(a[i+63:i], sc, interv) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Miscellaneous + + + + + + + + Normalize the mantissas of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). This intrinsic essentially calculates "±(2^k)*|x.significand|", where "k" depends on the interval range defined by "interv" and the sign depends on "sc" and the source sign. + [getmant_note][sae_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := GetNormalizedMantissa(a[i+31:i], sc, interv) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + Load 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from memory into "dst". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + Load packed double-precision (64-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Move + + + + + Move packed double-precision (64-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + Store packed double-precision (64-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + Store 512-bits (composed of 8 packed double-precision (64-bit) floating-point elements) from "a" into memory. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + Load 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from memory into "dst". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + Load packed single-precision (32-bit) floating-point elements from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Move + + + + + Move packed single-precision (32-bit) floating-point elements from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + Store packed single-precision (32-bit) floating-point elements from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + Store 512-bits (composed of 16 packed single-precision (32-bit) floating-point elements) from "a" into memory. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + Load 512-bits (composed of 16 packed 32-bit integers) from memory into "dst". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + Load 512-bits of integer data from memory into "dst". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + Load packed 32-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MEM[mem_addr+i+31:mem_addr+i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Move + + + + + Move packed 32-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + Store packed 32-bit integers from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + MEM[mem_addr+i+31:mem_addr+i] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + Store 512-bits (composed of 16 packed 32-bit integers) from "a" into memory. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + Store 512-bits of integer data from "a" into memory. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + Load 512-bits (composed of 8 packed 64-bit integers) from memory into "dst". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +dst[511:0] := MEM[mem_addr+511:mem_addr] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + Load packed 64-bit integers from memory into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := MEM[mem_addr+i+63:mem_addr+i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Move + + + + + Move packed 64-bit integers from "a" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + Store packed 64-bit integers from "a" into memory using writemask "k". + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + MEM[mem_addr+i+63:mem_addr+i] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + Store 512-bits (composed of 8 packed 64-bit integers) from "a" into memory. + "mem_addr" must be aligned on a 64-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+511:mem_addr] := a[511:0] + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). RM. + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] * b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] * b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). RM. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] * b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] * b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] + b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] AND b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise AND of 512 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[511:0] := (a[511:0] AND b[511:0]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (NOT a[i+31:i]) AND b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise NOT of 512 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst". + +dst[511:0] := ((NOT a[511:0]) AND b[511:0]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise NOT of packed 32-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise NOT of 512 bits (composed of packed 64-bit integers) in "a" and then AND with "b", and store the results in "dst". + +dst[511:0] := ((NOT a[511:0]) AND b[511:0]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise NOT of packed 64-bit integers in "a" and then AND with "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise AND of 512 bits (composed of packed 64-bit integers) in "a" and "b", and store the results in "dst". + +dst[511:0] := (a[511:0] AND b[511:0]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise AND of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] AND b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Swizzle + + + + + Blend packed 32-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Swizzle + + + + + Blend packed 64-bit integers from "a" and "b" using control mask "k", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + + Compare packed signed 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k". + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + + Compare packed unsigned 32-bit integers in "a" and "b" based on the comparison operand specified by "imm8", and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + CASE (imm8[2:0]) OF +0: OP := _MM_CMPINT_EQ +1: OP := _MM_CMPINT_LT +2: OP := _MM_CMPINT_LE +3: OP := _MM_CMPINT_FALSE +4: OP := _MM_CMPINT_NE +5: OP := _MM_CMPINT_NLT +6: OP := _MM_CMPINT_NLE +7: OP := _MM_CMPINT_TRUE +ESAC +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] OP b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for equality, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] == b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] >= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for greater-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] > b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] <= b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Compare + + + + + Compare packed unsigned 32-bit integers in "a" and "b" for not-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] != b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Swizzle + + + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the "permutevar" name. This intrinsic is identical to "_mm512_mask_permutexvar_epi32", and it is recommended that you use that intrinsic name. + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + IF k[j] + dst[i+31:i] := a[id+31:id] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Swizzle + + + + Shuffle 32-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". Note that this intrinsic shuffles across 128-bit lanes, unlike past intrinsics that use the "permutevar" name. This intrinsic is identical to "_mm512_permutexvar_epi32", and it is recommended that you use that intrinsic name. + +FOR j := 0 to 15 + i := j*32 + id := idx[i+3:i]*32 + dst[i+31:i] := a[id+31:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst". "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + + + Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst". + +FOR j := 0 to 15 + i := j*32 + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] OR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise OR of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] OR b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise OR of 512 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[511:0] := (a[511:0] OR b[511:0]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] OR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise OR of packed 64-bit integers in "a" and "b", and store the resut in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] OR b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + + Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + + + Scatter 32-bit integers from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Swizzle + + + + + + Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +tmp_dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +tmp_dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +tmp_dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +tmp_dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +tmp_dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +tmp_dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +tmp_dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +tmp_dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +tmp_dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +tmp_dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +tmp_dst[351:320] := SELECT4(a[383:256], imm8[5:4]) +tmp_dst[383:352] := SELECT4(a[383:256], imm8[7:6]) +tmp_dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +tmp_dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +tmp_dst[479:448] := SELECT4(a[511:384], imm8[5:4]) +tmp_dst[511:480] := SELECT4(a[511:384], imm8[7:6]) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := tmp_dst[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Swizzle + + + + Shuffle 32-bit integers in "a" within 128-bit lanes using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +dst[127:96] := SELECT4(a[127:0], imm8[7:6]) +dst[159:128] := SELECT4(a[255:128], imm8[1:0]) +dst[191:160] := SELECT4(a[255:128], imm8[3:2]) +dst[223:192] := SELECT4(a[255:128], imm8[5:4]) +dst[255:224] := SELECT4(a[255:128], imm8[7:6]) +dst[287:256] := SELECT4(a[383:256], imm8[1:0]) +dst[319:288] := SELECT4(a[383:256], imm8[3:2]) +dst[351:320] := SELECT4(a[383:256], imm8[5:4]) +dst[383:352] := SELECT4(a[383:256], imm8[7:6]) +dst[415:384] := SELECT4(a[511:384], imm8[1:0]) +dst[447:416] := SELECT4(a[511:384], imm8[3:2]) +dst[479:448] := SELECT4(a[511:384], imm8[5:4]) +dst[511:480] := SELECT4(a[511:384], imm8[7:6]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + Shift packed 32-bit integers in "a" left by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Shift + + + + Shift packed 32-bit integers in "a" right by the amount specified by the corresponding element in "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + IF count[i+31:i] < 32 + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Logical + + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" (subject to writemask "k") if the intermediate value is non-zero. + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512F/KNCNI + Logical + + + + Compute the bitwise AND of packed 32-bit integers in "a" and "b", producing intermediate 32-bit values, and set the corresponding bit in result mask "k" if the intermediate value is non-zero. + +FOR j := 0 to 15 + i := j*32 + k[j] := ((a[i+31:i] AND b[i+31:i]) != 0) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise XOR of packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise XOR of 512 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[511:0] := (a[511:0] XOR b[511:0]) +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Compute the bitwise XOR of packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + + Scatter single-precision (32-bit) floating-point elements from "a" into memory using 32-bit indices. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not stored when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Cast + + + Cast vector of type __m512d to type __m512. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + AVX512F/KNCNI + Cast + + + Cast vector of type __m512d to type __m512i. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Cast + + + Cast vector of type __m512 to type __m512d. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + AVX512F/KNCNI + Cast + + + Cast vector of type __m512 to type __m512i. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Cast + + + Cast vector of type __m512i to type __m512d. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Cast + + + Cast vector of type __m512i to type __m512. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed 32-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a". + +dst[31:0] := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := dst[31:0] + a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed 64-bit integers in "a" by addition using mask "k". Returns the sum of all active elements in "a". + +dst[63:0] := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := dst[63:0] + a[i+63:i] + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by addition using mask "k". Returns the sum of all active elements in "a". + +dst[63:0] := 0.0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := dst[63:0] + a[i+63:i] + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by addition using mask "k". Returns the sum of all active elements in "a". + +dst[31:0] := 0.0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := dst[31:0] + a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Reduce the packed 32-bit integers in "a" by bitwise AND using mask "k". Returns the bitwise AND of all active elements in "a". + +dst[31:0] := 0xFFFFFFFF +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := dst[31:0] AND a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Reduce the packed 64-bit integers in "a" by bitwise AND using mask "k". Returns the bitwise AND of all active elements in "a". + +dst[63:0] := 0xFFFFFFFFFFFFFFFF +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := dst[63:0] AND a[i+63:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed signed 32-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a". + +dst[31:0] := Int32(-0x80000000) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := (dst[31:0] > a[i+31:i] ? dst[31:0] : a[i+31:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed signed 64-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a". + +dst[63:0] := Int64(-0x8000000000000000) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := (dst[63:0] > a[i+63:i] ? dst[63:0] : a[i+63:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed unsigned 32-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a". + +dst[31:0] := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := (dst[31:0] > a[i+31:i] ? dst[31:0] : a[i+31:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed unsigned 64-bit integers in "a" by maximum using mask "k". Returns the maximum of all active elements in "a". + +dst[63:0] := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := (dst[63:0] > a[i+63:i] ? dst[63:0] : a[i+63:i]) + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum using mask "k". Returns the maximum of all active elements in "a". + +dst[63:0] := Cast_FP64(0xFFEFFFFFFFFFFFFF) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := (dst[63:0] > a[i+63:i] ? dst[63:0] : a[i+63:i]) + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum using mask "k". Returns the maximum of all active elements in "a". + +dst[31:0] := Cast_FP32(0xFF7FFFFF) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := (dst[31:0] > a[i+31:i] ? dst[31:0] : a[i+31:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed signed 32-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". + +dst[31:0] := Int32(0x7FFFFFFF) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := (dst[31:0] < a[i+31:i] ? dst[31:0] : a[i+31:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed signed 64-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". + +dst[63:0] := Int64(0x7FFFFFFFFFFFFFFF) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := (dst[63:0] < a[i+63:i] ? dst[63:0] : a[i+63:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed unsigned 32-bit integers in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". + +dst[31:0] := 0xFFFFFFFF +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := (dst[31:0] < a[i+31:i] ? dst[31:0] : a[i+31:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed unsigned 64-bit integers in "a" by minimum using mask "k". Returns the minimum of all active elements in "a". + +dst[63:0] := 0xFFFFFFFFFFFFFFFF +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := (dst[63:0] < a[i+63:i] ? dst[63:0] : a[i+63:i]) + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". + +dst[63:0] := Cast_FP64(0x7FEFFFFFFFFFFFFF) +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := (dst[63:0] < a[i+63:i] ? dst[63:0] : a[i+63:i]) + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum using mask "k". Returns the minimum of all active elements in "a". + +dst[31:0] := Cast_FP32(0x7F7FFFFF) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := (dst[31:0] < a[i+31:i] ? dst[31:0] : a[i+31:i]) + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed 32-bit integers in "a" by multiplication using mask "k". Returns the product of all active elements in "a". + +dst[31:0] := 1 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := dst[31:0] * a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed 64-bit integers in "a" by multiplication using mask "k". Returns the product of all active elements in "a". + +dst[63:0] := 1 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := dst[63:0] * a[i+63:i] + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by multiplication using mask "k". Returns the product of all active elements in "a". + +dst[63:0] := 1.0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := dst[63:0] * a[i+63:i] + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by multiplication using mask "k". Returns the product of all active elements in "a". + +dst[31:0] := FP32(1.0) +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := dst[31:0] * a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Reduce the packed 32-bit integers in "a" by bitwise OR using mask "k". Returns the bitwise OR of all active elements in "a". + +dst[31:0] := 0 +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[31:0] := dst[31:0] OR a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + Reduce the packed 64-bit integers in "a" by bitwise OR using mask "k". Returns the bitwise OR of all active elements in "a". + +dst[63:0] := 0 +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[63:0] := dst[63:0] OR a[i+63:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + Reduce the packed 32-bit integers in "a" by addition. Returns the sum of all elements in "a". + +dst[31:0] := 0 +FOR j := 0 to 15 + i := j*32 + dst[31:0] := dst[31:0] + a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + Reduce the packed 64-bit integers in "a" by addition. Returns the sum of all elements in "a". + +dst[63:0] := 0 +FOR j := 0 to 7 + i := j*64 + dst[63:0] := dst[63:0] + a[i+63:i] +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a". + +dst[63:0] := 0.0 +FOR j := 0 to 7 + i := j*64 + dst[63:0] := dst[63:0] + a[i+63:i] +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by addition. Returns the sum of all elements in "a". + +dst[31:0] := 0.0 +FOR j := 0 to 15 + i := j*32 + dst[31:0] := dst[31:0] + a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + Reduce the packed 32-bit integers in "a" by bitwise AND. Returns the bitwise AND of all elements in "a". + +dst[31:0] := 0xFFFFFFFF +FOR j := 0 to 15 + i := j*32 + dst[31:0] := dst[31:0] AND a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + Reduce the packed 64-bit integers in "a" by bitwise AND. Returns the bitwise AND of all elements in "a". + +dst[63:0] := 0xFFFFFFFFFFFFFFFF +FOR j := 0 to 7 + i := j*64 + dst[63:0] := dst[63:0] AND a[i+63:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed signed 32-bit integers in "a" by maximum. Returns the maximum of all elements in "a". + +dst[31:0] := Int32(-0x80000000) +FOR j := 0 to 15 + i := j*32 + dst[31:0] := (dst[31:0] > a[i+31:i] ? dst[31:0] : a[i+31:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed signed 64-bit integers in "a" by maximum. Returns the maximum of all elements in "a". + +dst[63:0] := Int64(-0x8000000000000000) +FOR j := 0 to 7 + i := j*64 + dst[63:0] := (dst[63:0] > a[i+63:i] ? dst[63:0] : a[i+63:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed unsigned 32-bit integers in "a" by maximum. Returns the maximum of all elements in "a". + +dst[31:0] := 0 +FOR j := 0 to 15 + i := j*32 + dst[31:0] := (dst[31:0] > a[i+31:i] ? dst[31:0] : a[i+31:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed unsigned 64-bit integers in "a" by maximum. Returns the maximum of all elements in "a". + +dst[63:0] := 0 +FOR j := 0 to 7 + i := j*64 + dst[63:0] := (dst[63:0] > a[i+63:i] ? dst[63:0] : a[i+63:i]) +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a". + +dst[63:0] := Cast_FP64(0xFFEFFFFFFFFFFFFF) +FOR j := 0 to 7 + i := j*64 + dst[63:0] := (dst[63:0] > a[i+63:i] ? dst[63:0] : a[i+63:i]) +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by maximum. Returns the maximum of all elements in "a". + +dst[31:0] := Cast_FP32(0xFF7FFFFF) +FOR j := 0 to 15 + i := j*32 + dst[31:0] := (dst[31:0] > a[i+31:i] ? dst[31:0] : a[i+31:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed signed 32-bit integers in "a" by minimum. Returns the minimum of all elements in "a". + +dst[31:0] := Int32(0x7FFFFFFF) +FOR j := 0 to 15 + i := j*32 + dst[31:0] := (dst[31:0] < a[i+31:i] ? dst[31:0] : a[i+31:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed signed 64-bit integers in "a" by minimum. Returns the minimum of all elements in "a". + +dst[63:0] := Int64(0x7FFFFFFFFFFFFFFF) +FOR j := 0 to 7 + i := j*64 + dst[63:0] := (dst[63:0] < a[i+63:i] ? dst[63:0] : a[i+63:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed unsigned 32-bit integers in "a" by minimum. Returns the minimum of all elements in "a". + +dst[31:0] := 0xFFFFFFFF +FOR j := 0 to 15 + i := j*32 + dst[31:0] := (dst[31:0] < a[i+31:i] ? dst[31:0] : a[i+31:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed unsigned 64-bit integers in "a" by minimum. Returns the minimum of all elements in "a". + +dst[63:0] := 0xFFFFFFFFFFFFFFFF +FOR j := 0 to 7 + i := j*64 + dst[63:0] := (dst[63:0] < a[i+63:i] ? dst[63:0] : a[i+63:i]) +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". + +dst[63:0] := Cast_FP64(0x7FEFFFFFFFFFFFFF) +FOR j := 0 to 7 + i := j*64 + dst[63:0] := (dst[63:0] < a[i+63:i] ? dst[63:0] : a[i+63:i]) +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Special Math Functions + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by minimum. Returns the minimum of all elements in "a". + +dst[31:0] := Cast_FP32(0x7F7FFFFF) +FOR j := 0 to 15 + i := j*32 + dst[31:0] := (dst[31:0] < a[i+31:i] ? dst[31:0] : a[i+31:i]) +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + Reduce the packed 32-bit integers in "a" by multiplication. Returns the product of all elements in "a". + +dst[31:0] := 1 +FOR j := 0 to 15 + i := j*32 + dst[31:0] := dst[31:0] * a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Arithmetic + + + Reduce the packed 64-bit integers in "a" by multiplication. Returns the product of all elements in "a". + +dst[63:0] := 1 +FOR j := 0 to 7 + i := j*64 + dst[63:0] := dst[63:0] * a[i+63:i] +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + Reduce the packed double-precision (64-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a". + +dst[63:0] := 1.0 +FOR j := 0 to 7 + i := j*64 + dst[63:0] := dst[63:0] * a[i+63:i] +ENDFOR + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + Reduce the packed single-precision (32-bit) floating-point elements in "a" by multiplication. Returns the product of all elements in "a". + +dst[31:0] := FP32(1.0) +FOR j := 0 to 15 + i := j*32 + dst[31:0] := dst[31:0] * a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + Reduce the packed 32-bit integers in "a" by bitwise OR. Returns the bitwise OR of all elements in "a". + +dst[31:0] := 0 +FOR j := 0 to 15 + i := j*32 + dst[31:0] := dst[31:0] OR a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + Reduce the packed 64-bit integers in "a" by bitwise OR. Returns the bitwise OR of all elements in "a". + +dst[63:0] := 0 +FOR j := 0 to 7 + i := j*64 + dst[63:0] := dst[63:0] OR a[i+63:i] +ENDFOR + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Logical + + + + + + Performs element-by-element bitwise AND between packed 32-bit integer elements of "v2" and "v3", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v2[i+31:i] & v3[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Convert + + + Performs element-by-element conversion of the lower half of packed single-precision (32-bit) floating-point elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst". + +FOR j := 0 to 7 + i := j*32 + n := j*64 + dst[n+63:n] := Convert_FP32_To_FP64(v2[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Convert + + + + + Performs element-by-element conversion of the lower half of packed single-precision (32-bit) floating-point elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[l+63:l] := Convert_FP32_To_FP64(v2[i+31:i]) + ELSE + dst[l+63:l] := src[l+63:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F/KNCNI + Convert + + + Performs element-by-element conversion of the lower half of packed 32-bit integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst". + +FOR j := 0 to 7 + i := j*32 + l := j*64 + dst[l+63:l] := Convert_Int32_To_FP64(v2[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F/KNCNI + Convert + + + + + Performs element-by-element conversion of the lower half of packed 32-bit integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + n := j*64 + IF k[j] + dst[n+63:n] := Convert_Int32_To_FP64(v2[i+31:i]) + ELSE + dst[n+63:n] := src[n+63:n] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F/KNCNI + Convert + + + Performs element-by-element conversion of the lower half of packed 32-bit unsigned integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst". + +FOR j := 0 to 7 + i := j*32 + n := j*64 + dst[n+63:n] := Convert_Int32_To_FP64(v2[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + AVX512F/KNCNI + Convert + + + + + Performs element-by-element conversion of the lower half of 32-bit unsigned integer elements in "v2" to packed double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + l := j*64 + IF k[j] + dst[l+63:l] := Convert_Int32_To_FP64(v2[i+31:i]) + ELSE + dst[l+63:l] := src[l+63:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + + + Up-converts 16 memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 32-bit integer elements and stores them in "dst". AVX512 only supports _MM_UPCONV_EPI32_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_EPI32_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_EPI32_UINT8: dst[i+31:i] := ZeroExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_SINT8: dst[i+31:i] := SignExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_UINT16: dst[i+31:i] := ZeroExtend32(MEM[addr+15:addr]) + _MM_UPCONV_EPI32_SINT16: dst[i+31:i] := SignExtend32(MEM[addr+15:addr]) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + + + + + Up-converts 16 single-precision (32-bit) memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 32-bit integer elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). AVX512 only supports _MM_UPCONV_EPI32_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_EPI32_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_EPI32_UINT8: dst[i+31:i] := ZeroExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_SINT8: dst[i+31:i] := SignExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_UINT16: dst[i+31:i] := ZeroExtend32(MEM[addr+15:addr]) + _MM_UPCONV_EPI32_SINT16: dst[i+31:i] := SignExtend32(MEM[addr+15:addr]) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + + + Up-converts 8 double-precision (64-bit) memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" using "conv" to 64-bit integer elements and stores them in "dst". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_EPI64_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + + + + + Up-converts 8 double-precision (64-bit) memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" using "conv" to 64-bit integer elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_EPI64_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + + + Up-converts 16 memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv" to single-precision (32-bit) floating-point elements and stores them in "dst". AVX512 only supports _MM_UPCONV_PS_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_PS_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_PS_FLOAT16: dst[i+31:i] := Convert_FP16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_UINT8: dst[i+31:i] := Convert_UInt8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_SINT8: dst[i+31:i] := Convert_Int8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_UINT16: dst[i+31:i] := Convert_UInt16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_SINT16: dst[i+31:i] := Convert_Int16_To_FP32(MEM[addr+15:addr]) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + + + + + Up-converts 16 single-precision (32-bit) memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv" to single-precision (32-bit) floating-point elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). AVX512 only supports _MM_UPCONV_PS_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_PS_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_PS_FLOAT16: dst[i+31:i] := Convert_FP16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_UINT8: dst[i+31:i] := Convert_UInt8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_SINT8: dst[i+31:i] := Convert_Int8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_UINT16: dst[i+31:i] := Convert_UInt16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_SINT16: dst[i+31:i] := Convert_Int16_To_FP32(MEM[addr+15:addr]) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + + + Up-converts 8 double-precision (64-bit) floating-point elements in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" using "conv" to 64-bit floating-point elements and stores them in "dst". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_PD_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + + + + + Up-converts 8 double-precision (64-bit) floating-point elements in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" using "conv" to 64-bit floating-point elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_PD_NONE: + dst[i+63:i] := MEM[addr+63:addr] + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + + + Down-converts 16 packed single-precision (32-bit) floating-point elements in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv". AVX512 only supports _MM_DOWNCONV_PS_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_PS_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_PS_FLOAT16: MEM[addr+15:addr] := Convert_FP32_To_FP16(a[i+31:i]) + _MM_DOWNCONV_PS_UINT8: MEM[addr+ 7:addr] := Convert_FP32_To_UInt8(a[i+31:i]) + _MM_DOWNCONV_PS_SINT8: MEM[addr+ 7:addr] := Convert_FP32_To_Int8(a[i+31:i]) + _MM_DOWNCONV_PS_UINT16: MEM[addr+15:addr] := Convert_FP32_To_UInt16(a[i+31:i]) + _MM_DOWNCONV_PS_SINT16: MEM[addr+15:addr] := Convert_FP32_To_Int16(a[i+31:i]) + ESAC +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + + + + Down-converts 16 packed single-precision (32-bit) floating-point elements in "a" according to "conv" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using writemask "k" (elements are written only when the corresponding mask bit is not set). AVX512 only supports _MM_DOWNCONV_PS_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_PS_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_PS_FLOAT16: MEM[addr+15:addr] := Convert_FP32_To_FP16(a[i+31:i]) + _MM_DOWNCONV_PS_UINT8: MEM[addr+ 7:addr] := Convert_FP32_To_UInt8(a[i+31:i]) + _MM_DOWNCONV_PS_SINT8: MEM[addr+ 7:addr] := Convert_FP32_To_Int8(a[i+31:i]) + _MM_DOWNCONV_PS_UINT16: MEM[addr+15:addr] := Convert_FP32_To_UInt16(a[i+31:i]) + _MM_DOWNCONV_PS_SINT16: MEM[addr+15:addr] := Convert_FP32_To_Int16(a[i+31:i]) + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + + + Down-converts 8 packed double-precision (64-bit) floating-point elements in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_PD_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + + + + Down-converts 8 packed double-precision (64-bit) floating-point elements in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv". Only those elements whose corresponding mask bit is set in writemask "k" are written to memory. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_PD_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + + + + Down-converts 8 packed 64-bit integer elements in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + + + + + Down-converts 8 packed 64-bit integer elements in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using "conv". Only those elements whose corresponding mask bit is set in writemask "k" are written to memory. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Convert + + + Performs an element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to single-precision (32-bit) floating-point elements and stores them in "dst". The elements are stored in the lower half of the results vector, while the remaining upper half locations are set to 0. + +FOR j := 0 to 7 + i := j*64 + k := j*32 + dst[k+31:k] := Convert_FP64_To_FP32(v2[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Convert + + + + + Performs an element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to single-precision (32-bit) floating-point elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The elements are stored in the lower half of the results vector, while the remaining upper half locations are set to 0. + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_FP64_To_FP32(v2[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + Loads 8 64-bit integer elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" and stores them in "dst". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Load + + + + + + + Loads 8 64-bit integer elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + Loads 8 double-precision (64-bit) floating-point elements stored at memory locations starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" them in "dst". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Load + + + + + + + Loads 8 double-precision (64-bit) floating-point elements from memory starting at location "base_addr" at packed 32-bit integer indices stored in the lower half of "vindex" scaled by "scale" into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + dst[i+63:i] := MEM[addr+63:addr] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + Stores 8 packed double-precision (64-bit) floating-point elements in "a" and to memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Store + + + + + + + Stores 8 packed double-precision (64-bit) floating-point elements in "a" to memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". Only those elements whose corresponding mask bit is set in writemask "k" are written to memory. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + Finds the absolute value of each packed single-precision (32-bit) floating-point element in "v2", storing the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ABS(v2[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Finds the absolute value of each packed single-precision (32-bit) floating-point element in "v2", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ABS(v2[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + Finds the absolute value of each packed double-precision (64-bit) floating-point element in "v2", storing the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ABS(v2[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Arithmetic + + + + + Finds the absolute value of each packed double-precision (64-bit) floating-point element in "v2", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ABS(v2[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Elementary Math Functions + + + Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512F/KNCNI + Elementary Math Functions + + + + + Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + + + + Down-converts 16 packed 32-bit integer elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". "hint" indicates to the processor whether the data is non-temporal. AVX512 only supports _MM_DOWNCONV_EPI32_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_EPI32_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_EPI32_UINT8: MEM[addr+ 7:addr] := Truncate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT8: MEM[addr+ 7:addr] := Saturate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_UINT16: MEM[addr+15:addr] := Truncate16(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT16: MEM[addr+15:addr] := Saturate16(a[i+15:i]) + ESAC +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512F/KNCNI + Store + + + + + + + + + Down-converts 16 packed 32-bit integer elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". Elements are written using writemask "k" (elements are only written when the corresponding mask bit is set; otherwise, elements are left unchanged in memory). "hint" indicates to the processor whether the data is non-temporal. AVX512 only supports _MM_DOWNCONV_EPI32_NONE. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI32_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_EPI32_UINT8: MEM[addr+ 7:addr] := Truncate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT8: MEM[addr+ 7:addr] := Saturate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_UINT16: MEM[addr+15:addr] := Truncate16(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT16: MEM[addr+15:addr] := Saturate16(a[i+15:i]) + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + AVX512IFMA52 + Arithmetic + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the low 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[51:0]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + Arithmetic + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*64 + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512IFMA52 + AVX512VL + Arithmetic + + + + + + Multiply packed unsigned 52-bit integers in each 64-bit element of "b" and "c" to form a 104-bit intermediate result. Add the high 52-bit unsigned integer from the intermediate result with the corresponding unsigned 64-bit integer in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ZeroExtend64(b[i+51:i]) * ZeroExtend64(c[i+51:i]) + dst[i+63:i] := a[i+63:i] + ZeroExtend64(tmp[103:52]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512PF + Load + + + + + + Prefetch single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged in cache. "scale" should be 1, 2, 4 or 8. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j:= 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Load + + + + + + + Prefetch single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged in cache using writemask "k" (elements are only brought into cache when their corresponding mask bit is set). "scale" should be 1, 2, 4 or 8.. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j:= 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Store + + + + + + Prefetch single-precision (32-bit) floating-point elements with intent to write into memory using 64-bit indices. Elements are prefetched into cache level "hint", where "hint" is 0 or 1. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Store + + + + + + + Prefetch single-precision (32-bit) floating-point elements with intent to write into memory using 64-bit indices. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. 32-bit elements are stored at addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not brought into cache when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Load + + + + + + Prefetch double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged in cache. "scale" should be 1, 2, 4 or 8. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Load + + + + + + + Prefetch double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged in cache using writemask "k" (elements are brought into cache only when their corresponding mask bits are set). "scale" should be 1, 2, 4 or 8. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Store + + + + + + Prefetch double-precision (64-bit) floating-point elements with intent to write using 32-bit indices. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. 64-bit elements are brought into cache from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Store + + + + + + + Prefetch double-precision (64-bit) floating-point elements with intent to write using 32-bit indices. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. 64-bit elements are brought into cache from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not brought into cache when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Load + + + + + + Prefetch double-precision (64-bit) floating-point elements from memory into cache level specified by "hint" using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Load + + + + + + + Prefetch double-precision (64-bit) floating-point elements from memory into cache level specified by "hint" using 64-bit indices. 64-bit elements are loaded from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). Prefetched elements are merged in cache using writemask "k" (elements are copied from memory when the corresponding mask bit is set). "scale" should be 1, 2, 4 or 8. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Store + + + + + + Prefetch double-precision (64-bit) floating-point elements with intent to write into memory using 64-bit indices. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. 64-bit elements are brought into cache from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale"). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF + Store + + + + + + + Prefetch double-precision (64-bit) floating-point elements with intent to write into memory using 64-bit indices. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. 64-bit elements are brought into cache from addresses starting at "base_addr" and offset by each 64-bit element in "vindex" (each index is scaled by the factor in "scale") subject to mask "k" (elements are not brought into cache when the corresponding mask bit is not set). "scale" should be 1, 2, 4 or 8. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+63:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Load + + + + + + + Prefetch single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at "base_addr" and offset by each 32-bit element in "vindex" (each index is scaled by the factor in "scale"). Gathered elements are merged in cache using writemask "k" (elements are brought into cache only when their corresponding mask bits are set). "scale" should be 1, 2, 4 or 8. The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Load + + + + + + + Prefetches a set of 16 single-precision (32-bit) memory locations pointed by base address "base_addr" and 32-bit integer index vector "vindex" with scale "scale" to L1 or L2 level of cache depending on the value of "hint". The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. +The "conv" parameter specifies the granularity used by compilers to better encode the instruction. It should be the same as the "conv" parameter specified for the subsequent gather intrinsic. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Load + + + + + + + + Prefetches a set of 16 single-precision (32-bit) memory locations pointed by base address "base_addr" and 32-bit integer index vector "vindex" with scale "scale" to L1 or L2 level of cache depending on the value of "hint". Gathered elements are merged in cache using writemask "k" (elements are brought into cache only when their corresponding mask bits are set). The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. +The "conv" parameter specifies the granularity used by compilers to better encode the instruction. It should be the same as the "conv" parameter specified for the subsequent gather intrinsic. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Store + + + + + + + Prefetches a set of 16 single-precision (32-bit) memory locations pointed by base address "base_addr" and 32-bit integer index vector "vindex" with scale "scale" to L1 or L2 level of cache depending on the value of "hint", with a request for exclusive ownership. The "hint" parameter may be one of the following: _MM_HINT_T0 = 1 for prefetching to L1 cache, _MM_HINT_T1 = 2 for prefetching to L2 cache, _MM_HINT_T2 = 3 for prefetching to L2 cache non-temporal, _MM_HINT_NTA = 0 for prefetching to L1 cache non-temporal. The "conv" parameter specifies the granularity used by compilers to better encode the instruction. It should be the same as the "conv" parameter specified for the subsequent scatter intrinsic. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Store + + + + + + + + Prefetches a set of 16 single-precision (32-bit) memory locations pointed by base address "base_addr" and 32-bit integer index vector "vindex" with scale "scale" to L1 or L2 level of cache depending on the value of "hint". The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. +The "conv" parameter specifies the granularity used by compilers to better encode the instruction. It should be the same as the "conv" parameter specified for the subsequent gather intrinsic. Only those elements whose corresponding mask bit in "k" is set are loaded into cache. + +cachev := 0 +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Load + + + + + + Prefetches 16 single-precision (32-bit) floating-point elements in memory starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Store + + + + + + Prefetches 16 single-precision (32-bit) floating-point elements in memory starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) +ENDFOR + + + +

immintrin.h

+ + + Floating Point + AVX512PF/KNCNI + Store + + + + + + + Prefetches 16 single-precision (32-bit) floating-point elements in memory starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". The "hint" parameter may be 1 (_MM_HINT_T0) for prefetching to L1 cache, or 2 (_MM_HINT_T1) for prefetching to L2 cache. Only those elements whose corresponding mask bit in "k" is set are loaded into the desired cache. + +FOR j := 0 to 15 + i := j*32 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + Prefetch(MEM[addr+31:addr], hint) + FI +ENDFOR + + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := POPCNT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := POPCNT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := POPCNT(a[i+63:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := POPCNT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := POPCNT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := POPCNT(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := POPCNT(a[i+31:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := POPCNT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := POPCNT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := POPCNT(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := POPCNT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := POPCNT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + Bit Manipulation + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := POPCNT(a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POPCNT(a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + Bit Manipulation + + + + Count the number of logical 1 bits in packed 32-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := POPCNT(a[i+31:i]) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + Bit Manipulation + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := POPCNT(a[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POPCNT(a[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VPOPCNTDQ + Bit Manipulation + + + + Count the number of logical 1 bits in packed 64-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := POPCNT(a[i+63:i]) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + Multiply packed single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by the 4 corresponding packed elements in "b", accumulate with the corresponding elements in "src", and store the results in "dst". + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[i] := dst.fp32[i] + a{m}.fp32[i] * Cast_FP32(MEM[addr+31:addr]) + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply packed single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by the 4 corresponding packed elements in "b", accumulate with the corresponding elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + addr := b + m * 32 + IF k[i] + dst.fp32[i] := dst.fp32[i] + a{m}.fp32[i] * Cast_FP32(MEM[addr+31:addr]) + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply packed single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by the 4 corresponding packed elements in "b", accumulate with the corresponding elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + addr := b + m * 32 + IF k[i] + dst.fp32[i] := dst.fp32[i] + a{m}.fp32[i] * Cast_FP32(MEM[addr+31:addr]) + ELSE + dst.fp32[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + Multiply packed single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by the 4 corresponding packed elements in "b", accumulate the negated intermediate result with the corresponding elements in "src", and store the results in "dst". + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[i] := dst.fp32[i] - a{m}.fp32[i] * Cast_FP32(MEM[addr+31:addr]) + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply packed single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by the 4 corresponding packed elements in "b", accumulate the negated intermediate result with the corresponding elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + addr := b + m * 32 + IF k[i] + dst.fp32[i] := dst.fp32[i] - a{m}.fp32[i] * Cast_FP32(MEM[addr+31:addr]) + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply packed single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by the 4 corresponding packed elements in "b", accumulate the negated intermediate result with the corresponding elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + addr := b + m * 32 + IF k[i] + dst.fp32[i] := dst.fp32[i] - a{m}.fp32[i] * Cast_FP32(MEM[addr+31:addr]) + ELSE + dst.fp32[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by corresponding element in "b", accumulate with the lower element in "a", and store the result in the lower element of "dst". + +dst[127:0] := src[127:0] +FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[0] := dst.fp32[0] + a{m}.fp32[0] * Cast_FP32(MEM[addr+31:addr]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by corresponding element in "b", accumulate with the lower element in "a", and store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set). + +dst[127:0] := src[127:0] +IF k[0] + FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[0] := dst.fp32[0] + a{m}.fp32[0] * Cast_FP32(MEM[addr+31:addr]) + ENDFOR +FI +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by corresponding element in "b", accumulate with the lower element in "a", and store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set). + +dst[127:0] := src[127:0] +IF k[0] + FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[0] := dst.fp32[0] + a{m}.fp32[0] * Cast_FP32(MEM[addr+31:addr]) + ENDFOR +ELSE + dst.fp32[0] := 0 +FI +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by corresponding element in "b", accumulate the negated intermediate result with the lower element in "src", and store the result in the lower element of "dst". + +dst[127:0] := src[127:0] +FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[0] := dst.fp32[0] - a{m}.fp32[0] * Cast_FP32(MEM[addr+31:addr]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by corresponding element in "b", accumulate the negated intermediate result with the lower element in "src", and store the result in the lower element of "dst" using writemask "k" (the element is copied from "a" when mask bit 0 is not set). + +dst[127:0] := src[127:0] +IF k[0] + FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[0] := dst.fp32[0] - a{m}.fp32[0] * Cast_FP32(MEM[addr+31:addr]) + ENDFOR +FI +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_4FMAPS + Arithmetic + + + + + + + + + Multiply the lower single-precision (32-bit) floating-point elements specified in 4 consecutive operands "a0" through "a3" by corresponding element in "b", accumulate the negated intermediate result with the lower element in "src", and store the result in the lower element of "dst" using zeromask "k" (the element is zeroed out when mask bit 0 is not set). + +dst[127:0] := src[127:0] +IF k[0] + FOR m := 0 to 3 + addr := b + m * 32 + dst.fp32[0] := dst.fp32[0] - a{m}.fp32[0] * Cast_FP32(MEM[addr+31:addr]) + ENDFOR +ELSE + dst.fp32[0] := 0 +FI +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_4VNNIW + Arithmetic + + + + + + + + Compute 4 sequential operand source-block dot-products of two signed 16-bit element operands with 32-bit element accumulation, and store the results in "dst". + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + lim_base := b + m*32 + t.dword := MEM[lim_base+31:lim_base] + p1.dword := SignExtend32(a{m}.word[2*i+0]) * SignExtend32(Cast_Int16(t.word[0])) + p2.dword := SignExtend32(a{m}.word[2*i+1]) * SignExtend32(Cast_Int16(t.word[1])) + dst.dword[i] := dst.dword[i] + p1.dword + p2.dword + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_4VNNIW + Arithmetic + + + + + + + + + Compute 4 sequential operand source-block dot-products of two signed 16-bit element operands with 32-bit element accumulation with mask, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + IF k[i] + FOR m := 0 to 3 + lim_base := b + m*32 + t.dword := MEM[lim_base+31:lim_base] + p1.dword := SignExtend32(a{m}.word[2*i+0]) * SignExtend32(Cast_Int16(t.word[0])) + p2.dword := SignExtend32(a{m}.word[2*i+1]) * SignExtend32(Cast_Int16(t.word[1])) + dst.dword[i] := dst.dword[i] + p1.dword + p2.dword + ENDFOR + ELSE + dst.dword[i] := src.dword[i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_4VNNIW + Arithmetic + + + + + + + + + Compute 4 sequential operand source-block dot-products of two signed 16-bit element operands with 32-bit element accumulation with mask, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + IF k[i] + FOR m := 0 to 3 + lim_base := b + m*32 + t.dword := MEM[lim_base+31:lim_base] + p1.dword := SignExtend32(a{m}.word[2*i+0]) * SignExtend32(Cast_Int16(t.word[0])) + p2.dword := SignExtend32(a{m}.word[2*i+1]) * SignExtend32(Cast_Int16(t.word[1])) + dst.dword[i] := dst.dword[i] + p1.dword + p2.dword + ENDFOR + ELSE + dst.dword[i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_4VNNIW + Arithmetic + + + + + + + + Compute 4 sequential operand source-block dot-products of two signed 16-bit element operands with 32-bit element accumulation and signed saturation, and store the results in "dst". + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + FOR m := 0 to 3 + lim_base := b + m*32 + t.dword := MEM[lim_base+31:lim_base] + p1.dword := SignExtend32(a{m}.word[2*i+0]) * SignExtend32(Cast_Int16(t.word[0])) + p2.dword := SignExtend32(a{m}.word[2*i+1]) * SignExtend32(Cast_Int16(t.word[1])) + dst.dword[i] := Saturate32(dst.dword[i] + p1.dword + p2.dword) + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_4VNNIW + Arithmetic + + + + + + + + + Compute 4 sequential operand source-block dot-products of two signed 16-bit element operands with 32-bit element accumulation with mask and signed saturation, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set).. + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + IF k[i] + FOR m := 0 to 3 + lim_base := b + m*32 + t.dword := MEM[lim_base+31:lim_base] + p1.dword := SignExtend32(a{m}.word[2*i+0]) * SignExtend32(Cast_Int16(t.word[0])) + p2.dword := SignExtend32(a{m}.word[2*i+1]) * SignExtend32(Cast_Int16(t.word[1])) + dst.dword[i] := Saturate32(dst.dword[i] + p1.dword + p2.dword) + ENDFOR + ELSE + dst.dword[i] := src.dword[i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_4VNNIW + Arithmetic + + + + + + + + + Compute 4 sequential operand source-block dot-products of two signed 16-bit element operands with 32-bit element accumulation with mask and signed saturation, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set).. + +dst[511:0] := src[511:0] +FOR i := 0 to 15 + IF k[i] + FOR m := 0 to 3 + lim_base := b + m*32 + t.dword := MEM[lim_base+31:lim_base] + p1.dword := SignExtend32(a{m}.word[2*i+0]) * SignExtend32(Cast_Int16(t.word[0])) + p2.dword := SignExtend32(a{m}.word[2*i+1]) * SignExtend32(Cast_Int16(t.word[1])) + dst.dword[i] := Saturate32(dst.dword[i] + p1.dword + p2.dword) + ENDFOR + ELSE + dst.dword[i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst". + +FOR j := 0 to 7 + IF j < 4 + t := b.fp32[j] + ELSE + t := a.fp32[j-4] + FI + dst.word[j] := Convert_FP32_To_BF16(t) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + IF j < 4 + t := b.fp32[j] + ELSE + t := a.fp32[j-4] + FI + dst.word[j] := Convert_FP32_To_BF16(t) + ELSE + dst.word[j] := src.word[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + IF j < 4 + t := b.fp32[j] + ELSE + t := a.fp32[j-4] + FI + dst.word[j] := Convert_FP32_To_BF16(t) + ELSE + dst.word[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst". + +FOR j := 0 to 15 + IF j < 8 + t := b.fp32[j] + ELSE + t := a.fp32[j-8] + FI + dst.word[j] := Convert_FP32_To_BF16(t) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + IF j < 8 + t := b.fp32[j] + ELSE + t := a.fp32[j-8] + FI + dst.word[j] := Convert_FP32_To_BF16(t) + ELSE + dst.word[j] := src.word[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + IF j < 8 + t := b.fp32[j] + ELSE + t := a.fp32[j-8] + FI + dst.word[j] := Convert_FP32_To_BF16(t) + ELSE + dst.word[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst". + +FOR j := 0 to 31 + IF j < 16 + t := b.fp32[j] + ELSE + t := a.fp32[j-16] + FI + dst.word[j] := Convert_FP32_To_BF16(t) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Convert + + + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + IF k[j] + IF j < 16 + t := b.fp32[j] + ELSE + t := a.fp32[j-16] + FI + dst.word[j] := Convert_FP32_To_BF16(t) + ELSE + dst.word[j] := src.word[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in two vectors "a" and "b" to packed BF16 (16-bit) floating-point elements, and store the results in single vector "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + IF k[j] + IF j < 16 + t := b.fp32[j] + ELSE + t := a.fp32[j-16] + FI + dst.word[j] := Convert_FP32_To_BF16(t) + ELSE + dst.word[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) + ELSE + dst.word[j] := src.word[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) + ELSE + dst.word[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) + ELSE + dst.word[j] := src.word[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) + ELSE + dst.word[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 15 + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Convert + + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) + ELSE + dst.word[j] := src.word[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed BF16 (16-bit) floating-point elements, and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + dst.word[j] := Convert_FP32_To_BF16(a.fp32[j]) + ELSE + dst.word[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Arithmetic + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst". + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 3 + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Arithmetic + + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 3 + IF k[j] + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Arithmetic + + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 3 + IF k[j] + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Arithmetic + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst". + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 7 + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Arithmetic + + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 7 + IF k[j] + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512VL + Arithmetic + + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 7 + IF k[j] + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Arithmetic + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst". + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 15 + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Arithmetic + + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 15 + IF k[j] + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + AVX512_BF16 + AVX512F + Arithmetic + + + + + + Compute dot-product of BF16 (16-bit) floating-point pairs in "a" and "b", accumulating the intermediate single-precision (32-bit) floating-point elements with elements in "src", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE make_fp32(x[15:0]) { + y.fp32 := 0.0 + y[31:16] := x[15:0] + RETURN y +} +dst := src +FOR j := 0 to 15 + IF k[j] + dst.fp32[j] += make_fp32(a.bf16[2*j+1]) * make_fp32(b.bf16[2*j+1]) + dst.fp32[j] += make_fp32(a.bf16[2*j+0]) * make_fp32(b.bf16[2*j+0]) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512_BITALG + Bit Manipulation + + + + + Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR i := 0 to 7 //Qword + FOR j := 0 to 7 // Byte + IF k[i*8+j] + m := c.qword[i].byte[j] & 0x3F + dst[i*8+j] := b.qword[i].bit[m] + ELSE + dst[i*8+j] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512_BITALG + Bit Manipulation + + + + Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst". + +FOR i := 0 to 7 //Qword + FOR j := 0 to 7 // Byte + m := c.qword[i].byte[j] & 0x3F + dst[i*8+j] := b.qword[i].bit[m] + ENDFOR +ENDFOR +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + + Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR i := 0 to 3 //Qword + FOR j := 0 to 7 // Byte + IF k[i*8+j] + m := c.qword[i].byte[j] & 0x3F + dst[i*8+j] := b.qword[i].bit[m] + ELSE + dst[i*8+j] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst". + +FOR i := 0 to 3 //Qword + FOR j := 0 to 7 // Byte + m := c.qword[i].byte[j] & 0x3F + dst[i*8+j] := b.qword[i].bit[m] + ENDFOR +ENDFOR +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + + Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR i := 0 to 1 //Qword + FOR j := 0 to 7 // Byte + IF k[i*8+j] + m := c.qword[i].byte[j] & 0x3F + dst[i*8+j] := b.qword[i].bit[m] + ELSE + dst[i*8+j] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + Gather 64 bits from "b" using selection bits in "c". For each 64-bit element in "b", gather 8 bits from the 64-bit element in "b" at 8 bit position controlled by the 8 corresponding 8-bit elements of "c", and store the result in the corresponding 8-bit element of "dst". + +FOR i := 0 to 1 //Qword + FOR j := 0 to 7 // Byte + m := c.qword[i].byte[j] & 0x3F + dst[i*8+j] := b.qword[i].bit[m] + ENDFOR +ENDFOR +dst[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + Bit Manipulation + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := POPCNT(a[i+15:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := POPCNT(a[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + Bit Manipulation + + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := POPCNT(a[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := POPCNT(a[i+15:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := POPCNT(a[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := POPCNT(a[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := POPCNT(a[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := POPCNT(a[i+15:i]) + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 16-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := POPCNT(a[i+15:i]) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + Bit Manipulation + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 63 + i := j*8 + dst[i+7:i] := POPCNT(a[i+7:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := POPCNT(a[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + Bit Manipulation + + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := POPCNT(a[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 31 + i := j*8 + dst[i+7:i] := POPCNT(a[i+7:i]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := POPCNT(a[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := POPCNT(a[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst". + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := POPCNT(a[i+7:i]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := POPCNT(a[i+7:i]) + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_BITALG + AVX512VL + Bit Manipulation + + + + Count the number of logical 1 bits in packed 8-bit integers in "a", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE POPCNT(a) { + count := 0 + DO WHILE a > 0 + count += a[0] + a >>= 1 + OD + RETURN count +} +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := POPCNT(a[i+7:i]) + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Bit Manipulation + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst". + +FOR i := 0 to 7 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Bit Manipulation + + + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR i := 0 to 7 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + IF k[i*8+j] + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ELSE + dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8] + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Bit Manipulation + + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR i := 0 to 7 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + IF k[i*8+j] + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ELSE + dst[q+j*8+7:q+j*8] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Bit Manipulation + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst". + +FOR i := 0 to 3 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Bit Manipulation + + + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR i := 0 to 3 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + IF k[i*8+j] + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ELSE + dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8] + FI + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Bit Manipulation + + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR i := 0 to 3 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + IF k[i*8+j] + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ELSE + dst[q+j*8+7:q+j*8] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Bit Manipulation + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst". + +FOR i := 0 to 1 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Bit Manipulation + + + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR i := 0 to 1 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + IF k[i*8+j] + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ELSE + dst[q+j*8+7:q+j*8] := src[q+j*8+7:q+j*8] + FI + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Bit Manipulation + + + + + For each 64-bit element in "b", select 8 unaligned bytes using a byte-granular shift control within the corresponding 64-bit element of "a", and store the 8 assembled bytes to the corresponding 64-bit element of "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR i := 0 to 1 + q := i * 64 + FOR j := 0 to 7 + tmp8 := 0 + ctrl := a[q+j*8+7:q+j*8] & 63 + FOR l := 0 to 7 + tmp8[l] := b[q+((ctrl+l) & 63)] + ENDFOR + IF k[i*8+j] + dst[q+j*8+7:q+j*8] := tmp8[7:0] + ELSE + dst[q+j*8+7:q+j*8] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Swizzle + + + + Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + id := idx[i+5:i]*8 + dst[i+7:i] := a[id+7:id] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Swizzle + + + + + + Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + id := idx[i+5:i]*8 + IF k[j] + dst[i+7:i] := a[id+7:id] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Swizzle + + + + + Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + id := idx[i+5:i]*8 + IF k[j] + dst[i+7:i] := a[id+7:id] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + id := idx[i+4:i]*8 + dst[i+7:i] := a[id+7:id] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + + Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + id := idx[i+4:i]*8 + IF k[j] + dst[i+7:i] := a[id+7:id] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + Shuffle 8-bit integers in "a" across lanes using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + id := idx[i+4:i]*8 + IF k[j] + dst[i+7:i] := a[id+7:id] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + id := idx[i+3:i]*8 + dst[i+7:i] := a[id+7:id] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + + Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + id := idx[i+3:i]*8 + IF k[j] + dst[i+7:i] := a[id+7:id] + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + Shuffle 8-bit integers in "a" using the corresponding index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + id := idx[i+3:i]*8 + IF k[j] + dst[i+7:i] := a[id+7:id] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Swizzle + + + + + Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 63 + i := j*8 + off := 8*idx[i+5:i] + dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Swizzle + + + + + + Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + off := 8*idx[i+5:i] + dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + Swizzle + + + + + + Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 63 + i := j*8 + IF k[j] + off := 8*idx[i+5:i] + dst[i+7:i] := idx[i+6] ? b[off+7:off] : a[off+7:off] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 31 + i := j*8 + off := 8*idx[i+4:i] + dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + + Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + off := 8*idx[i+4:i] + dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + + Shuffle 8-bit integers in "a" and "b" across lanes using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*8 + IF k[j] + off := 8*idx[i+4:i] + dst[i+7:i] := idx[i+5] ? b[off+7:off] : a[off+7:off] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + off := 8*idx[i+3:i] + dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + + Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + off := 8*idx[i+3:i] + dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + AVX512_VBMI + AVX512VL + Swizzle + + + + + + Shuffle 8-bit integers in "a" and "b" using the corresponding selector and index in "idx", and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*8 + IF k[j] + off := 8*idx[i+3:i] + dst[i+7:i] := idx[i+4] ? b[off+7:off] : a[off+7:off] + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 64-bits in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> (c[i+63:i] & 63) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 32-bits in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> (c[i+31:i] & 31) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by the amount specified in the corresponding element of "c", and store the lower 16-bits in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> (c[i+15:i] & 15) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "b" and "a" producing an intermediate 128-bit result. Shift the result right by "imm8" bits, and store the lower 64-bits in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ((b[i+63:i] << 64)[127:0] | a[i+63:i]) >> imm8[5:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "b" and "a" producing an intermediate 64-bit result. Shift the result right by "imm8" bits, and store the lower 32-bits in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ((b[i+31:i] << 32)[63:0] | a[i+31:i]) >> imm8[4:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst". + +FOR j := 0 to 31 + i := j*16 + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst". + +FOR j := 0 to 15 + i := j*16 + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "b" and "a" producing an intermediate 32-bit result. Shift the result right by "imm8" bits, and store the lower 16-bits in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := ((b[i+15:i] << 16)[31:0] | a[i+15:i]) >> imm8[3:0] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst". + +FOR j := 0 to 7 + i := j*64 + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst". + +FOR j := 0 to 3 + i := j*64 + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 64-bits in "dst". + +FOR j := 0 to 1 + i := j*64 + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << (c[i+63:i] & 63) + dst[i+63:i] := tmp[127:64] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst". + +FOR j := 0 to 15 + i := j*32 + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst". + +FOR j := 0 to 7 + i := j*32 + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 32-bits in "dst". + +FOR j := 0 to 3 + i := j*32 + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << (c[i+31:i] & 31) + dst[i+31:i] := tmp[63:32] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst". + +FOR j := 0 to 31 + i := j*16 + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst". + +FOR j := 0 to 15 + i := j*16 + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by the amount specified in the corresponding element of "c", and store the upper 16-bits in "dst". + +FOR j := 0 to 7 + i := j*16 + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << (c[i+15:i] & 15) + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst"). + +FOR j := 0 to 7 + i := j*64 + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst"). + +FOR j := 0 to 3 + i := j*64 + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 1 + i := j*64 + IF k[j] + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 64-bit integers in "a" and "b" producing an intermediate 128-bit result. Shift the result left by "imm8" bits, and store the upper 64-bits in "dst"). + +FOR j := 0 to 1 + i := j*64 + tmp[127:0] := ((a[i+63:i] << 64)[127:0] | b[i+63:i]) << imm8[5:0] + dst[i+63:i] := tmp[127:64] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst". + +FOR j := 0 to 15 + i := j*32 + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst". + +FOR j := 0 to 7 + i := j*32 + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + i := j*32 + IF k[j] + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 32-bit integers in "a" and "b" producing an intermediate 64-bit result. Shift the result left by "imm8" bits, and store the upper 32-bits in "dst". + +FOR j := 0 to 3 + i := j*32 + tmp[63:0] := ((a[i+31:i] << 32)[63:0] | b[i+31:i]) << imm8[4:0] + dst[i+31:i] := tmp[63:32] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 31 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Shift + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst"). + +FOR j := 0 to 31 + i := j*16 + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst"). + +FOR j := 0 to 15 + i := j*16 + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*16 + IF k[j] + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Shift + + + + + Concatenate packed 16-bit integers in "a" and "b" producing an intermediate 32-bit result. Shift the result left by "imm8" bits, and store the upper 16-bits in "dst"). + +FOR j := 0 to 7 + i := j*16 + tmp[31:0] := ((a[i+15:i] << 16)[31:0] | b[i+15:i]) << imm8[3:0] + dst[i+15:i] := tmp[31:16] +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Load + Swizzle + + + + Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m] + m := m + 16 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Load + Swizzle + + + + + Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m] + m := m + 16 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[m+15:m] + m := m + 16 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + + Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[i+15:i] := a[m+15:m] + m := m + 16 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m] + m := m + 16 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + + Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m] + m := m + 16 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[m+15:m] + m := m + 16 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[i+15:i] := a[m+15:m] + m := m + 16 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m] + m := m + 16 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + + Load contiguous active 16-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := MEM[mem_addr+m+15:mem_addr+m] + m := m + 16 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[m+15:m] + m := m + 16 + ELSE + dst[i+15:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Load contiguous active 16-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[i+15:i] := a[m+15:m] + m := m + 16 + ELSE + dst[i+15:i] := src[i+15:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Load + Swizzle + + + + Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m] + m := m + 8 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Load + Swizzle + + + + + Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m] + m := m + 8 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m] + m := m + 8 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + + Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m] + m := m + 8 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m] + m := m + 8 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Load + Swizzle + + + + + Load contiguous active 8-bit integers from unaligned memory at "mem_addr" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := MEM[mem_addr+m+7:mem_addr+m] + m := m + 8 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[m+7:m] + m := m + 8 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + + Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[i+7:i] := a[m+7:m] + m := m + 8 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[m+7:m] + m := m + 8 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[i+7:i] := a[m+7:m] + m := m + 8 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[m+7:m] + m := m + 8 + ELSE + dst[i+7:i] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Load contiguous active 8-bit integers from "a" (those with their respective bit set in mask "k"), and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +m := 0 +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[i+7:i] := a[m+7:m] + m := m + 8 + ELSE + dst[i+7:i] := src[i+7:i] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Store + Swizzle + + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 16 +m := base_addr +FOR j := 0 to 31 + i := j*16 + IF k[j] + MEM[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Store + Swizzle + + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 16 +m := base_addr +FOR j := 0 to 15 + i := j*16 + IF k[j] + MEM[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Store + Swizzle + + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 16 +m := base_addr +FOR j := 0 to 7 + i := j*16 + IF k[j] + MEM[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 16 +m := 0 +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR +dst[511:m] := 0 +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 16 +m := 0 +FOR j := 0 to 31 + i := j*16 + IF k[j] + dst[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR +dst[511:m] := src[511:m] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 16 +m := 0 +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR +dst[255:m] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 16 +m := 0 +FOR j := 0 to 15 + i := j*16 + IF k[j] + dst[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR +dst[255:m] := src[255:m] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 16 +m := 0 +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR +dst[127:m] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Contiguously store the active 16-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 16 +m := 0 +FOR j := 0 to 7 + i := j*16 + IF k[j] + dst[m+size-1:m] := a[i+15:i] + m := m + size + FI +ENDFOR +dst[127:m] := src[127:m] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Store + Swizzle + + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 8 +m := base_addr +FOR j := 0 to 63 + i := j*8 + IF k[j] + MEM[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Store + Swizzle + + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 8 +m := base_addr +FOR j := 0 to 31 + i := j*8 + IF k[j] + MEM[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Store + Swizzle + + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to unaligned memory at "base_addr". + +size := 8 +m := base_addr +FOR j := 0 to 15 + i := j*8 + IF k[j] + MEM[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 8 +m := 0 +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR +dst[511:m] := 0 +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + Swizzle + + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 8 +m := 0 +FOR j := 0 to 63 + i := j*8 + IF k[j] + dst[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR +dst[511:m] := src[511:m] +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 8 +m := 0 +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR +dst[255:m] := 0 +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 8 +m := 0 +FOR j := 0 to 31 + i := j*8 + IF k[j] + dst[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR +dst[255:m] := src[255:m] +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in zeromask "k") to "dst", and set the remaining elements to zero. + +size := 8 +m := 0 +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR +dst[127:m] := 0 +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VBMI2 + AVX512VL + Swizzle + + + + + Contiguously store the active 8-bit integers in "a" (those with their respective bit set in writemask "k") to "dst", and pass through the remaining elements from "src". + +size := 8 +m := 0 +FOR j := 0 to 15 + i := j*8 + IF k[j] + dst[m+size-1:m] := a[i+7:i] + m := m + size + FI +ENDFOR +dst[127:m] := src[127:m] +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst". + +FOR j := 0 to 15 + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst". + +FOR j := 0 to 7 + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst". + +FOR j := 0 to 3 + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst". + +FOR j := 0 to 15 + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst". + +FOR j := 0 to 7 + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 2 adjacent pairs of signed 16-bit integers in "a" with corresponding 16-bit integers in "b", producing 2 intermediate signed 32-bit results. Sum these 2 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst". + +FOR j := 0 to 3 + tmp1.dword := SignExtend32(a.word[2*j]) * SignExtend32(b.word[2*j]) + tmp2.dword := SignExtend32(a.word[2*j+1]) * SignExtend32(b.word[2*j+1]) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst". + +FOR j := 0 to 15 + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst". + +FOR j := 0 to 7 + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src" using signed saturation, and store the packed 32-bit results in "dst". + +FOR j := 0 to 3 + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := Saturate32(src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + Arithmetic + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst". + +FOR j := 0 to 15 + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst". + +FOR j := 0 to 7 + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 + ELSE + dst.dword[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 3 + IF k[j] + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 + ELSE + dst.dword[j] := src.dword[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VNNI + AVX512VL + Arithmetic + + + + + Multiply groups of 4 adjacent pairs of unsigned 8-bit integers in "a" with corresponding signed 8-bit integers in "b", producing 4 intermediate signed 16-bit results. Sum these 4 results with the corresponding 32-bit integer in "src", and store the packed 32-bit results in "dst". + +FOR j := 0 to 3 + tmp1.word := Signed(ZeroExtend16(a.byte[4*j]) * SignExtend16(b.byte[4*j])) + tmp2.word := Signed(ZeroExtend16(a.byte[4*j+1]) * SignExtend16(b.byte[4*j+1])) + tmp3.word := Signed(ZeroExtend16(a.byte[4*j+2]) * SignExtend16(b.byte[4*j+2])) + tmp4.word := Signed(ZeroExtend16(a.byte[4*j+3]) * SignExtend16(b.byte[4*j+3])) + dst.dword[j] := src.dword[j] + tmp1 + tmp2 + tmp3 + tmp4 +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + AVX512_VP2INTERSECT + AVX512VL + Mask + + + + + + Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers. + +MEM[k1+7:k1] := 0 +MEM[k2+7:k2] := 0 +FOR i := 0 TO 3 + FOR j := 0 TO 3 + match := (a.dword[i] == b.dword[j] ? 1 : 0) + MEM[k1+7:k1].bit[i] |= match + MEM[k2+7:k2].bit[j] |= match + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VP2INTERSECT + AVX512VL + Mask + + + + + + Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers. + +MEM[k1+7:k1] := 0 +MEM[k2+7:k2] := 0 +FOR i := 0 TO 7 + FOR j := 0 TO 7 + match := (a.dword[i] == b.dword[j] ? 1 : 0) + MEM[k1+7:k1].bit[i] |= match + MEM[k2+7:k2].bit[j] |= match + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VP2INTERSECT + AVX512F + Mask + + + + + + Compute intersection of packed 32-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers. + +MEM[k1+15:k1] := 0 +MEM[k2+15:k2] := 0 +FOR i := 0 TO 15 + FOR j := 0 TO 15 + match := (a.dword[i] == b.dword[j] ? 1 : 0) + MEM[k1+15:k1].bit[i] |= match + MEM[k2+15:k2].bit[j] |= match + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VP2INTERSECT + AVX512VL + Mask + + + + + + Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers. + +MEM[k1+7:k1] := 0 +MEM[k2+7:k2] := 0 +FOR i := 0 TO 1 + FOR j := 0 TO 1 + match := (a.qword[i] == b.qword[j] ? 1 : 0) + MEM[k1+7:k1].bit[i] |= match + MEM[k2+7:k2].bit[j] |= match + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VP2INTERSECT + AVX512VL + Mask + + + + + + Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers. + +MEM[k1+7:k1] := 0 +MEM[k2+7:k2] := 0 +FOR i := 0 TO 3 + FOR j := 0 TO 3 + match := (a.qword[i] == b.qword[j] ? 1 : 0) + MEM[k1+7:k1].bit[i] |= match + MEM[k2+7:k2].bit[j] |= match + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Integer + AVX512_VP2INTERSECT + AVX512F + Mask + + + + + + Compute intersection of packed 64-bit integer vectors "a" and "b", and store indication of match in the corresponding bit of two mask registers specified by "k1" and "k2". A match in corresponding elements of "a" and "b" is indicated by a set bit in the corresponding bit of the mask registers. + +MEM[k1+7:k1] := 0 +MEM[k2+7:k2] := 0 +FOR i := 0 TO 7 + FOR j := 0 TO 7 + match := (a.qword[i] == b.qword[j] ? 1 : 0) + MEM[k1+7:k1].bit[i] |= match + MEM[k2+7:k2].bit[j] |= match + ENDFOR +ENDFOR + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + + + Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start". + +tmp[511:0] := a +dst[31:0] := ZeroExtend32(tmp[(start[7:0] + len[7:0] - 1):start[7:0]]) + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + + Extract contiguous bits from unsigned 32-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control". + +start := control[7:0] +len := control[15:8] +tmp[511:0] := a +dst[31:0] := ZeroExtend32(tmp[(start[7:0] + len[7:0] - 1):start[7:0]]) + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + + + Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by "len", starting at the bit specified by "start". + +tmp[511:0] := a +dst[63:0] := ZeroExtend64(tmp[(start[7:0] + len[7:0] - 1):start[7:0]]) + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + + Extract contiguous bits from unsigned 64-bit integer "a", and store the result in "dst". Extract the number of bits specified by bits 15:8 of "control", starting at the bit specified by bits 0:7 of "control".. + +start := control[7:0] +len := control[15:8] +tmp[511:0] := a +dst[63:0] := ZeroExtend64(tmp[(start[7:0] + len[7:0] - 1):start[7:0]]) + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Extract the lowest set bit from unsigned 32-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a". + +dst := (-a) AND a + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Extract the lowest set bit from unsigned 64-bit integer "a" and set the corresponding bit in "dst". All other bits in "dst" are zeroed, and all bits are zeroed if no bits are set in "a". + +dst := (-a) AND a + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 32-bit integer "a". + +dst := (a - 1) XOR a + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Set all the lower bits of "dst" up to and including the lowest set bit in unsigned 64-bit integer "a". + +dst := (a - 1) XOR a + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a". + +dst := (a - 1) AND a + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the bit in "dst" that corresponds to the lowest set bit in "a". + +dst := (a - 1) AND a + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + + Compute the bitwise NOT of 32-bit integer "a" and then AND with b, and store the results in dst. + +dst[31:0] := ((NOT a[31:0]) AND b[31:0]) + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + + Compute the bitwise NOT of 64-bit integer "a" and then AND with b, and store the results in dst. + +dst[63:0] := ((NOT a[63:0]) AND b[63:0]) + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Count the number of trailing zero bits in unsigned 32-bit integer "a", and return that count in "dst". + +tmp := 0 +dst := 0 +DO WHILE ((tmp < 32) AND a[tmp] == 0) + tmp := tmp + 1 + dst := dst + 1 +OD + + +

immintrin.h

+ + + Integer + BMI1 + Bit Manipulation + + + Count the number of trailing zero bits in unsigned 64-bit integer "a", and return that count in "dst". + +tmp := 0 +dst := 0 +DO WHILE ((tmp < 64) AND a[tmp] == 0) + tmp := tmp + 1 + dst := dst + 1 +OD + + +

immintrin.h

+ + + Integer + BMI2 + Bit Manipulation + + + + Copy all bits from unsigned 32-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index". + +n := index[7:0] +dst := a +IF (n < 32) + dst[31:n] := 0 +FI + + +

immintrin.h

+ + + Integer + BMI2 + Bit Manipulation + + + + Copy all bits from unsigned 64-bit integer "a" to "dst", and reset (set to 0) the high bits in "dst" starting at "index". + +n := index[7:0] +dst := a +IF (n < 64) + dst[63:n] := 0 +FI + + +

immintrin.h

+ + + Integer + BMI2 + Bit Manipulation + + + + Deposit contiguous low bits from unsigned 32-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero. + +tmp := a +dst := 0 +m := 0 +k := 0 +DO WHILE m < 32 + IF mask[m] == 1 + dst[m] := tmp[k] + k := k + 1 + FI + m := m + 1 +OD + + +

immintrin.h

+ + + Integer + BMI2 + Bit Manipulation + + + + Deposit contiguous low bits from unsigned 64-bit integer "a" to "dst" at the corresponding bit locations specified by "mask"; all other bits in "dst" are set to zero. + +tmp := a +dst := 0 +m := 0 +k := 0 +DO WHILE m < 64 + IF mask[m] == 1 + dst[m] := tmp[k] + k := k + 1 + FI + m := m + 1 +OD + + +

immintrin.h

+ + + Integer + BMI2 + Bit Manipulation + + + + Extract bits from unsigned 32-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero. + +tmp := a +dst := 0 +m := 0 +k := 0 +DO WHILE m < 32 + IF mask[m] == 1 + dst[k] := tmp[m] + k := k + 1 + FI + m := m + 1 +OD + + +

immintrin.h

+ + + Integer + BMI2 + Bit Manipulation + + + + Extract bits from unsigned 64-bit integer "a" at the corresponding bit locations specified by "mask" to contiguous low bits in "dst"; the remaining upper bits in "dst" are set to zero. + +tmp := a +dst := 0 +m := 0 +k := 0 +DO WHILE m < 64 + IF mask[m] == 1 + dst[k] := tmp[m] + k := k + 1 + FI + m := m + 1 +OD + + +

immintrin.h

+ + + Integer + BMI2 + Arithmetic + + + + + Multiply unsigned 32-bit integers "a" and "b", store the low 32-bits of the result in "dst", and store the high 32-bits in "hi". This does not read or write arithmetic flags. + +dst[31:0] := (a * b)[31:0] +MEM[hi+31:hi] := (a * b)[63:32] + + +

immintrin.h

+ + + Integer + BMI2 + Arithmetic + + + + + Multiply unsigned 64-bit integers "a" and "b", store the low 64-bits of the result in "dst", and store the high 64-bits in "hi". This does not read or write arithmetic flags. + +dst[63:0] := (a * b)[63:0] +MEM[hi+63:hi] := (a * b)[127:64] + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a". + +SSP := SSP + a[7:0] * 4 + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Increment the shadow stack pointer by 8 times the value specified in bits [7:0] of "a". + +SSP := SSP + a[7:0] * 8 + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Read the low 32-bits of the current shadow stack pointer, and store the result in "dst". + dst := SSP[31:0] + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Read the current shadow stack pointer, and store the result in "dst". + dst := SSP[63:0] + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Save the previous shadow stack pointer context. + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Restore the saved shadow stack pointer from the shadow stack restore token previously created on shadow stack by saveprevssp. + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + + Write 32-bit value in "val" to a shadow stack page in memory specified by "p". + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + + Write 64-bit value in "val" to a shadow stack page in memory specified by "p". + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + + Write 32-bit value in "val" to a user shadow stack page in memory specified by "p". + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + + Write 64-bit value in "val" to a user shadow stack page in memory specified by "p". + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Mark shadow stack pointed to by IA32_PL0_SSP as busy. + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Mark shadow stack pointed to by "p" as not busy. + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + If CET is enabled, read the low 32-bits of the current shadow stack pointer, and store the result in "dst". Otherwise return 0. + dst := SSP[31:0] + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + If CET is enabled, read the current shadow stack pointer, and store the result in "dst". Otherwise return 0. + dst := SSP[63:0] + + +

immintrin.h

+ + + CET_SS + Miscellaneous + + + Increment the shadow stack pointer by 4 times the value specified in bits [7:0] of "a". + +SSP := SSP + a[7:0] * 4 + + +

immintrin.h

+ + + CLDEMOTE + Miscellaneous + + + Hint to hardware that the cache line that contains "p" should be demoted from the cache closest to the processor core to a level more distant from the processor core. + +

immintrin.h

+ + + CLFLUSHOPT + General Support + + + Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy. + +

immintrin.h

+ + + CLWB + General Support + + + Write back to memory the cache line that contains "p" from any level of the cache hierarchy in the cache coherence domain. + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] * b[63:0]) + c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := (a[31:0] * b[31:0]) + c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively add and subtract packed elements in "c" to/from the intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] * b[63:0]) - c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := (a[31:0] * b[31:0]) - c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) + c[i+63:i] + ELSE + dst[i+63:i] := (a[i+63:i] * b[i+63:i]) - c[i+63:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", alternatively subtract and add packed elements in "c" from/to the intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) - c[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) + c[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", add the negated intermediate result to packed elements in "c", and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := -(a[63:0] * b[63:0]) + c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and add the negated intermediate result to the lower element in "c". Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := -(a[31:0] * b[31:0]) + c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := -(a[i+63:i] * b[i+63:i]) - c[i+63:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", subtract packed elements in "c" from the negated intermediate result, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + dst[i+31:i] := -(a[i+31:i] * b[i+31:i]) - c[i+31:i] +ENDFOR +dst[MAX:256] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower double-precision (64-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := -(a[63:0] * b[63:0]) - c[63:0] +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FMA + Arithmetic + + + + + Multiply the lower single-precision (32-bit) floating-point elements in "a" and "b", and subtract the lower element in "c" from the negated intermediate result. Store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := -(a[31:0] * b[31:0]) - c[31:0] +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + + + +

immintrin.h

+ + + Floating Point + FP16C + Convert + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 7 + i := j*32 + m := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Floating Point + FP16C + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". + [sae_note] + +FOR j := 0 to 7 + i := 16*j + l := 32*j + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Floating Point + FP16C + Convert + + + Convert packed half-precision (16-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + m := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(a[m+15:m]) +ENDFOR +dst[MAX:128] := 0 + + +

emmintrin.h

+ + + Floating Point + FP16C + Convert + + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed half-precision (16-bit) floating-point elements, and store the results in "dst". + [sae_note] + +FOR j := 0 to 3 + i := 16*j + l := 32*j + dst[i+15:i] := Convert_FP32_To_FP16(a[l+31:l]) +ENDFOR +dst[MAX:64] := 0 + + +

emmintrin.h

+ + + Integer + FSGSBASE + General Support + + Read the FS segment base register and store the 32-bit result in "dst". + dst[31:0] := FS_Segment_Base_Register +dst[63:32] := 0 + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + Read the FS segment base register and store the 64-bit result in "dst". + dst[63:0] := FS_Segment_Base_Register + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + Read the GS segment base register and store the 32-bit result in "dst". + dst[31:0] := GS_Segment_Base_Register +dst[63:32] := 0 + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + Read the GS segment base register and store the 64-bit result in "dst". + dst[63:0] := GS_Segment_Base_Register + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + + Write the unsigned 32-bit integer "a" to the FS segment base register. + +FS_Segment_Base_Register[31:0] := a[31:0] +FS_Segment_Base_Register[63:32] := 0 + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + + Write the unsigned 64-bit integer "a" to the FS segment base register. + +FS_Segment_Base_Register[63:0] := a[63:0] + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + + Write the unsigned 32-bit integer "a" to the GS segment base register. + +GS_Segment_Base_Register[31:0] := a[31:0] +GS_Segment_Base_Register[63:32] := 0 + + +

immintrin.h

+ + + Integer + FSGSBASE + General Support + + + Write the unsigned 64-bit integer "a" to the GS segment base register. + +GS_Segment_Base_Register[63:0] := a[63:0] + + +

immintrin.h

+ + + FXSR + OS-Targeted + + + Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary. + state_x87_fpu_mmx_sse := fxrstor(MEM[mem_addr+512*8:mem_addr]) + + +

immintrin.h

+ + + FXSR + OS-Targeted + + + Reload the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image at "mem_addr". This data should have been written to memory previously using the FXSAVE64 instruction, and in the same format as required by the operating mode. "mem_addr" must be aligned on a 16-byte boundary. + state_x87_fpu_mmx_sse := fxrstor64(MEM[mem_addr+512*8:mem_addr]) + + +

immintrin.h

+ + + FXSR + OS-Targeted + + + Save the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location at "mem_addr". The layout of the 512-byte region depends on the operating mode. Bytes [511:464] are available for software use and will not be overwritten by the processor. + MEM[mem_addr+512*8:mem_addr] := fxsave(state_x87_fpu_mmx_sse) + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 63 + IF k[j] + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) + ELSE + dst.byte[j] := 0 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 63 + IF k[j] + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) + ELSE + dst.byte[j] := src.byte[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 63 + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 31 + IF k[j] + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) + ELSE + dst.byte[j] := 0 + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 31 + IF k[j] + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) + ELSE + dst.byte[j] := src.byte[j] + FI +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 31 + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 15 + IF k[j] + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) + ELSE + dst.byte[j] := 0 + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst" using writemask "k" (elements are copied from "src"" when the corresponding mask bit is not set). The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 15 + IF k[j] + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) + ELSE + dst.byte[j] := src.byte[j] + FI +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + Multiply the packed 8-bit integers in "a" and "b" in the finite field GF(2^8), and store the results in "dst". The field GF(2^8) is represented in polynomial representation with the reduction polynomial x^8 + x^4 + x^3 + x + 1. + +DEFINE gf2p8mul_byte(src1byte, src2byte) { + tword := 0 + FOR i := 0 to 7 + IF src2byte.bit[i] + tword := tword XOR (src1byte << i) + FI + ENDFOR + FOR i := 14 downto 8 + p := 0x11B << (i-8) + IF tword.bit[i] + tword := tword XOR p + FI + ENDFOR + RETURN tword.byte[0] +} +FOR j := 0 TO 15 + dst.byte[j] := gf2p8mul_byte(a.byte[j], b.byte[j]) +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 7 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 7 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := src.qword[j].byte[i] + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst". + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 7 + FOR i := 0 to 7 + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 3 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 3 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := src.qword[j].byte[i] + FI + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst". + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 3 + FOR i := 0 to 7 + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 1 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 1 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := src.qword[j].byte[i] + FI + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + Compute an affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. Store the packed 8-bit results in "dst". + +DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND src1byte) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 1 + FOR i := 0 to 7 + dst.qword[j].byte[i] := affine_byte(A.qword[j], x.qword[j].byte[i], b) + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 7 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 7 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := src.qword[j].byte[b] + FI + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512F + Arithmetic + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst". + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 7 + FOR i := 0 to 7 + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ENDFOR +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 3 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 3 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := src.qword[j].byte[i] + FI + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst". + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 3 + FOR i := 0 to 7 + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ENDFOR +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using zeromask "k" (elements are zeroed out when the corresponding mask bit is not set). + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 1 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := 0 + FI + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 1 + FOR i := 0 to 7 + IF k[j*8+i] + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ELSE + dst.qword[j].byte[i] := src.qword[j].byte[i] + FI + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + Integer + GFNI + AVX512VL + Arithmetic + + + + + Compute an inverse affine transformation in the Galois Field 2^8. An affine transformation is defined by "A" * "x" + "b", where "A" represents an 8 by 8 bit matrix, "x" represents an 8-bit vector, and "b" is a constant immediate byte. The inverse of the 8-bit values in "x" is defined with respect to the reduction polynomial x^8 + x^4 + x^3 + x + 1. Store the packed 8-bit results in "dst". + DEFINE parity(x) { + t := 0 + FOR i := 0 to 7 + t := t XOR x.bit[i] + ENDFOR + RETURN t +} +DEFINE affine_inverse_byte(tsrc2qw, src1byte, imm8) { + FOR i := 0 to 7 + retbyte.bit[i] := parity(tsrc2qw.byte[7-i] AND inverse(src1byte)) XOR imm8.bit[i] + ENDFOR + RETURN retbyte +} +FOR j := 0 TO 1 + FOR i := 0 to 7 + dst.qword[j].byte[i] := affine_inverse_byte(A.qword[j], x.qword[j].byte[i], b) + ENDFOR +ENDFOR +dst[MAX:128] := 0 + + +

immintrin.h

+ + + INVPCID + OS-Targeted + + + + Invalidate mappings in the Translation Lookaside Buffers (TLBs) and paging-structure caches for the processor context identifier (PCID) specified by "descriptor" based on the invalidation type specified in "type". + The PCID "descriptor" is specified as a 16-byte memory operand (with no alignment restrictions) where bits [11:0] specify the PCID, and bits [127:64] specify the linear address; bits [63:12] are reserved. + The types supported are: + 0) Individual-address invalidation: If "type" is 0, the logical processor invalidates mappings for a single linear address and tagged with the PCID specified in "descriptor", except global translations. The instruction may also invalidate global translations, mappings for other linear addresses, or mappings tagged with other PCIDs. + 1) Single-context invalidation: If "type" is 1, the logical processor invalidates all mappings tagged with the PCID specified in "descriptor" except global translations. In some cases, it may invalidate mappings for other PCIDs as well. + 2) All-context invalidation: If "type" is 2, the logical processor invalidates all mappings tagged with any PCID. + 3) All-context invalidation, retaining global translations: If "type" is 3, the logical processor invalidates all mappings tagged with any PCID except global translations, ignoring "descriptor". The instruction may also invalidate global translations as well. + +CASE type[1:0] OF +0: // individual-address invalidation retaining global translations + OP_PCID := MEM[descriptor+11:descriptor] + ADDR := MEM[descriptor+127:descriptor+64] + BREAK +1: // single PCID invalidation retaining globals + OP_PCID := MEM[descriptor+11:descriptor] + // invalidate all mappings tagged with OP_PCID except global translations + BREAK +2: // all PCID invalidation + // invalidate all mappings tagged with any PCID + BREAK +3: // all PCID invalidation retaining global translations + // invalidate all mappings tagged with any PCID except global translations + BREAK +ESAC + + +

immintrin.h

+ + + KNCNI + General Support + + + + Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i". + + + + + + + + +

xmmintrin.h

+ + + Mask + KNCNI + Mask + + + + Compute the bitwise NOT of 16-bit masks "a" and then AND with "b", and store the result in "k". + +k[15:0] := (NOT a[15:0]) AND b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Compute the bitwise AND of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] AND b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + Copy 16-bit mask "a" to "k". + +k[15:0] := a[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + Compute the bitwise NOT of 16-bit mask "a", and store the result in "k". + +k[15:0] := NOT a[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Compute the bitwise OR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] OR b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Compute the bitwise XNOR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := NOT (a[15:0] XOR b[15:0]) +k[MAX:16] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Compute the bitwise XOR of 16-bit masks "a" and "b", and store the result in "k". + +k[15:0] := a[15:0] XOR b[15:0] +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + KNCNI + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in mask vector "k". + +FOR j := 0 to 15 + i := j*32 + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Integer + Mask + KNCNI + Compare + + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than-or-equal, and store the results in mask vector "k" using zeromask "k1" (elements are zeroed out when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k1[j] + k[j] := ( a[i+31:i] < b[i+31:i] ) ? 1 : 0 + ELSE + k[j] := 0 + FI +ENDFOR +k[MAX:16] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + Depending on "bc", loads 1, 4, or 16 elements of type and size determined by "conv" from memory address "mt" and converts all elements to single-precision (32-bit) floating-point elements, storing the results in "dst". "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + CASE bc OF + _MM_BROADCAST32_NONE: + CASE conv OF + _MM_UPCONV_PS_NONE: + n := j*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_PS_FLOAT16: + n := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_UINT8: + n := j*8 + dst[i+31:i] := Convert_UInt8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_SINT8: + n := j*8 + dst[i+31:i] := Convert_Int8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_UINT16: + n := j*16 + dst[i+31:i] := Convert_UInt16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_SINT16: + n := j*16 + dst[i+31:i] := Convert_Int16_To_FP32(addr[n+15:n]) + ESAC + _MM_BROADCAST_1X16: + CASE conv OF + _MM_UPCONV_PS_NONE: + n := j*32 + dst[i+31:i] := addr[31:0] + _MM_UPCONV_PS_FLOAT16: + n := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(addr[15:0]) + _MM_UPCONV_PS_UINT8: + n := j*8 + dst[i+31:i] := Convert_UInt8_To_FP32(addr[7:0]) + _MM_UPCONV_PS_SINT8: + n := j*8 + dst[i+31:i] := Convert_Int8_To_FP32(addr[7:0]) + _MM_UPCONV_PS_UINT16: + n := j*16 + dst[i+31:i] := Convert_UInt16_To_FP32(addr[15:0]) + _MM_UPCONV_PS_SINT16: + n := j*16 + dst[i+31:i] := Convert_Int16_To_FP32(addr[15:0]) + ESAC + _MM_BROADCAST_4X16: + mod := j%4 + CASE conv OF + _MM_UPCONV_PS_NONE: + n := mod*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_PS_FLOAT16: + n := mod*16 + dst[i+31:i] := Convert_FP16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_UINT8: + n := mod*8 + dst[i+31:i] := Convert_UInt8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_SINT8: + n := mod*8 + dst[i+31:i] := Convert_Int8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_UINT16: + n := mod*16 + dst[i+31:i] := Convert_UInt16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_SINT16: + n := mod*16 + dst[i+31:i] := Convert_Int16_To_FP32(addr[n+15:n]) + ESAC + ESAC +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + + Depending on "bc", loads 1, 4, or 16 elements of type and size determined by "conv" from memory address "mt" and converts all elements to single-precision (32-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + IF k[j] + CASE bc OF + _MM_BROADCAST32_NONE: + CASE conv OF + _MM_UPCONV_PS_NONE: + n := j*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_PS_FLOAT16: + n := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_UINT8: + n := j*8 + dst[i+31:i] := Convert_UInt8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_SINT8: + n := j*8 + dst[i+31:i] := Convert_Int8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_UINT16: + n := j*16 + dst[i+31:i] := Convert_UInt16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_SINT16: + n := j*16 + dst[i+31:i] := Convert_Int16_To_FP32(addr[n+15:n]) + ESAC + _MM_BROADCAST_1X16: + CASE conv OF + _MM_UPCONV_PS_NONE: + n := j*32 + dst[i+31:i] := addr[31:0] + _MM_UPCONV_PS_FLOAT16: + n := j*16 + dst[i+31:i] := Convert_FP16_To_FP32(addr[15:0]) + _MM_UPCONV_PS_UINT8: + n := j*8 + dst[i+31:i] := Convert_UInt8_To_FP32(addr[7:0]) + _MM_UPCONV_PS_SINT8: + n := j*8 + dst[i+31:i] := Convert_Int8_To_FP32(addr[7:0]) + _MM_UPCONV_PS_UINT16: + n := j*16 + dst[i+31:i] := Convert_UInt16_To_FP32(addr[15:0]) + _MM_UPCONV_PS_SINT16: + n := j*16 + dst[i+31:i] := Convert_Int16_To_FP32(addr[15:0]) + ESAC + _MM_BROADCAST_4X16: + mod := j%4 + CASE conv OF + _MM_UPCONV_PS_NONE: + n := mod*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_PS_FLOAT16: + n := mod*16 + dst[i+31:i] := Convert_FP16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_UINT8: + n := mod*8 + dst[i+31:i] := Convert_UInt8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_SINT8: + n := mod*8 + dst[i+31:i] := Convert_Int8_To_FP32(addr[n+7:n]) + _MM_UPCONV_PS_UINT16: + n := mod*16 + dst[i+31:i] := Convert_UInt16_To_FP32(addr[n+15:n]) + _MM_UPCONV_PS_SINT16: + n := mod*16 + dst[i+31:i] := Convert_Int16_To_FP32(addr[n+15:n]) + ESAC + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + Depending on "bc", loads 1, 4, or 16 elements of type and size determined by "conv" from memory address "mt" and converts all elements to 32-bit integer elements, storing the results in "dst". "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + CASE bc OF + _MM_BROADCAST32_NONE: + CASE conv OF + _MM_UPCONV_EPI32_NONE: + n := j*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_EPI32_UINT8: + n := j*8 + dst[i+31:i] := ZeroExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_SINT8: + n := j*8 + dst[i+31:i] := SignExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_UINT16: + n := j*16 + dst[i+31:i] := ZeroExtend32(addr[n+15:n]) + _MM_UPCONV_EPI32_SINT16: + n := j*16 + dst[i+31:i] := SignExtend32(addr[n+15:n]) + ESAC + _MM_BROADCAST_1X16: + CASE conv OF + _MM_UPCONV_EPI32_NONE: + n := j*32 + dst[i+31:i] := addr[31:0] + _MM_UPCONV_EPI32_UINT8: + n := j*8 + dst[i+31:i] := ZeroExtend32(addr[7:0]) + _MM_UPCONV_EPI32_SINT8: + n := j*8 + dst[i+31:i] := SignExtend32(addr[7:0]) + _MM_UPCONV_EPI32_UINT16: + n := j*16 + dst[i+31:i] := ZeroExtend32(addr[15:0]) + _MM_UPCONV_EPI32_SINT16: + n := j*16 + dst[i+31:i] := SignExtend32(addr[15:0]) + ESAC + _MM_BROADCAST_4X16: + mod := j%4 + CASE conv OF + _MM_UPCONV_EPI32_NONE: + n := mod*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_EPI32_UINT8: + n := mod*8 + dst[i+31:i] := ZeroExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_SINT8: + n := mod*8 + dst[i+31:i] := SignExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_UINT16: + n := mod*16 + dst[i+31:i] := ZeroExtend32(addr[n+15:n]) + _MM_UPCONV_EPI32_SINT16: + n := mod*16 + dst[i+31:i] := SignExtend32(addr[n+15:n]) + ESAC + ESAC +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + + Depending on "bc", loads 1, 4, or 16 elements of type and size determined by "conv" from memory address "mt" and converts all elements to 32-bit integer elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + IF k[j] + CASE bc OF + _MM_BROADCAST32_NONE: + CASE conv OF + _MM_UPCONV_EPI32_NONE: + n := j*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_EPI32_UINT8: + n := j*8 + dst[i+31:i] := ZeroExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_SINT8: + n := j*8 + dst[i+31:i] := SignExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_UINT16: + n := j*16 + dst[i+31:i] := ZeroExtend32(addr[n+15:n]) + _MM_UPCONV_EPI32_SINT16: + n := j*16 + dst[i+31:i] := SignExtend32(addr[n+15:n]) + ESAC + _MM_BROADCAST_1X16: + CASE conv OF + _MM_UPCONV_EPI32_NONE: + n := j*32 + dst[i+31:i] := addr[31:0] + _MM_UPCONV_EPI32_UINT8: + n := j*8 + dst[i+31:i] := ZeroExtend32(addr[7:0]) + _MM_UPCONV_EPI32_SINT8: + n := j*8 + dst[i+31:i] := SignExtend32(addr[7:0]) + _MM_UPCONV_EPI32_UINT16: + n := j*16 + dst[i+31:i] := ZeroExtend32(addr[15:0]) + _MM_UPCONV_EPI32_SINT16: + n := j*16 + dst[i+31:i] := SignExtend32(addr[15:0]) + ESAC + _MM_BROADCAST_4X16: + mod := j%4 + CASE conv OF + _MM_UPCONV_EPI32_NONE: + n := mod*32 + dst[i+31:i] := addr[n+31:n] + _MM_UPCONV_EPI32_UINT8: + n := mod*8 + dst[i+31:i] := ZeroExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_SINT8: + n := mod*8 + dst[i+31:i] := SignExtend32(addr[n+7:n]) + _MM_UPCONV_EPI32_UINT16: + n := mod*16 + dst[i+31:i] := ZeroExtend32(addr[n+15:n]) + _MM_UPCONV_EPI32_SINT16: + n := mod*16 + dst[i+31:i] := SignExtend32(addr[n+15:n]) + ESAC + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + Depending on "bc", loads 1, 4, or 8 elements of type and size determined by "conv" from memory address "mt" and converts all elements to double-precision (64-bit) floating-point elements, storing the results in "dst". "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + CASE bc OF + _MM_BROADCAST64_NONE: + CASE conv OF + _MM_UPCONV_PD_NONE: + n := j*64 + dst[i+63:i] := addr[n+63:n] + ESAC + _MM_BROADCAST_1X8: + CASE conv OF + _MM_UPCONV_PD_NONE: + n := j*64 + dst[i+63:i] := addr[63:0] + ESAC + _MM_BROADCAST_4X8: + mod := j%4 + CASE conv OF + _MM_UPCONV_PD_NONE: + n := mod*64 + dst[i+63:i] := addr[n+63:n] + ESAC + ESAC +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + + Depending on "bc", loads 1, 4, or 8 elements of type and size determined by "conv" from memory address "mt" and converts all elements to double-precision (64-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + IF k[j] + CASE bc OF + _MM_BROADCAST64_NONE: + CASE conv OF + _MM_UPCONV_PD_NONE: + n := j*64 + dst[i+63:i] := addr[n+63:n] + ESAC + _MM_BROADCAST_1X8: + CASE conv OF + _MM_UPCONV_PD_NONE: + n := j*64 + dst[i+63:i] := addr[63:0] + ESAC + _MM_BROADCAST_4X8: + mod := j%4 + CASE conv OF + _MM_UPCONV_PD_NONE: + n := mod*64 + dst[i+63:i] := addr[n+63:n] + ESAC + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + Depending on "bc", loads 1, 4, or 8 elements of type and size determined by "conv" from memory address "mt" and converts all elements to 64-bit integer elements, storing the results in "dst". "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + CASE bc OF + _MM_BROADCAST64_NONE: + CASE conv OF + _MM_UPCONV_EPI64_NONE: + n := j*64 + dst[i+63:i] := addr[n+63:n] + ESAC + _MM_BROADCAST_1X8: + CASE conv OF + _MM_UPCONV_EPI64_NONE: + n := j*64 + dst[i+63:i] := addr[63:0] + ESAC + _MM_BROADCAST_4X8: + mod := j%4 + CASE conv OF + _MM_UPCONV_EPI64_NONE: + n := mod*64 + dst[i+63:i] := addr[n+63:n] + ESAC + ESAC +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + + Depending on "bc", loads 1, 4, or 8 elements of type and size determined by "conv" from memory address "mt" and converts all elements to 64-bit integer elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + IF k[j] + CASE bc OF + _MM_BROADCAST64_NONE: + CASE conv OF + _MM_UPCONV_EPI64_NONE: + n := j*64 + dst[i+63:i] := addr[n+63:n] + ESAC + _MM_BROADCAST_1X8: + CASE conv OF + _MM_UPCONV_EPI64_NONE: + n := j*64 + dst[i+63:i] := addr[63:0] + ESAC + _MM_BROADCAST_4X8: + mod := j%4 + CASE conv OF + _MM_UPCONV_EPI64_NONE: + n := mod*64 + dst[i+63:i] := addr[n+63:n] + ESAC + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + + + +

immintrin.h

+ + + Floating Point + KNCNI + Swizzle + + + + Performs a swizzle transformation of each of the four groups of packed 4xsingle-precision (32-bit) floating-point elements in "v" using swizzle parameter "s", storing the results in "dst". + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 7 + i := j*64 + dst[i+31:i] := v[i+63:i+32] + dst[i+63:i+32] := v[i+31:i] + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+95:i+64] + dst[i+63:i+32] := v[i+127:i+96] + dst[i+95:i+64] := v[i+31:i] + dst[i+127:i+96] := v[i+63:i+32] + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+31:i] + dst[i+63:i+32] := v[i+31:i] + dst[i+95:i+64] := v[i+31:i] + dst[i+127:i+96] := v[i+31:i] + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+63:i+32] + dst[i+63:i+32] := v[i+63:i+32] + dst[i+95:i+64] := v[i+63:i+32] + dst[i+127:i+96] := v[i+63:i+32] + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+95:i+64] + dst[i+63:i+32] := v[i+95:i+64] + dst[i+95:i+64] := v[i+95:i+64] + dst[i+127:i+96] := v[i+95:i+64] + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+127:i+96] + dst[i+63:i+32] := v[i+127:i+96] + dst[i+95:i+64] := v[i+127:i+96] + dst[i+127:i+96] := v[i+127:i+96] + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+63:i+32] + dst[i+63:i+32] := v[i+95:i+64] + dst[i+95:i+64] := v[i+31:i] + dst[i+127:i+96] := v[i+127:i+96] + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Swizzle + + + + Performs a swizzle transformation of each of the two groups of packed 4x double-precision (64-bit) floating-point elements in "v" using swizzle parameter "s", storing the results in "dst". + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := v[i+127:i+64] + dst[i+127:i+64] := v[i+63:i] + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+191:i+128] + dst[i+127:i+64] := v[i+255:i+192] + dst[i+191:i+128] := v[i+63:i] + dst[i+255:i+192] := v[i+127:i+64] + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+63:i] + dst[i+127:i+64] := v[i+63:i] + dst[i+191:i+128] := v[i+63:i] + dst[i+255:i+192] := v[i+63:i] + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+127:i+63] + dst[i+127:i+64] := v[i+127:i+63] + dst[i+191:i+128] := v[i+127:i+63] + dst[i+255:i+192] := v[i+127:i+63] + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+191:i+128] + dst[i+127:i+64] := v[i+191:i+128] + dst[i+191:i+128] := v[i+191:i+128] + dst[i+255:i+192] := v[i+191:i+128] + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+255:i+192] + dst[i+127:i+64] := v[i+255:i+192] + dst[i+191:i+128] := v[i+255:i+192] + dst[i+255:i+192] := v[i+255:i+192] + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+127:i+64] + dst[i+127:i+64] := v[i+191:i+128] + dst[i+191:i+128] := v[i+63:i] + dst[i+255:i+192] := v[i+255:i+192] + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Swizzle + + + + Performs a swizzle transformation of each of the four groups of packed 4x 32-bit integer elements in "v" using swizzle parameter "s", storing the results in "dst". + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 7 + i := j*64 + dst[i+31:i] := v[i+63:i+32] + dst[i+63:i+32] := v[i+31:i] + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+95:i+64] + dst[i+63:i+32] := v[i+127:i+96] + dst[i+95:i+64] := v[i+31:i] + dst[i+127:i+96] := v[i+63:i+32] + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+31:i] + dst[i+63:i+32] := v[i+31:i] + dst[i+95:i+64] := v[i+31:i] + dst[i+127:i+96] := v[i+31:i] + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+63:i+32] + dst[i+63:i+32] := v[i+63:i+32] + dst[i+95:i+64] := v[i+63:i+32] + dst[i+127:i+96] := v[i+63:i+32] + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+95:i+64] + dst[i+63:i+32] := v[i+95:i+64] + dst[i+95:i+64] := v[i+95:i+64] + dst[i+127:i+96] := v[i+95:i+64] + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+127:i+96] + dst[i+63:i+32] := v[i+127:i+96] + dst[i+95:i+64] := v[i+127:i+96] + dst[i+127:i+96] := v[i+127:i+96] + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 3 + i := j*128 + dst[i+31:i] := v[i+63:i+32] + dst[i+63:i+32] := v[i+95:i+64] + dst[i+95:i+64] := v[i+31:i] + dst[i+127:i+96] := v[i+127:i+96] + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Swizzle + + + + Performs a swizzle transformation of each of the two groups of packed 4x64-bit integer elements in "v" using swizzle parameter "s", storing the results in "dst". + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 3 + i := j*64 + dst[i+63:i] := v[i+127:i+64] + dst[i+127:i+64] := v[i+63:i] + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+191:i+128] + dst[i+127:i+64] := v[i+255:i+192] + dst[i+191:i+128] := v[i+63:i] + dst[i+255:i+192] := v[i+127:i+64] + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+63:i] + dst[i+127:i+64] := v[i+63:i] + dst[i+191:i+128] := v[i+63:i] + dst[i+255:i+192] := v[i+63:i] + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+127:i+63] + dst[i+127:i+64] := v[i+127:i+63] + dst[i+191:i+128] := v[i+127:i+63] + dst[i+255:i+192] := v[i+127:i+63] + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+191:i+128] + dst[i+127:i+64] := v[i+191:i+128] + dst[i+191:i+128] := v[i+191:i+128] + dst[i+255:i+192] := v[i+191:i+128] + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+255:i+192] + dst[i+127:i+64] := v[i+255:i+192] + dst[i+191:i+128] := v[i+255:i+192] + dst[i+255:i+192] := v[i+255:i+192] + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 1 + i := j*256 + dst[i+63:i] := v[i+127:i+64] + dst[i+127:i+64] := v[i+191:i+128] + dst[i+191:i+128] := v[i+63:i] + dst[i+255:i+192] := v[i+255:i+192] + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Swizzle + + + + + + Performs a swizzle transformation of each of the four groups of packed 4x single-precision (32-bit) floating-point elements in "v" using swizzle parameter "s", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 7 + i := j*64 + IF k[j*2] + dst[i+31:i] := v[i+63:i+32] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*2+1] + dst[i+63:i+32] := v[i+31:i] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+95:i+64] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+127:i+96] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+31:i] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+63:i+32] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+31:i] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+31:i] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+31:i] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+63:i+32] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+63:i+32] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+63:i+32] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+63:i+32] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+95:i+64] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+95:i+64] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+95:i+64] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+95:i+64] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+127:i+96] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+127:i+96] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+127:i+96] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+127:i+96] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+63:i+32] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+95:i+64] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+31:i] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+127:i+96] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Swizzle + + + + + + Performs a swizzle transformation of each of the two groups of packed 4x double-precision (64-bit) floating-point elements in "v" using swizzle parameter "s", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 3 + i := j*64 + IF k[j*2] + dst[i+63:i] := v[i+127:i+64] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*2+1] + dst[i+127:i+64] := v[i+63:i] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+191:i+128] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+255:i+192] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+63:i] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+127:i+64] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+63:i] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+63:i] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+63:i] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+127:i+63] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+127:i+63] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+127:i+63] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+127:i+63] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+191:i+128] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+191:i+128] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+191:i+128] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+191:i+128] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+255:i+192] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+255:i+192] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+255:i+192] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+255:i+192] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+127:i+64] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+191:i+128] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+63:i] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+255:i+192] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Swizzle + + + + + + Performs a swizzle transformation of each of the four groups of packed 4x32-bit integer elements in "v" using swizzle parameter "s", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 7 + i := j*64 + IF k[j*2] + dst[i+31:i] := v[i+63:i+32] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*2+1] + dst[i+63:i+32] := v[i+31:i] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+95:i+64] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+127:i+96] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+31:i] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+63:i+32] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+31:i] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+31:i] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+31:i] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+63:i+32] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+63:i+32] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+63:i+32] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+63:i+32] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+95:i+64] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+95:i+64] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+95:i+64] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+95:i+64] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+127:i+96] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+127:i+96] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+127:i+96] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+127:i+96] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 3 + i := j*128 + IF k[j*4] + dst[i+31:i] := v[i+63:i+32] + ELSE + dst[i+31:i] := src[i+31:i] + FI + IF k[j*4+1] + dst[i+63:i+32] := v[i+95:i+64] + ELSE + dst[i+63:i+32] := src[i+63:i+32] + FI + IF k[j*4+2] + dst[i+95:i+64] := v[i+31:i] + ELSE + dst[i+95:i+64] := src[i+95:i+64] + FI + IF k[j*4+3] + dst[i+127:i+96] := v[i+127:i+96] + ELSE + dst[i+127:i+96] := src[i+127:i+96] + FI + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Swizzle + + + + + + Performs a swizzle transformation of each of the four groups of packed 4x64-bit integer elements in "v" using swizzle parameter "s", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + CASE s OF +_MM_SWIZ_REG_NONE: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_DCBA: + dst[511:0] := v[511:0] +_MM_SWIZ_REG_CDAB: + FOR j := 0 to 3 + i := j*64 + IF k[j*2] + dst[i+63:i] := v[i+127:i+64] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*2+1] + dst[i+127:i+64] := v[i+63:i] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + ENDFOR +_MM_SWIZ_REG_BADC: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+191:i+128] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+255:i+192] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+63:i] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+127:i+64] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_AAAA: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+63:i] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+63:i] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+63:i] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_BBBB: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+127:i+63] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+127:i+63] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+127:i+63] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+127:i+63] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_CCCC: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+191:i+128] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+191:i+128] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+191:i+128] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+191:i+128] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_DDDD: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+255:i+192] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+255:i+192] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+255:i+192] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+255:i+192] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +_MM_SWIZ_REG_DACB: + FOR j := 0 to 1 + i := j*256 + IF k[j*4] + dst[i+63:i] := v[i+127:i+64] + ELSE + dst[i+63:i] := src[i+63:i] + FI + IF k[j*4+1] + dst[i+127:i+64] := v[i+191:i+128] + ELSE + dst[i+127:i+64] := src[i+127:i+64] + FI + IF k[j*4+2] + dst[i+191:i+128] := v[i+63:i] + ELSE + dst[i+191:i+128] := src[i+191:i+128] + FI + IF k[j*4+3] + dst[i+255:i+192] := v[i+255:i+192] + ELSE + dst[i+255:i+192] := src[i+255:i+192] + FI + ENDFOR +ESAC +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Downconverts packed single-precision (32-bit) floating-point elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt". "hint" indicates to the processor whether the data is non-temporal. + +addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + CASE conv OF + _MM_DOWNCONV_PS_NONE: + addr[i+31:i] := v[i+31:i] + _MM_DOWNCONV_PS_FLOAT16: + n := j*16 + addr[n+15:n] := Convert_FP32_To_FP16(v[i+31:i]) + _MM_DOWNCONV_PS_UINT8: + n := j*8 + addr[n+7:n] := Convert_FP32_To_UInt8(v[i+31:i]) + _MM_DOWNCONV_PS_SINT8: + n := j*8 + addr[n+7:n] := Convert_FP32_To_Int8(v[i+31:i]) + _MM_DOWNCONV_PS_UINT16: + n := j*16 + addr[n+15:n] := Convert_FP32_To_UInt16(v[i+31:i]) + _MM_DOWNCONV_PS_SINT16: + n := j*16 + addr[n+15:n] := Convert_FP32_To_Int16(v[i+31:i]) + ESAC +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Downconverts packed 32-bit integer elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt". "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + CASE conv OF + _MM_DOWNCONV_EPI32_NONE: + addr[i+31:i] := v[i+31:i] + _MM_DOWNCONV_EPI32_UINT8: + n := j*8 + addr[n+7:n] := Int32ToUInt8(v[i+31:i]) + _MM_DOWNCONV_EPI32_SINT8: + n := j*8 + addr[n+7:n] := Int32ToSInt8(v[i+31:i]) + _MM_DOWNCONV_EPI32_UINT16: + n := j*16 + addr[n+15:n] := Int32ToUInt16(v[i+31:i]) + _MM_DOWNCONV_EPI32_SINT16: + n := j*16 + addr[n+15:n] := Int32ToSInt16(v[i+31:i]) + ESAC +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Downconverts packed double-precision (64-bit) floating-point elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt". "hint" indicates to the processor whether the data is non-temporal. + +addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + CASE conv OF + _MM_DOWNCONV_PS_NONE: + addr[i+63:i] := v[i+63:i] + ESAC +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Downconverts packed 64-bit integer elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt". "hint" indicates to the processor whether the data is non-temporal. + +addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: addr[i+63:i] := v[i+63:i] + ESAC +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Downconverts packed single-precision (32-bit) floating-point elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt" using writemask "k" (elements are not written to memory when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 15 + i := j*32 + IF k[j] + CASE conv OF + _MM_DOWNCONV_PS_NONE: + mt[i+31:i] := v[i+31:i] + _MM_DOWNCONV_PS_FLOAT16: + n := j*16 + mt[n+15:n] := Convert_FP32_To_FP16(v[i+31:i]) + _MM_DOWNCONV_PS_UINT8: + n := j*8 + mt[n+7:n] := Convert_FP32_To_UInt8(v[i+31:i]) + _MM_DOWNCONV_PS_SINT8: + n := j*8 + mt[n+7:n] := Convert_FP32_To_Int8(v[i+31:i]) + _MM_DOWNCONV_PS_UINT16: + n := j*16 + mt[n+15:n] := Convert_FP32_To_UInt16(v[i+31:i]) + _MM_DOWNCONV_PS_SINT16: + n := j*16 + mt[n+15:n] := Convert_FP32_To_Int16(v[i+31:i]) + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Downconverts packed double-precision (64-bit) floating-point elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt" (elements in "mt" are unaltered when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + +addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + CASE conv OF + _MM_DOWNCONV_PD_NONE: + IF k[j] + mt[i+63:i] := v[i+63:i] + FI + ESAC +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Downconverts packed 32-bit integer elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt" (elements in "mt" are unaltered when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI32_NONE: + addr[i+31:i] := v[i+31:i] + _MM_DOWNCONV_EPI32_UINT8: + n := j*8 + addr[n+7:n] := Int32ToUInt8(v[i+31:i]) + _MM_DOWNCONV_EPI32_SINT8: + n := j*8 + addr[n+7:n] := Int32ToSInt8(v[i+31:i]) + _MM_DOWNCONV_EPI32_UINT16: + n := j*16 + addr[n+15:n] := Int32ToUInt16(v[i+31:i]) + _MM_DOWNCONV_EPI32_SINT16: + n := j*16 + addr[n+15:n] := Int32ToSInt16(v[i+31:i]) + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Downconverts packed 64-bit integer elements stored in "v" to a smaller type depending on "conv" and stores them in memory location "mt" (elements in "mt" are unaltered when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + +addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: addr[i+63:i] := v[i+63:i] + ESAC + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed single-precision (32-bit) floating-point elements from "v" to memory address "mt" with a no-read hint to the processor. + +addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + addr[i+31:i] := v[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed double-precision (64-bit) floating-point elements from "v" to memory address "mt" with a no-read hint to the processor. + +addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + addr[i+63:i] := v[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed single-precision (32-bit) floating-point elements from "v" to memory address "mt" with a no-read hint and using a weakly-ordered memory consistency model (stores performed with this function are not globally ordered, and subsequent stores from the same thread can be observed before them). + +addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + addr[i+31:i] := v[i+31:i] +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed double-precision (64-bit) floating-point elements from "v" to memory address "mt" with a no-read hint and using a weakly-ordered memory consistency model (stores performed with this function are not globally ordered, and subsequent stores from the same thread can be observed before them). + +addr := MEM[mt] +FOR j := 0 to 7 + i := j*64 + addr[i+63:i] := v[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Performs element-by-element addition of packed 32-bit integers in "v2" and "v3" and the corresponding bit in "k2", storing the result of the addition in "dst" and the result of the carry in "k2_res". + FOR j := 0 to 15 + i := j*32 + k2_res[j] := Carry(v2[i+31:i] + v3[i+31:i] + k2[j]) + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + k2[j] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs element-by-element addition of packed 32-bit integers in "v2" and "v3" and the corresponding bit in "k2", storing the result of the addition in "dst" and the result of the carry in "k2_res" using writemask "k1" (elements are copied from "v2" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k1[j] + k2_res[j] := Carry(v2[i+31:i] + v3[i+31:i] + k2[j]) + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + k2[j] + ELSE + dst[i+31:i] := v2[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + Performs element-by-element addition between packed double-precision (64-bit) floating-point elements in "v2" and "v3" and negates their sum, storing the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := -(v2[i+63:i] + v3[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Performs element-by-element addition between packed double-precision (64-bit) floating-point elements in "v2" and "v3" and negates their sum, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(v2[i+63:i] + v3[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + Performs element-by-element addition between packed single-precision (32-bit) floating-point elements in "v2" and "v3" and negates their sum, storing the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := -(v2[i+31:i] + v3[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Performs element-by-element addition between packed single-precision (32-bit) floating-point elements in "v2" and "v3" and negates their sum, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(v2[i+31:i] + v3[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Performs element by element addition between packed double-precision (64-bit) floating-point elements in "v2" and "v3" and negates the sum, storing the result in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := -(v2[i+63:i] + v3[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Performs element by element addition between packed double-precision (64-bit) floating-point elements in "v2" and "v3" and negates the sum, storing the result in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := -(v2[i+63:i] + v3[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Performs element by element addition between packed single-precision (32-bit) floating-point elements in "v2" and "v3" and negates the sum, storing the result in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := -(v2[i+31:i] + v3[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Performs element by element addition between packed single-precision (32-bit) floating-point elements in "v2" and "v3" and negates the sum, storing the result in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := -(v2[i+31:i] + v3[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + Performs element-by-element subtraction of packed double-precision (64-bit) floating-point elements in "v2" from "v3" storing the results in "dst". + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := v3[i+63:i] - v2[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Performs element-by-element subtraction of packed double-precision (64-bit) floating-point elements in "v2" from "v3" storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := v3[i+63:i] - v2[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + Performs element-by-element subtraction of packed single-precision (32-bit) floating-point elements in "v2" from "v3" storing the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Performs element-by-element subtraction of packed single-precision (32-bit) floating-point elements in "v2" from "v3" storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Performs element-by-element subtraction of packed double-precision (64-bit) floating-point elements in "v2" from "v3" storing the results in "dst". + [round_note] + +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := v3[i+63:i] - v2[i+63:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Performs element-by-element subtraction of packed double-precision (64-bit) floating-point elements in "v2" from "v3" storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := v3[i+63:i] - v2[i+63:i] + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Performs element-by-element subtraction of packed single-precision (32-bit) floating-point elements in "v2" from "v3" storing the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Performs element-by-element subtraction of packed single-precision (32-bit) floating-point elements in "v2" from "v3" storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + Performs element-by-element subtraction of packed 32-bit integer elements in "v2" from "v3" storing the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Performs element-by-element subtraction of packed 32-bit integer elements in "v2" from "v3" storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set) + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + Performs element-by-element addition of packed 32-bit integer elements in "v2" and "v3", storing the resultant carry in "k2_res" (carry flag) and the addition results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + k2_res[j] := Carry(v2[i+31:i] + v3[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs element-by-element addition of packed 32-bit integer elements in "v2" and "v3", storing the resultant carry in "k2_res" (carry flag) and the addition results in "dst" using writemask "k" (elements are copied from "v2" and "k_old" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + ELSE + dst[i+31:i] := v2[i+31:i] + k2_res[j] := k_old[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + Performs an element-by-element addition of packed 32-bit integer elements in "v2" and "v3", storing the results in "dst" and the sign of the sum in "sign" (sign flag). + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + sign[j] := v2[i+31:i] & v3[i+31:i] & 0x80000000 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs an element-by-element addition of packed 32-bit integer elements in "v2" and "v3", storing the results in "dst" and the sign of the sum in "sign" (sign flag). Results are stored using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + sign[j] := v2[i+31:i] & v3[i+31:i] & 0x80000000 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Performs an element-by-element addition of packed single-precision (32-bit) floating-point elements in "v2" and "v3", storing the results in "dst" and the sign of the sum in "sign" (sign flag). + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + sign[j] := v2[i+31:i] & v3[i+31:i] & 0x80000000 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Performs an element-by-element addition of packed single-precision (32-bit) floating-point elements in "v2" and "v3", storing the results in "dst" and the sign of the sum in "sign" (sign flag). Results are stored using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + sign[j] := v2[i+31:i] & v3[i+31:i] & 0x80000000 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Performs an element-by-element addition of packed single-precision (32-bit) floating-point elements in "v2" and "v3", storing the results in "dst" and the sign of the sum in "sign" (sign flag). + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + sign[j] := v2[i+31:i] & v3[i+31:i] & 0x80000000 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + + Performs an element-by-element addition of packed single-precision (32-bit) floating-point elements in "v2" and "v3", storing the results in "dst" and the sign of the sum in "sign" (sign flag). Results are stored using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v2[i+31:i] + v3[i+31:i] + sign[j] := v2[i+31:i] & v3[i+31:i] & 0x80000000 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + Performs element-by-element subtraction of packed 32-bit integer elements in "v3" from "v2", storing the results in "dst" and the nth borrow bit in the nth position of "borrow" (borrow flag). + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] - v3[i+31:i] + borrow[j] := Borrow(v2[i+31:i] - v3[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs element-by-element subtraction of packed 32-bit integer elements in "v3" from "v2", storing the results in "dst" and the nth borrow bit in the nth position of "borrow" (borrow flag). Results are stored using writemask "k" (elements are copied from "v2" and "k_old" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := v2[i+31:i] - v3[i+31:i] + borrow[j] := Borrow(v2[i+31:i] - v3[i+31:i]) + ELSE + dst[i+31:i] := v3[i+31:i] + borrow[j] := k_old[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + Performs element-by-element subtraction of packed 32-bit integer elements in "v2" from "v3", storing the results in "dst" and "v2". The borrowed value from the subtraction difference for the nth element is written to the nth bit of "borrow" (borrow flag). + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] + borrow[j] := Borrow(v3[i+31:i] - v2[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs element-by-element subtraction of packed 32-bit integer elements in "v2" from "v3", storing the results in "dst" and "v2". The borrowed value from the subtraction difference for the nth element is written to the nth bit of "borrow" (borrow flag). Results are written using writemask "k" (elements are copied from "k" to "k_old" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + diff := v3[i+31:i] - v2[i+31:i] + borrow[j] := Borrow(v3[i+31:i] - v2[i+31:i]) + dst[i+31:i] := diff + v2[i+31:i] := diff + ELSE + borrow[j] := k_old[j] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Performs element-by-element three-input subtraction of packed 32-bit integer elements of "v3" as well as the corresponding bit from "k" from "v2". The borrowed value from the subtraction difference for the nth element is written to the nth bit of "borrow" (borrow flag). Results are stored in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] - v3[i+31:i] - k[j] + borrow[j] := Borrow(v2[i+31:i] - v3[i+31:i] - k[j]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs element-by-element three-input subtraction of packed 32-bit integer elements of "v3" as well as the corresponding bit from "k2" from "v2". The borrowed value from the subtraction difference for the nth element is written to the nth bit of "borrow" (borrow flag). Results are stored in "dst" using writemask "k1" (elements are copied from "v2" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k1[j] + dst[i+31:i] := v2[i+31:i] - v3[i+31:i] - k2[j] + borrow[j] := Borrow(v2[i+31:i] - v3[i+31:i] - k2[j]) + ELSE + dst[i+31:i] := v2[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Performs element-by-element three-input subtraction of packed 32-bit integer elements of "v2" as well as the corresponding bit from "k" from "v3". The borrowed value from the subtraction difference for the nth element is written to the nth bit of "borrow" (borrow flag). Results are stored in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] - k[j] + borrow[j] := Borrow(v2[i+31:i] - v3[i+31:i] - k[j]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + + Performs element-by-element three-input subtraction of packed 32-bit integer elements of "v2" as well as the corresponding bit from "k2" from "v3". The borrowed value from the subtraction difference for the nth element is written to the nth bit of "borrow" (borrow flag). Results are stored in "dst" using writemask "k1" (elements are copied from "v2" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k1[j] + dst[i+31:i] := v3[i+31:i] - v2[i+31:i] - k2[j] + borrow[j] := Borrow(v2[i+31:i] - v3[i+31:i] - k2[j]) + ELSE + dst[i+31:i] := v2[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Convert + + + + Performs element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to packed single-precision (32-bit) floating-point elements, storing the results in "dst". Results are written to the lower half of "dst", and the upper half locations are set to '0'. + [round_note] + +FOR j := 0 to 7 + i := j*64 + k := j*32 + dst[k+31:k] := Convert_FP64_To_FP32(v2[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Convert + + + + + + Performs element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to packed single-precision (32-bit) floating-point elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Results are written to the lower half of "dst", and the upper half locations are set to '0'. + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_FP64_To_FP32(v2[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + Performs element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to packed 32-bit unsigned integer elements, storing the results in "dst". Results are written to the lower half of "dst", and the upper half locations are set to '0'. + [round_note] + +FOR j := 0 to 7 + i := j*64 + k := j*32 + dst[k+31:k] := Convert_FP64_To_Int32(v2[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + + Performs element-by-element conversion of packed double-precision (64-bit) floating-point elements in "v2" to packed 32-bit unsigned integer elements, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Results are written to the lower half of "dst", and the upper half locations are set to '0'. + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_FP64_To_Int32(v2[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + Performs element-by-element conversion of packed single-precision (32-bit) floating-point elements in "v2" to packed 32-bit integer elements and performs an optional exponent adjust using "expadj", storing the results in "dst". + [round_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC + dst[i+31:i] := Float32ToInt32(dst[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + Performs element-by-element conversion of packed single-precision (32-bit) floating-point elements in "v2" to packed 32-bit unsigned integer elements and performing an optional exponent adjust using "expadj", storing the results in "dst". + [round_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := v2[i+31:i] + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC + dst[i+31:i] := Float32ToUInt32(dst[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + Performs element-by-element conversion of packed 32-bit unsigned integer elements in "v2" to packed single-precision (32-bit) floating-point elements and performing an optional exponent adjust using "expadj", storing the results in "dst". + [round_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := UInt32ToFloat32(v2[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + + + Performs element-by-element conversion of packed 32-bit unsigned integer elements in "v2" to packed single-precision (32-bit) floating-point elements and performing an optional exponent adjust using "expadj", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Int32ToFloat32(v2[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + Approximates the base-2 exponent of the packed single-precision (32-bit) floating-point elements in "v2" with eight bits for sign and magnitude and 24 bits for the fractional part. Results are stored in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := exp223(v2[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + + + Approximates the base-2 exponent of the packed single-precision (32-bit) floating-point elements in "v2" with eight bits for sign and magnitude and 24 bits for the fractional part. Results are stored in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := exp223(v2[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + Fixes up NaN's from packed double-precision (64-bit) floating-point elements in "v1" and "v2", storing the results in "dst" and storing the quietized NaN's from "v1" in "v3". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := FixupNaNs(v1[i+63:i], v2[i+63:i]) + v3[i+63:i] := QuietizeNaNs(v1[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + + Fixes up NaN's from packed double-precision (64-bit) floating-point elements in "v1" and "v2", storing the results in "dst" using writemask "k" (only elements whose corresponding mask bit is set are used in the computation). Quietized NaN's from "v1" are stored in "v3". + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FixupNaNs(v1[i+63:i], v2[i+63:i]) + v3[i+63:i] := QuietizeNaNs(v1[i+63:i]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + Fixes up NaN's from packed single-precision (32-bit) floating-point elements in "v1" and "v2", storing the results in "dst" and storing the quietized NaN's from "v1" in "v3". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FixupNaNs(v1[i+31:i], v2[i+31:i]) + v3[i+31:i] := QuietizeNaNs(v1[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + + Fixes up NaN's from packed single-precision (32-bit) floating-point elements in "v1" and "v2", storing the results in "dst" using writemask "k" (only elements whose corresponding mask bit is set are used in the computation). Quietized NaN's from "v1" are stored in "v3". + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FixupNaNs(v1[i+31:i], v2[i+31:i]) + v3[i+31:i] := QuietizeNaNs(v1[i+31:i]) + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_EPI32_UINT8: + RETURN ZeroExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_SINT8: + RETURN SignExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_UINT16: + RETURN ZeroExtend32(MEM[addr + 2*offset]) + _MM_UPCONV_EPI32_SINT16: + RETURN SignExtend32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN 4 + _MM_UPCONV_EPI32_UINT8: + RETURN 1 + _MM_UPCONV_EPI32_SINT8: + RETURN 1 + _MM_UPCONV_EPI32_UINT16: + RETURN 2 + _MM_UPCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_EPI32_UINT8: + RETURN ZeroExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_SINT8: + RETURN SignExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_UINT16: + RETURN ZeroExtend32(MEM[addr + 2*offset]) + _MM_UPCONV_EPI32_SINT16: + RETURN SignExtend32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN 4 + _MM_UPCONV_EPI32_UINT8: + RETURN 1 + _MM_UPCONV_EPI32_SINT8: + RETURN 1 + _MM_UPCONV_EPI32_UINT16: + RETURN 2 + _MM_UPCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + Loads the low-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_EPI32_UINT8: + RETURN ZeroExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_SINT8: + RETURN SignExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_UINT16: + RETURN ZeroExtend32(MEM[addr + 2*offset]) + _MM_UPCONV_EPI32_SINT16: + RETURN SignExtend32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN 4 + _MM_UPCONV_EPI32_UINT8: + RETURN 1 + _MM_UPCONV_EPI32_SINT8: + RETURN 1 + _MM_UPCONV_EPI32_UINT16: + RETURN 2 + _MM_UPCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (mt + loadOffset * upSize) % 64 == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Loads the low-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_EPI32_UINT8: + RETURN ZeroExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_SINT8: + RETURN SignExtend32(MEM[addr + offset]) + _MM_UPCONV_EPI32_UINT16: + RETURN ZeroExtend32(MEM[addr + 2*offset]) + _MM_UPCONV_EPI32_SINT16: + RETURN SignExtend32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI32_NONE: + RETURN 4 + _MM_UPCONV_EPI32_UINT8: + RETURN 1 + _MM_UPCONV_EPI32_SINT8: + RETURN 1 + _MM_UPCONV_EPI32_UINT16: + RETURN 2 + _MM_UPCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 15 + IF k[j] + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (mt + loadOffset * upSize) % 64 == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (addr + loadOffset*upSize % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + IF k[j] + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (addr + loadOffset*upSize % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN 4 + _MM_UPCONV_PS_FLOAT16: + RETURN 2 + _MM_UPCONV_PS_UINT8: + RETURN 1 + _MM_UPCONV_PS_SINT8: + RETURN 1 + _MM_UPCONV_PS_UINT16: + RETURN 2 + _MM_UPCONV_PS_SINT16: + RETURN 2 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + Loads the low-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := MEM[mt] +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (mt + loadOffset * upSize) % 64 == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Loads the low-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PS_NONE: + RETURN MEM[addr + 4*offset] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP16_To_FP32(MEM[addr + 4*offset]) + _MM_UPCONV_PS_UINT8: + RETURN Convert_UInt8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_SINT8: + RETURN Convert_Int8_To_FP32(MEM[addr + offset]) + _MM_UPCONV_PS_UINT16: + RETURN Convert_UInt16_To_FP32(MEM[addr + 2*offset]) + _MM_UPCONV_PS_SINT16: + RETURN Convert_Int16_To_FP32(MEM[addr + 2*offset]) + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := MEM[mt] +FOR j := 0 to 15 + IF k[j] + i := j*32 + dst[i+31:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (mt + loadOffset * upSize) % 64 == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed double-precision (64-bit) floating-point values in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize) % 64 == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64, up-converted depending on the value of "conv", and expanded into packed double-precision (64-bit) floating-point values in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +upSize := UPCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*upSize) % 64 == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed double-precision (64-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. + +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (mt + loadOffset * upSize) % 64 == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt, up-converted depending on the value of "conv", and expanded into packed double-precision (64-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". "hint" indicates to the processor whether the loaded data is non-temporal. Elements are copied to "dst" according to element selector "k" (elemenst are skipped when the corresponding mask bit is not set). + +DEFINE UPCONVERT(addr, offset, convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN MEM[addr + 8*offset] + ESAC +} +DEFINE UPCONVERTSIZE(convertTo) { + CASE conv OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +dst[511:0] := src[511:0] +loadOffset := 0 +upSize := UPCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + IF k[j] + i := j*64 + dst[i+63:i] := UPCONVERT(addr, loadOffset, conv) + loadOffset := loadOffset + 1 + IF (mt + loadOffset * upSize) % 64 == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Down-converts and stores packed 32-bit integer elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN element[31:0] + _MM_DOWNCONV_EPI32_UINT8: + RETURN Truncate8(element[31:0]) + _MM_DOWNCONV_EPI32_SINT8: + RETURN Saturate8(element[31:0]) + _MM_DOWNCONV_EPI32_UINT16: + RETURN Truncate16(element[31:0]) + _MM_DOWNCONV_EPI32_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN 4 + _MM_DOWNCONV_EPI32_UINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_SINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_UINT16: + RETURN 2 + _MM_DOWNCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + FI + storeOffset := storeOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Down-converts and stores packed 32-bit integer elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped when the corresonding mask bit is not set). + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN element[31:0] + _MM_DOWNCONV_EPI32_UINT8: + RETURN Truncate8(element[31:0]) + _MM_DOWNCONV_EPI32_SINT8: + RETURN Saturate8(element[31:0]) + _MM_DOWNCONV_EPI32_UINT16: + RETURN Truncate16(element[31:0]) + _MM_DOWNCONV_EPI32_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN 4 + _MM_DOWNCONV_EPI32_UINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_SINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_UINT16: + RETURN 2 + _MM_DOWNCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + FI + storeOffset := storeOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Down-converts and stores packed 32-bit integer elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN element[31:0] + _MM_DOWNCONV_EPI32_UINT8: + RETURN Truncate8(element[31:0]) + _MM_DOWNCONV_EPI32_SINT8: + RETURN Saturate8(element[31:0]) + _MM_DOWNCONV_EPI32_UINT16: + RETURN Truncate16(element[31:0]) + _MM_DOWNCONV_EPI32_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN 4 + _MM_DOWNCONV_EPI32_UINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_SINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_UINT16: + RETURN 2 + _MM_DOWNCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 15 + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Down-converts and stores packed 32-bit integer elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. Elements are written to memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN element[31:0] + _MM_DOWNCONV_EPI32_UINT8: + RETURN Truncate8(element[31:0]) + _MM_DOWNCONV_EPI32_SINT8: + RETURN Saturate8(element[31:0]) + _MM_DOWNCONV_EPI32_UINT16: + RETURN Truncate16(element[31:0]) + _MM_DOWNCONV_EPI32_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_DOWNCONV_EPI32_NONE: + RETURN 4 + _MM_DOWNCONV_EPI32_UINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_SINT8: + RETURN 1 + _MM_DOWNCONV_EPI32_UINT16: + RETURN 2 + _MM_DOWNCONV_EPI32_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 15 + IF k[j] + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Down-converts and stores packed 64-bit integer elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + FI + storeOffset := storeOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Down-converts and stores packed 64-bit integer elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (mt-64)). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped when the corresonding mask bit is not set). + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + FI + storeOffset := storeOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Down-converts and stores packed 64-bit integer elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + i := j*63 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Down-converts and stores packed 64-bit integer elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped whent he corresponding mask bit is not set). + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_EPI64_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + IF k[j] + i := j*63 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Down-converts and stores packed single-precision (32-bit) floating-point elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN element[31:0] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP32_To_FP16(element[31:0]) + _MM_UPCONV_PS_UINT8: + RETURN Truncate8(element[31:0]) + _MM_UPCONV_PS_SINT8: + RETURN Saturate8(element[31:0]) + _MM_UPCONV_PS_UINT16: + RETURN Truncate16(element[31:0]) + _MM_UPCONV_PS_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN 4 + _MM_UPCONV_PS_FLOAT16: + RETURN 2 + _MM_UPCONV_PS_UINT8: + RETURN 1 + _MM_UPCONV_PS_SINT8: + RETURN 1 + _MM_UPCONV_PS_UINT16: + RETURN 2 + _MM_UPCONV_PS_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + FI + storeOffset := storeOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Down-converts and stores packed single-precision (32-bit) floating-point elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN element[31:0] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP32_To_FP16(element[31:0]) + _MM_UPCONV_PS_UINT8: + RETURN Truncate8(element[31:0]) + _MM_UPCONV_PS_SINT8: + RETURN Saturate8(element[31:0]) + _MM_UPCONV_PS_UINT16: + RETURN Truncate16(element[31:0]) + _MM_UPCONV_PS_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN 4 + _MM_UPCONV_PS_FLOAT16: + RETURN 2 + _MM_UPCONV_PS_UINT8: + RETURN 1 + _MM_UPCONV_PS_SINT8: + RETURN 1 + _MM_UPCONV_PS_UINT16: + RETURN 2 + _MM_UPCONV_PS_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + FI + storeOffset := storeOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Down-converts and stores packed single-precision (32-bit) floating-point elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN element[31:0] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP32_To_FP16(element[31:0]) + _MM_UPCONV_PS_UINT8: + RETURN Truncate8(element[31:0]) + _MM_UPCONV_PS_SINT8: + RETURN Saturate8(element[31:0]) + _MM_UPCONV_PS_UINT16: + RETURN Truncate16(element[31:0]) + _MM_UPCONV_PS_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN 4 + _MM_UPCONV_PS_FLOAT16: + RETURN 2 + _MM_UPCONV_PS_UINT8: + RETURN 1 + _MM_UPCONV_PS_SINT8: + RETURN 1 + _MM_UPCONV_PS_UINT16: + RETURN 2 + _MM_UPCONV_PS_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 15 + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Down-converts and stores packed single-precision (32-bit) floating-point elements of "v1" into a byte/word/doubleword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN element[31:0] + _MM_UPCONV_PS_FLOAT16: + RETURN Convert_FP32_To_FP16(element[31:0]) + _MM_UPCONV_PS_UINT8: + RETURN Truncate8(element[31:0]) + _MM_UPCONV_PS_SINT8: + RETURN Saturate8(element[31:0]) + _MM_UPCONV_PS_UINT16: + RETURN Truncate16(element[31:0]) + _MM_UPCONV_PS_SINT16: + RETURN Saturate16(element[31:0]) + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PS_NONE: + RETURN 4 + _MM_UPCONV_PS_FLOAT16: + RETURN 2 + _MM_UPCONV_PS_UINT8: + RETURN 1 + _MM_UPCONV_PS_SINT8: + RETURN 1 + _MM_UPCONV_PS_UINT16: + RETURN 2 + _MM_UPCONV_PS_SINT16: + RETURN 2 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 15 + IF k[j] + i := j*32 + tmp := DOWNCONVERT(v1[i+31:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 4: MEM[storeAddr] := tmp[31:0] + 2: MEM[storeAddr] := tmp[15:0] + 1: MEM[storeAddr] := tmp[7:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Down-converts and stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + FI + storeOffset := storeOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Down-converts and stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +foundNext64BytesBoundary := false +downSize := DOWNCONVERTSIZE(conv) +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == false + IF ((addr + (storeOffset + 1)*downSize) % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + FI + storeOffset := storeOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Down-converts and stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + i := j*63 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Down-converts and stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream according to "conv" at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). "hint" indicates to the processor whether the data is non-temporal. Elements are stored to memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +DEFINE DOWNCONVERT(element, convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN element[63:0] + ESAC +} +DEFINE DOWNCONVERTSIZE(convertTo) { + CASE convertTo OF + _MM_UPCONV_PD_NONE: + RETURN 8 + ESAC +} +storeOffset := 0 +downSize := DOWNCONVERTSIZE(conv) +addr := mt +FOR j := 0 to 7 + IF k[j] + i := j*63 + tmp := DOWNCONVERT(v1[i+63:i], conv) + storeAddr := addr + storeOffset * downSize + CASE downSize OF + 8: MEM[storeAddr] := tmp[63:0] + ESAC + storeOffset := storeOffset + 1 + IF ((addr + storeOffset * downSize) % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Stores 8 packed 64-bit integer elements located in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale". + +FOR j := 0 to 7 + i := j*64 + m := j*32 + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Stores 8 packed 64-bit integer elements located in "a" and stores them in memory locations starting at location "base_addr" at packed 32-bit integer indices stored in "vindex" scaled by "scale" using writemask "k" (elements whose corresponding mask bit is not set are not written to memory). + +FOR j := 0 to 7 + i := j*64 + m := j*32 + IF k[j] + addr := base_addr + SignExtend64(vindex[m+31:m]) * ZeroExtend64(scale) * 8 + MEM[addr+63:addr] := a[i+63:i] + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64 and expands them into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*4 % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64 and expands them into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*4 % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + Loads the low-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt and expanded into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 15 + i := j*32 + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + loadOffset := loadOffset + 1 + IF (mt + loadOffset * 4) % 64 == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + Loads the low-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt and expands them into packed 32-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + loadOffset := loadOffset + 1 + IF (mt + loadOffset * 4) % 64 == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64 and expands them into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*8) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64 and expands them into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*8) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt and expands them into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 7 + i := j*64 + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + loadOffset := loadOffset + 1 + IF (addr + loadOffset*8 % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt and expands them into packed 64-bit integers in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + loadOffset := loadOffset + 1 + IF (addr + loadOffset*8 % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + Loads the high-64-byte-aligned portion of the byte/word/doubleword stream starting at element-aligned address mt-64 and expands them into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*4 % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + Loads the high-64-byte-aligned portion of the doubleword stream starting at element-aligned address mt-64 and expands them into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*4 % 64) == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*32 + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + Loads the low-64-byte-aligned portion of the doubleword stream starting at element-aligned address mt and expanded into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 15 + i := j*32 + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + loadOffset := loadOffset + 1 + IF (mt + loadOffset * 4) % 64 == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + Loads the low-64-byte-aligned portion of the doubleword stream starting at element-aligned address mt and expanded into packed single-precision (32-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted doublewords that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those doublewords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 15 + i := j*32 + IF k[j] + tmp := MEM[addr + loadOffset*4] + dst[i+31:i] := tmp[i+31:i] + loadOffset := loadOffset + 1 + IF (mt + loadOffset * 4) % 64 == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64 and expands them into packed double-precision (64-bit) floating-point values in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*8) % 64 == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + FI + loadOffset := loadOffset + 1 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + Loads the high-64-byte-aligned portion of the quadword stream starting at element-aligned address mt-64 and expands them into packed double-precision (64-bit) floating-point values in "dst". The initial values of "dst" are copied from "src". Only those converted quadwords that occur at or after the first 64-byte-aligned address following (mt-64) are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + dst[511:0] := src[511:0] +loadOffset := 0 +foundNext64BytesBoundary := false +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == false + IF (addr + (loadOffset + 1)*8) % 64 == 0 + foundNext64BytesBoundary := true + FI + ELSE + i := j*64 + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + FI + loadOffset := loadOffset + 1 + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt and expands them into packed double-precision (64-bit) floating-point elements in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 7 + i := j*64 + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + loadOffset := loadOffset + 1 + IF ((addr + 8*loadOffset) % 64) == 0 + BREAK + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + Loads the low-64-byte-aligned portion of the quadword stream starting at element-aligned address mt and expands them into packed double-precision (64-bit) floating-point values in "dst". The initial values of "dst" are copied from "src". Only those converted quad that occur before first 64-byte-aligned address following "mt" are loaded. Elements in the resulting vector that do not map to those quadwords are taken from "src". Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +dst[511:0] := src[511:0] +loadOffset := 0 +addr := mt +FOR j := 0 to 7 + i := j*64 + IF k[j] + tmp := MEM[addr + loadOffset*8] + dst[i+63:i] := tmp[i+63:i] + loadOffset := loadOffset + 1 + IF ((addr + 8*loadOffset) % 64) == 0 + BREAK + FI + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + Stores packed 32-bit integer elements of "v1" into a doubleword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elements of the stream that map at or after the first 64-byte-aligned address following (m5-64)). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*4) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + FI + storeOffset := storeOffset + 1 +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + Stores packed 32-bit integer elements of "v1" into a doubleword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elements of the stream that map at or after the first 64-byte-aligned address following (m5-64)). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*4) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + FI + storeOffset := storeOffset + 1 + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + Stores packed 32-bit integer elements of "v1" into a doubleword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). + +storeOffset := 0 +addr := mt +FOR j := 0 to 15 + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*4) % 64) == 0 + BREAK + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + Stores packed 32-bit integer elements of "v1" into a doubleword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +addr := mt +FOR j := 0 to 15 + IF k[j] + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*4) % 64) == 0 + BREAK + FI + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + Stores packed 64-bit integer elements of "v1" into a quadword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*8) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*64 + MEM[addr + storeOffset*8] := v1[i+63:i] + FI + storeOffset := storeOffset + 1 +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + Stores packed 64-bit integer elements of "v1" into a quadword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*8) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*64 + MEM[addr + storeOffset*8] := v1[i+63:i] + FI + storeOffset := storeOffset + 1 + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + Stores packed 64-bit integer elements of "v1" into a quadword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). + +storeOffset := 0 +addr := mt +FOR j := 0 to 7 + i := j*64 + MEM[addr + storeOffset*8] := v1[i+63:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*8) % 64) == 0 + BREAK + FI +ENDFOR + + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + Stores packed 64-bit integer elements of "v1" into a quadword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +addr := mt +FOR j := 0 to 7 + IF k[j] + i := j*64 + MEM[addr + storeOffset*8] := v1[i+63:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*8) % 64) == 0 + BREAK + FI + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed single-precision (32-bit) floating-point elements of "v1" into a doubleword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 15 + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*4) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + FI + storeOffset := storeOffset + 1 +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + Stores packed single-precision (32-bit) floating-point elements of "v1" into a doubleword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 15 + IF k[j] + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*4) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + FI + storeOffset := storeOffset + 1 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed single-precision (32-bit) floating-point elements of "v1" into a doubleword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). + +storeOffset := 0 +addr := mt +FOR j := 0 to 15 + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*4) % 64) == 0 + BREAK + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + Stores packed single-precision (32-bit) floating-point elements of "v1" into a doubleword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +addr := mt +FOR j := 0 to 15 + IF k[j] + i := j*32 + MEM[addr + storeOffset*4] := v1[i+31:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*4) % 64) == 0 + BREAK + FI + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 7 + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*8) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*64 + MEM[addr + storeOffset*4] := v1[i+63:i] + FI + storeOffset := storeOffset + 1 +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + Stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream at a logically mapped starting address (mt-64), storing the high-64-byte elements of that stream (those elemetns of the stream that map at or after the first 64-byte-aligned address following (m5-64)). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +foundNext64BytesBoundary := 0 +addr := mt-64 +FOR j := 0 to 7 + IF k[j] + IF foundNext64BytesBoundary == 0 + IF ((addr + (storeOffset + 1)*8) % 64) == 0 + foundNext64BytesBoundary := 1 + FI + ELSE + i := j*64 + MEM[addr + storeOffset*4] := v1[i+63:i] + FI + storeOffset := storeOffset + 1 + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). + +storeOffset := 0 +addr := mt +FOR j := 0 to 7 + i := j*64 + MEM[addr + storeOffset*8] := v1[i+63:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*8) % 64) == 0 + BREAK + FI +ENDFOR + + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + Stores packed double-precision (64-bit) floating-point elements of "v1" into a quadword stream at a logically mapped starting address "mt", storing the low-64-byte elements of that stream (those elements of the stream that map before the first 64-byte-aligned address follwing "mt"). Elements are loaded from memory according to element selector "k" (elements are skipped when the corresponding mask bit is not set). + +storeOffset := 0 +addr := mt +FOR j := 0 to 7 + IF k[j] + i := j*64 + MEM[addr + storeOffset*8] := v1[i+63:i] + storeOffset := storeOffset + 1 + IF ((addr + storeOffset*8) % 64) == 0 + BREAK + FI + FI +ENDFOR + + +

immintrin.h

+ + + KNCNI + Bit Manipulation + + + Counts the number of set bits in 32-bit unsigned integer "r1", returning the results in "dst". + dst[31:0] := PopCount(r1[31:0]) + + +

immintrin.h

+ + + KNCNI + Bit Manipulation + + + Counts the number of set bits in 64-bit unsigned integer "r1", returning the results in "dst". + dst[63:0] := PopCount(r1[63:0]) + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Inserts the low byte of mask "k2" into the high byte of "dst", and copies the low byte of "k1" to the low byte of "dst". + +dst[7:0] := k1[7:0] +dst[15:8] := k2[7:0] + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + Performs an element-by-element conversion of elements in packed double-precision (64-bit) floating-point vector "v2" to 32-bit integer elements, storing them in the lower half of "dst". The elements in the upper half of "dst" are set to 0. + [round_note] + +FOR j := 0 to 7 + i := j*64 + k := j*32 + dst[k+31:k] := Convert_FP64_To_Int32(v2[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + + Performs an element-by-element conversion of elements in packed double-precision (64-bit) floating-point vector "v2" to 32-bit integer elements, storing them in the lower half of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). The elements in the upper half of "dst" are set to 0. + [round_note] + +FOR j := 0 to 7 + i := j*64 + l := j*32 + IF k[j] + dst[l+31:l] := Convert_FP64_To_Int32(v2[i+63:i]) + ELSE + dst[l+31:l] := src[l+31:l] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + Integer + KNCNI + Convert + + + + + Performs element-by-element conversion of packed 32-bit integer elements in "v2" to packed single-precision (32-bit) floating-point elements and performing an optional exponent adjust using "expadj", storing the results in "dst". + [round_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := Int32ToFloat32(v2[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a" with absolute error of 2^(-23) and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + + + Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a" with absolute error of 2^(-23) and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + Multiply packed 32-bit integer elements in "a" and "b", add the intermediate result to packed elements in "c" and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Multiply packed 32-bit integer elements in "a" and "b", add the intermediate result to packed elements in "c" and store the results in "dst" using writemask "k" (elements are copied from "a" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Multiply packed 32-bit integer elements in "a" and "b", add the intermediate result to packed elements in "c" and store the results in "dst" using writemask "k" (elements are copied from "c" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) + c[i+31:i] + ELSE + dst[i+31:i] := c[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + Multiply packed 32-bit integer elements in each 4-element set of "a" and by element 1 of the corresponding 4-element set from "b", add the intermediate result to element 0 of the corresponding 4-element set from "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + base := (j & ~0x3) * 32 + scale[31:0] := b[base+63:base+32] + bias[31:0] := b[base+31:base] + dst[i+31:i] := (a[i+31:i] * scale[31:0]) + bias[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Multiply packed 32-bit integer elements in each 4-element set of "a" and by element 1 of the corresponding 4-element set from "b", add the intermediate result to element 0 of the corresponding 4-element set from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + base := (j & ~0x3) * 32 + scale[31:0] := b[base+63:base+32] + bias[31:0] := b[base+31:base] + dst[i+31:i] := (a[i+31:i] * scale[31:0]) + bias[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Multiply packed single-precision (32-bit) floating-point elements in each 4-element set of "a" and by element 1 of the corresponding 4-element set from "b", add the intermediate result to element 0 of the corresponding 4-element set from "b", and store the results in "dst". + [round_note] + +FOR j := 0 to 15 + i := j*32 + base := (j & ~0x3) * 32 + scale[31:0] := b[base+63:base+32] + bias[31:0] := b[base+31:base] + dst[i+31:i] := (a[i+31:i] * scale[31:0]) + bias[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Multiply packed single-precision (32-bit) floating-point elements in each 4-element set of "a" and by element 1 of the corresponding 4-element set from "b", add the intermediate result to element 0 of the corresponding 4-element set from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + base := (j & ~0x3) * 32 + scale[31:0] := b[base+63:base+32] + bias[31:0] := b[base+31:base] + dst[i+31:i] := (a[i+31:i] * scale[31:0]) + bias[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the maximum of the absolute elements of each pair of corresponding elements of packed single-precision (32-bit) floating-point elements in "a" and "b", storing the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FpMax(ABS(a[i+31:i]), ABS(b[i+31:i])) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + + + Determines the maximum of the absolute elements of each pair of corresponding elements of packed single-precision (32-bit) floating-point elements in "a" and "b", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FpMax(ABS(a[i+31:i]), ABS(b[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the maximum of each pair of corresponding elements in packed single-precision (32-bit) floating-point elements in "a" and "b", storing the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FpMax(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + + + Determines the maximum of each pair of corresponding elements of packed single-precision (32-bit) floating-point elements in "a" and "b", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FpMax(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the maximum of each pair of corresponding elements in packed double-precision (64-bit) floating-point elements in "a" and "b", storing the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := FpMax(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + + + Determines the maximum of each pair of corresponding elements of packed double-precision (64-bit) floating-point elements in "a" and "b", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FpMax(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the minimum of each pair of corresponding elements in packed single-precision (32-bit) floating-point elements in "a" and "b", storing the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := FpMin(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + + + Determines the maximum of each pair of corresponding elements of packed single-precision (32-bit) floating-point elements in "a" and "b", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := FpMin(a[i+31:i], b[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the minimum of each pair of corresponding elements in packed double-precision (64-bit) floating-point elements in "a" and "b", storing the results in "dst". + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := FpMin(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + + + Determines the maximum of each pair of corresponding elements of packed double-precision (64-bit) floating-point elements in "a" and "b", storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := FpMin(a[i+63:i], b[i+63:i]) + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + Performs element-by-element multiplication between packed 32-bit integer elements in "a" and "b" and stores the high 32 bits of each result into "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) >> 32 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Performs element-by-element multiplication between packed 32-bit integer elements in "a" and "b" and stores the high 32 bits of each result into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) >> 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + Performs element-by-element multiplication between packed unsigned 32-bit integer elements in "a" and "b" and stores the high 32 bits of each result into "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) >> 32 +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Arithmetic + + + + + + Performs element-by-element multiplication between packed unsigned 32-bit integer elements in "a" and "b" and stores the high 32 bits of each result into "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (a[i+31:i] * b[i+31:i]) >> 32 + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Swizzle + + + + Permutes 128-bit blocks of the packed 32-bit integer vector "a" using constant "imm8". The results are stored in "dst". + +DEFINE SELECT4(src, control) { + CASE control[1:0] OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +FOR j := 0 to 3 + i := j*128 + n := j*2 + dst[i+127:i] := SELECT4(a[511:0], imm8[n+1:n]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Swizzle + + + + + + Permutes 128-bit blocks of the packed 32-bit integer vector "a" using constant "imm8". The results are stored in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE control[1:0] OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp[511:0] := 0 +FOR j := 0 to 3 + i := j*128 + n := j*2 + tmp[i+127:i] := SELECT4(a[511:0], imm8[n+1:n]) +ENDFOR +FOR j := 0 to 15 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + Approximates the reciprocals of packed single-precision (32-bit) floating-point elements in "a" to 23 bits of precision, storing the results in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + + + Approximates the reciprocals of packed single-precision (32-bit) floating-point elements in "a" to 23 bits of precision, storing the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := (1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Convert + + + + + Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value using "expadj" and in the direction of "rounding", and store the results as packed single-precision floating-point elements in "dst". + [round_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ROUND(a[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Convert + + + + + + + Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value using "expadj" and in the direction of "rounding", and store the results as packed single-precision floating-point elements in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ROUND(a[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + Performs element-by-element rounding of packed single-precision (32-bit) floating-point elements in "a" using "expadj" and in the direction of "rounding" and stores results in "dst". + [round_note] + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := ROUND(a[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + + + Performs element-by-element rounding of packed single-precision (32-bit) floating-point elements in "a" using "expadj" and in the direction of "rounding" and stores results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := ROUND(a[i+31:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + Performs element-by-element rounding of packed double-precision (64-bit) floating-point elements in "a" using "expadj" and in the direction of "rounding" and stores results in "dst". + [round_note] + FOR j := 0 to 7 + i := j*64 + dst[i+63:i] := ROUND(a[i+63:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Miscellaneous + + + + + + + Performs element-by-element rounding of packed double-precision (64-bit) floating-point elements in "a" using "expadj" and in the direction of "rounding" and stores results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + [round_note] + FOR j := 0 to 7 + i := j*64 + IF k[j] + dst[i+63:i] := ROUND(a[i+63:i]) + CASE expadj OF + _MM_EXPADJ_NONE: dst[i+31:i] := dst[i+31:i] * (2 << 0) + _MM_EXPADJ_4: dst[i+31:i] := dst[i+31:i] * (2 << 4) + _MM_EXPADJ_5: dst[i+31:i] := dst[i+31:i] * (2 << 5) + _MM_EXPADJ_8: dst[i+31:i] := dst[i+31:i] * (2 << 8) + _MM_EXPADJ_16: dst[i+31:i] := dst[i+31:i] * (2 << 16) + _MM_EXPADJ_24: dst[i+31:i] := dst[i+31:i] * (2 << 24) + _MM_EXPADJ_31: dst[i+31:i] := dst[i+31:i] * (2 << 31) + _MM_EXPADJ_32: dst[i+31:i] := dst[i+31:i] * (2 << 32) + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + Calculates the reciprocal square root of packed single-precision (32-bit) floating-point elements in "a" to 23 bits of accuracy and stores the result in "dst". + FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := Sqrt(1.0 / a[i+31:i]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Elementary Math Functions + + + + + Calculates the reciprocal square root of packed single-precision (32-bit) floating-point elements in "a" to 23 bits of accuracy and stores the result in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := Sqrt(1.0 / a[i+31:i]) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + Scales each single-precision (32-bit) floating-point element in "a" by multiplying it by 2**exponent, where the exponent is the corresponding 32-bit integer element in "b", storing results in "dst". + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] * POW(2.0, FP32(b[i+31:i])) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Scales each single-precision (32-bit) floating-point element in "a" by multiplying it by 2**exponent, where the exponent is the corresponding 32-bit integer element in "b", storing results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * POW(2.0, FP32(b[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + Scales each single-precision (32-bit) floating-point element in "a" by multiplying it by 2**exponent, where the exponent is the corresponding 32-bit integer element in "b", storing results in "dst". Intermediate elements are rounded using "rounding". + [round_note] + +FOR j := 0 to 15 + i := j*32 + dst[i+31:i] := a[i+31:i] * POW(2.0,FP32(b[i+31:i])) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + + Scales each single-precision (32-bit) floating-point element in "a" by multiplying it by 2**exp, where the exp is the corresponding 32-bit integer element in "b", storing results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). Results are rounded using constant "rounding". + [round_note] + +FOR j := 0 to 15 + i := j*32 + IF k[j] + dst[i+31:i] := a[i+31:i] * POW(2.0, FP32(b[i+31:i])) + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + Determines the minimum element of the packed single-precision (32-bit) floating-point elements stored in "a" and stores the result in "dst". + min := a[31:0] +FOR j := 1 to 15 + i := j*32 + dst := FpMin(min, a[i+31:i]) +ENDFOR +dst := min + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the minimum element of the packed single-precision (32-bit) floating-point elements stored in "a" and stores the result in "dst" using writemask "k" (elements are ignored when the corresponding mask bit is not set). + min := a[31:0] +FOR j := 1 to 15 + i := j*32 + IF k[j] + CONTINUE + ELSE + dst := FpMin(min, a[i+31:i]) + FI +ENDFOR +dst := min + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + Determines the minimum element of the packed double-precision (64-bit) floating-point elements stored in "a" and stores the result in "dst". + min := a[63:0] +FOR j := 1 to 7 + i := j*64 + dst := FpMin(min, a[i+63:i]) +ENDFOR +dst := min + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the minimum element of the packed double-precision (64-bit) floating-point elements stored in "a" and stores the result in "dst". Bitmask "k" is used to exclude certain elements (elements are ignored when the corresponding mask bit is not set). + min := a[63:0] +FOR j := 1 to 7 + i := j*64 + IF k[j] + CONTINUE + ELSE + dst := FpMin(min, a[i+63:i]) + FI +ENDFOR +dst := min + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + Determines the maximum element of the packed single-precision (32-bit) floating-point elements stored in "a" and stores the result in "dst". + max := a[31:0] +FOR j := 1 to 15 + i := j*32 + dst := FpMax(max, a[i+31:i]) +ENDFOR +dst := max + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the maximum element of the packed single-precision (32-bit) floating-point elements stored in "a" and stores the result in "dst". Bitmask "k" is used to exclude certain elements (elements are ignored when the corresponding mask bit is not set). + max := a[31:0] +FOR j := 1 to 15 + i := j*32 + IF k[j] + CONTINUE + ELSE + dst := FpMax(max, a[i+31:i]) + FI +ENDFOR +dst := max + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + Determines the maximum element of the packed double-precision (64-bit) floating-point elements stored in "a" and stores the result in "dst". + max := a[63:0] +FOR j := 1 to 7 + i := j*64 + dst := FpMax(max, a[i+63:i]) +ENDFOR +dst := max + +

immintrin.h

+ + + Floating Point + KNCNI + Special Math Functions + + + + Determines the maximum element of the packed double-precision (64-bit) floating-point elements stored in "a" and stores the result in "dst". Bitmask "k" is used to exclude certain elements (elements are ignored when the corresponding mask bit is not set). + max := a[63:0] +FOR j := 1 to 7 + i := j*64 + IF k[j] + CONTINUE + ELSE + dst := FpMax(max, a[i+63:i]) + FI +ENDFOR +dst := max + +

immintrin.h

+ + + KNCNI + Bit Manipulation + + + + Count the number of trailing zero bits in unsigned 32-bit integer "x" starting at bit "a", and return that count in "dst". + +tmp := a +IF tmp < 0 + tmp := 0 +FI +dst := 0 +IF tmp > 31 + dst := 32 +ELSE + DO WHILE ((tmp < 32) AND x[tmp] == 0) + tmp := tmp + 1 + dst := dst + 1 + OD +FI + + +

immintrin.h

+ + + KNCNI + Bit Manipulation + + + + Count the number of trailing zero bits in unsigned 64-bit integer "x" starting at bit "a", and return that count in "dst". + +tmp := a +IF tmp < 0 + tmp := 0 +FI +dst := 0 +IF tmp > 63 + dst := 64 +ELSE + DO WHILE ((tmp < 64) AND x[tmp] == 0) + tmp := tmp + 1 + dst := dst + 1 + OD +FI + + +

immintrin.h

+ + + KNCNI + General Support + + + Stalls a thread without blocking other threads for 32-bit unsigned integer "r1" clock cycles. + BlockThread(r1) + + +

immintrin.h

+ + + KNCNI + General Support + + + Stalls a thread without blocking other threads for 64-bit unsigned integer "r1" clock cycles. + BlockThread(r1) + + +

immintrin.h

+ + + KNCNI + General Support + + + Set performance monitoring filtering mask to 32-bit unsigned integer "r1". + SetPerfMonMask(r1[31:0]) + + +

immintrin.h

+ + + KNCNI + General Support + + + Set performance monitoring filtering mask to 64-bit unsigned integer "r1". + SetPerfMonMask(r1[63:0]) + + +

immintrin.h

+ + + KNCNI + General Support + + + + Evicts the cache line containing the address "ptr" from cache level "level" (can be either 0 or 1). + CacheLineEvict(ptr, level) + + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Performs a bitwise AND operation between NOT of "k2" and "k1", storing the result in "dst". + dst[15:0] := NOT(k2[15:0]) & k1[15:0] + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Moves high byte from "k2" to low byte of "k1", and moves low byte of "k2" to high byte of "k1". + +tmp[7:0] := k2[15:8] +k2[15:8] := k1[7:0] +k1[7:0] := tmp[7:0] +tmp[7:0] := k2[7:0] +k2[7:0] := k1[15:8] +k1[15:8] := tmp[7:0] + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Performs bitwise OR between "k1" and "k2", storing the result in "dst". ZF flag is set if "dst" is 0. + dst[15:0] := k1[15:0] | k2[15:0] +IF dst == 0 + SetZF() +FI + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Performs bitwise OR between "k1" and "k2", storing the result in "dst". CF flag is set if "dst" consists of all 1's. + dst[15:0] := k1[15:0] | k2[15:0] +IF PopCount(dst[15:0]) == 16 + SetCF() +FI + + +

immintrin.h

+ + + KNCNI + Mask + + + Converts bit mask "k1" into an integer value, storing the results in "dst". + +dst := ZeroExtend32(k1) + + +

immintrin.h

+ + + KNCNI + Mask + + + Converts integer "mask" into bitmask, storing the result in "dst". + +dst := mask[15:0] + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Packs masks "k1" and "k2" into the high 32 bits of "dst". The rest of "dst" is set to 0. + +dst[63:48] := k1[15:0] +dst[47:32] := k2[15:0] +dst[31:0] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Packs masks "k1" and "k2" into the low 32 bits of "dst". The rest of "dst" is set to 0. + +dst[31:16] := k1[15:0] +dst[15:0] := k2[15:0] +dst[63:32] := 0 + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Extracts 16-bit value "b" from 64-bit integer "a", storing the result in "dst". + +CASE b[1:0] OF +0: dst[15:0] := a[63:48] +1: dst[15:0] := a[47:32] +2: dst[15:0] := a[31:16] +3: dst[15:0] := a[15:0] +ESAC +dst[MAX:15] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + Multiply packed single-precision (32-bit) floating-point elements in each 4-element set of "a" and by element 1 of the corresponding 4-element set from "b", add the intermediate result to element 0 of the corresponding 4-element set from "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*32 + base := (j & ~0x3) * 32 + scale[31:0] := b[base+63:base+32] + bias[31:0] := b[base+31:base] + dst[i+31:i] := (a[i+31:i] * scale[31:0]) + bias[31:0] +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Arithmetic + + + + + + Multiply packed single-precision (32-bit) floating-point elements in each 4-element set of "a" and by element 1 of the corresponding 4-element set from "b", add the intermediate result to element 0 of the corresponding 4-element set from "b", and store the results in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 15 + i := j*32 + IF k[j] + base := (j & ~0x3) * 32 + scale[31:0] := b[base+63:base+32] + bias[31:0] := b[base+31:base] + dst[i+31:i] := (a[i+31:i] * scale[31:0]) + bias[31:0] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Up-converts 8 single-precision (32-bit) memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 32-bit integer elements and stores them in "dst". "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_EPI32_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_EPI32_UINT8: dst[i+31:i] := ZeroExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_SINT8: dst[i+31:i] := SignExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_UINT16: dst[i+31:i] := ZeroExtend32(MEM[addr+15:addr]) + _MM_UPCONV_EPI32_SINT16: dst[i+31:i] := SignExtend32(MEM[addr+15:addr]) + ESAC +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + + + Up-converts 8 single-precision (32-bit) memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 32-bit integer elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_EPI32_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_EPI32_UINT8: dst[i+31:i] := ZeroExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_SINT8: dst[i+31:i] := SignExtend32(MEM[addr+7:addr]) + _MM_UPCONV_EPI32_UINT16: dst[i+31:i] := ZeroExtend32(MEM[addr+15:addr]) + _MM_UPCONV_EPI32_SINT16: dst[i+31:i] := SignExtend32(MEM[addr+15:addr]) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Up-converts 8 double-precision (64-bit) memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 64-bit integer elements and stores them in "dst". "hint" indicates to the processor whether the load is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_EPI64_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + + + Up-converts 8 double-precision (64-bit) memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 64-bit integer elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the load is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_EPI64_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Up-converts 8 memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to single-precision (32-bit) floating-point elements and stores them in the lower half of "dst". "hint" indicates to the processor whether the load is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_PS_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_PS_FLOAT16: dst[i+31:i] := Convert_FP16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_UINT8: dst[i+31:i] := Convert_UInt8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_SINT8: dst[i+31:i] := Convert_Int8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_UINT16: dst[i+31:i] := Convert_UInt16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_SINT16: dst[i+31:i] := Convert_Int16_To_FP32(MEM[addr+15:addr]) + ESAC +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + + + Up-converts 8 memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to single-precision (32-bit) floating-point elements and stores them in the lower half of "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the load is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_PS_NONE: dst[i+31:i] := MEM[addr+31:addr] + _MM_UPCONV_PS_FLOAT16: dst[i+31:i] := Convert_FP16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_UINT8: dst[i+31:i] := Convert_UInt8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_SINT8: dst[i+31:i] := Convert_Int8_To_FP32(MEM[addr+7:addr]) + _MM_UPCONV_PS_UINT16: dst[i+31:i] := Convert_UInt16_To_FP32(MEM[addr+15:addr]) + _MM_UPCONV_PS_SINT16: dst[i+31:i] := Convert_Int16_To_FP32(MEM[addr+15:addr]) + ESAC + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Up-converts 8 double-precision (64-bit) floating-point elements stored in memory starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 64-bit floating-point elements and stores them in "dst". "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_UPCONV_PD_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + + + Up-converts 8 double-precision (64-bit) floating-point elements stored in memory starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using "conv" to 64-bit floating-point elements and stores them in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_UPCONV_PD_NONE: dst[i+63:i] := MEM[addr+63:addr] + ESAC + ELSE + dst[i+63:i] := src[i+63:i] + FI +ENDFOR +dst[MAX:512] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + + Down-converts 8 packed single-precision (32-bit) floating-point elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_PS_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_PS_FLOAT16: MEM[addr+15:addr] := Convert_FP32_To_FP16(a[i+31:i]) + _MM_DOWNCONV_PS_UINT8: MEM[addr+ 7:addr] := Convert_FP32_To_UInt8(a[i+31:i]) + _MM_DOWNCONV_PS_SINT8: MEM[addr+ 7:addr] := Convert_FP32_To_Int8(a[i+31:i]) + _MM_DOWNCONV_PS_UINT16: MEM[addr+15:addr] := Convert_FP32_To_UInt16(a[i+31:i]) + _MM_DOWNCONV_PS_SINT16: MEM[addr+15:addr] := Convert_FP32_To_Int16(a[i+31:i]) + ESAC +ENDFOR + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + + + Down-converts 8 packed single-precision (32-bit) floating-point elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". Elements are only written when the corresponding mask bit is set in "k"; otherwise, elements are unchanged in memory. "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_PS_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_PS_FLOAT16: MEM[addr+15:addr] := Convert_FP32_To_FP16(a[i+31:i]) + _MM_DOWNCONV_PS_UINT8: MEM[addr+ 7:addr] := Convert_FP32_To_UInt8(a[i+31:i]) + _MM_DOWNCONV_PS_SINT8: MEM[addr+ 7:addr] := Convert_FP32_To_Int8(a[i+31:i]) + _MM_DOWNCONV_PS_UINT16: MEM[addr+15:addr] := Convert_FP32_To_UInt16(a[i+31:i]) + _MM_DOWNCONV_PS_SINT16: MEM[addr+15:addr] := Convert_FP32_To_Int16(a[i+31:i]) + ESAC + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + + Down-converts 8 packed double-precision (64-bit) floating-point elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC +ENDFOR + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + + + Down-converts 8 packed double-precision (64-bit) floating-point elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". Elements are written to memory using writemask "k" (elements are not stored to memory when the corresponding mask bit is not set; the memory location is left unchagned). "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC + FI +ENDFOR + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + + Down-converts the low 8 packed 32-bit integer elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_EPI32_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_EPI32_UINT8: MEM[addr+ 7:addr] := Truncate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT8: MEM[addr+ 7:addr] := Saturate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_UINT16: MEM[addr+15:addr] := Truncate16(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT16: MEM[addr+15:addr] := Saturate16(a[i+31:i]) + ESAC +ENDFOR + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + + + Down-converts the low 8 packed 32-bit integer elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". Elements are written to memory using writemask "k" (elements are only written when the corresponding mask bit is set; otherwise, the memory location is left unchanged). "hint" indicates to the processor whether the data is non-temporal. + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI32_NONE: MEM[addr+31:addr] := a[i+31:i] + _MM_DOWNCONV_EPI32_UINT8: MEM[addr+ 7:addr] := Truncate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT8: MEM[addr+ 7:addr] := Saturate8(a[i+31:i]) + _MM_DOWNCONV_EPI32_UINT16: MEM[addr+15:addr] := Truncate16(a[i+31:i]) + _MM_DOWNCONV_EPI32_SINT16: MEM[addr+15:addr] := Saturate16(a[i+31:i]) + ESAC + FI +ENDFOR + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + + Down-converts 8 packed 64-bit integer elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". "hint" indicates to the processor whether the load is non-temporal. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC +ENDFOR + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + + + Down-converts 8 packed 64-bit integer elements in "a" using "conv" and stores them in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". Only those elements whose corresponding mask bit is set in writemask "k" are written to memory. + +FOR j := 0 to 7 + i := j*64 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + + IF k[j] + CASE conv OF + _MM_DOWNCONV_EPI64_NONE: MEM[addr+63:addr] := a[i+63:i] + ESAC + FI +ENDFOR + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + Permutes 128-bit blocks of the packed single-precision (32-bit) floating-point elements in "a" using constant "imm8". The results are stored in "dst". + +DEFINE SELECT4(src, control) { + CASE control[1:0] OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +FOR j := 0 to 3 + i := j*128 + n := j*2 + dst[i+127:i] := SELECT4(a[511:0], imm8[n+1:n]) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Floating Point + KNCNI + Swizzle + + + + + + Permutes 128-bit blocks of the packed single-precision (32-bit) floating-point elements in "a" using constant "imm8". The results are stored in "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +DEFINE SELECT4(src, control) { + CASE control[1:0] OF + 0: tmp[127:0] := src[127:0] + 1: tmp[127:0] := src[255:128] + 2: tmp[127:0] := src[383:256] + 3: tmp[127:0] := src[511:384] + ESAC + RETURN tmp[127:0] +} +tmp[511:0] := 0 +FOR j := 0 to 3 + i := j*128 + n := j*2 + tmp[i+127:i] := SELECT4(a[511:0], imm8[n+1:n]) +ENDFOR +FOR j := 0 to 15 + IF k[j] + dst[i+31:i] := tmp[i+31:i] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + Loads 8 32-bit integer memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" to "dst". + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Integer + KNCNI + Load + + + + + + + Loads 8 32-bit integer memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + Loads 8 single-precision (32-bit) floating-point memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" to "dst". + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Load + + + + + + + Loads 8 single-precision (32-bit) floating-point memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" to "dst" using writemask "k" (elements are copied from "src" when the corresponding mask bit is not set). + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + dst[i+31:i] := MEM[addr+31:addr] + ELSE + dst[i+31:i] := src[i+31:i] + FI +ENDFOR +dst[MAX:256] := 0 + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + Stores 8 packed single-precision (32-bit) floating-point elements in "a" in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Floating Point + KNCNI + Store + + + + + + + Stores 8 packed single-precision (32-bit) floating-point elements in "a" in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using writemask "k" (elements are only written to memory when the corresponding mask bit is set). + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + Stores 8 packed 32-bit integer elements in "a" in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale". + +FOR j := 0 to 7 + i := j*32 + m := j*64 + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] +ENDFOR + +

immintrin.h

+ + + Integer + KNCNI + Store + + + + + + + Stores 8 packed 32-bit integer elements in "a" in memory locations starting at location "base_addr" at packed 64-bit integer indices stored in "vindex" scaled by "scale" using writemask "k" (elements are only written to memory when the corresponding mask bit is set). + +FOR j := 0 to 7 + i := j*32 + m := j*64 + IF k[j] + addr := base_addr + vindex[m+63:m] * ZeroExtend64(scale) * 8 + MEM[addr+31:addr] := a[i+31:i] + FI +ENDFOR + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Move the high element from "k1" to the low element of "k1", and insert the low element of "k2" into the high element of "k1". + +tmp[7:0] := k1[15:8] +k1[15:8] := k2[7:0] +k1[7:0] := tmp[7:0] + + +

immintrin.h

+ + + Mask + KNCNI + Mask + + + + Insert the low element of "k2" into the high element of "k1". + +k1[15:8] := k2[7:0] + + +

immintrin.h

+ + + Integer + LZCNT + Bit Manipulation + + + Count the number of leading zero bits in unsigned 32-bit integer "a", and return that count in "dst". + +tmp := 31 +dst := 0 +DO WHILE (tmp >= 0 AND a[tmp] == 0) + tmp := tmp - 1 + dst := dst + 1 +OD + + +

immintrin.h

+ + + Integer + LZCNT + Bit Manipulation + + + Count the number of leading zero bits in unsigned 64-bit integer "a", and return that count in "dst". + +tmp := 63 +dst := 0 +DO WHILE (tmp >= 0 AND a[tmp] == 0) + tmp := tmp - 1 + dst := dst + 1 +OD + + +

immintrin.h

+ + + Integer + MMX + Convert + + + Copy 64-bit integer "a" to "dst". + +dst[63:0] := a[63:0] + + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy 64-bit integer "a" to "dst". + +dst[63:0] := a[63:0] + + +

mmintrin.h

+ + + MMX + General Support + + + Empty the MMX state, which marks the x87 FPU registers as available for use by x87 instructions. This instruction must be used at the end of all MMX technology procedures. + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst". + +dst[31:0] := a[31:0] +dst[63:32] := 0 + + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy the lower 32-bit integer in "a" to "dst". + +dst[31:0] := a[31:0] + + +

mmintrin.h

+ + + Integer + MMX + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst". + +dst[7:0] := Saturate8(a[15:0]) +dst[15:8] := Saturate8(a[31:16]) +dst[23:16] := Saturate8(a[47:32]) +dst[31:24] := Saturate8(a[63:48]) +dst[39:32] := Saturate8(b[15:0]) +dst[47:40] := Saturate8(b[31:16]) +dst[55:48] := Saturate8(b[47:32]) +dst[63:56] := Saturate8(b[63:48]) + + +

mmintrin.h

+ + + Integer + MMX + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst". + +dst[15:0] := Saturate16(a[31:0]) +dst[31:16] := Saturate16(a[63:32]) +dst[47:32] := Saturate16(b[31:0]) +dst[63:48] := Saturate16(b[63:32]) + + +

mmintrin.h

+ + + Integer + MMX + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst". + +dst[7:0] := SaturateU8(a[15:0]) +dst[15:8] := SaturateU8(a[31:16]) +dst[23:16] := SaturateU8(a[47:32]) +dst[31:24] := SaturateU8(a[63:48]) +dst[39:32] := SaturateU8(b[15:0]) +dst[47:40] := SaturateU8(b[31:16]) +dst[55:48] := SaturateU8(b[47:32]) +dst[63:56] := SaturateU8(b[63:48]) + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_BYTES(src1[63:0], src2[63:0]) { + dst[7:0] := src1[39:32] + dst[15:8] := src2[39:32] + dst[23:16] := src1[47:40] + dst[31:24] := src2[47:40] + dst[39:32] := src1[55:48] + dst[47:40] := src2[55:48] + dst[55:48] := src1[63:56] + dst[63:56] := src2[63:56] + RETURN dst[63:0] +} +dst[63:0] := INTERLEAVE_HIGH_BYTES(a[63:0], b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_WORDS(src1[63:0], src2[63:0]) { + dst[15:0] := src1[47:32] + dst[31:16] := src2[47:32] + dst[47:32] := src1[63:48] + dst[63:48] := src2[63:48] + RETURN dst[63:0] +} +dst[63:0] := INTERLEAVE_HIGH_WORDS(a[63:0], b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst". + +dst[31:0] := a[63:32] +dst[63:32] := b[63:32] + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_BYTES(src1[63:0], src2[63:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + RETURN dst[63:0] +} +dst[63:0] := INTERLEAVE_BYTES(a[63:0], b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_WORDS(src1[63:0], src2[63:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + RETURN dst[63:0] +} +dst[63:0] := INTERLEAVE_WORDS(a[63:0], b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst". + +dst[31:0] := a[31:0] +dst[63:32] := b[31:0] + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := a[i+7:i] + b[i+7:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := a[i+15:i] + b[i+15:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := a[i+7:i] - b[i+7:i] +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := a[i+15:i] - b[i+15:i] +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Arithmetic + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 3 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 3 + i := j*16 + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[15:0] +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst". + +IF count[63:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] << count[63:0]) +FI + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst". + +IF imm8[7:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] << imm8[7:0]) +FI + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst". + +IF count[63:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] >> count[63:0]) +FI + + +

mmintrin.h

+ + + Floating Point + Integer + MMX + Shift + + + + Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst". + +IF imm8[7:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] >> imm8[7:0]) +FI + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[63:0] := (a[63:0] AND b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise NOT of 64 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst". + +dst[63:0] := ((NOT a[63:0]) AND b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[63:0] := (a[63:0] OR b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[63:0] := (a[63:0] XOR b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := a[i+7:i] + b[i+7:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := a[i+15:i] + b[i+15:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := a[i+7:i] - b[i+7:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := a[i+15:i] - b[i+15:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Arithmetic + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift 64-bit integer "a" left by "count" while shifting in zeros, and store the result in "dst". + +IF count[63:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] << count[63:0]) +FI + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift 64-bit integer "a" left by "imm8" while shifting in zeros, and store the result in "dst". + +IF imm8[7:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] << imm8[7:0]) +FI + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift 64-bit integer "a" right by "count" while shifting in zeros, and store the result in "dst". + +IF count[63:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] >> count[63:0]) +FI + + +

mmintrin.h

+ + + Integer + MMX + Shift + + + + Shift 64-bit integer "a" right by "imm8" while shifting in zeros, and store the result in "dst". + +IF imm8[7:0] > 63 + dst[63:0] := 0 +ELSE + dst[63:0] := ZeroExtend64(a[63:0] >> imm8[7:0]) +FI + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise AND of 64 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[63:0] := (a[63:0] AND b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise OR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[63:0] := (a[63:0] OR b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Logical + + + + Compute the bitwise XOR of 64 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[63:0] := (a[63:0] XOR b[63:0]) + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper element of "dst". + +dst[31:0] := a[31:0] +dst[63:32] := 0 + + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy the lower 32-bit integer in "a" to "dst". + +dst[31:0] := a[31:0] + + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy 64-bit integer "a" to "dst". + +dst[63:0] := a[63:0] + + +

mmintrin.h

+ + + Integer + MMX + Convert + + + Copy 64-bit integer "a" to "dst". + +dst[63:0] := a[63:0] + + +

mmintrin.h

+ + + Integer + MMX + Set + + + Return vector of type __m64 with all elements set to zero. + +dst[MAX:0] := 0 + + +

mmintrin.h

+ + + Integer + MMX + Set + + + + Set packed 32-bit integers in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 + +

mmintrin.h

+ + + Integer + MMX + Set + + + + + + Set packed 16-bit integers in "dst" with the supplied values. + +dst[15:0] := e0 +dst[31:16] := e1 +dst[47:32] := e2 +dst[63:48] := e3 + +

mmintrin.h

+ + + Integer + MMX + Set + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values. + +dst[7:0] := e0 +dst[15:8] := e1 +dst[23:16] := e2 +dst[31:24] := e3 +dst[39:32] := e4 +dst[47:40] := e5 +dst[55:48] := e6 +dst[63:56] := e7 + +

mmintrin.h

+ + + Integer + MMX + Set + + + Broadcast 32-bit integer "a" to all elements of "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR + +

mmintrin.h

+ + + Integer + MMX + Set + + + Broadcast 16-bit integer "a" to all all elements of "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR + +

mmintrin.h

+ + + Integer + MMX + Set + + + Broadcast 8-bit integer "a" to all elements of "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR + +

mmintrin.h

+ + + Integer + MMX + Set + + + + Set packed 32-bit integers in "dst" with the supplied values in reverse order. + +dst[31:0] := e1 +dst[63:32] := e0 + +

mmintrin.h

+ + + Integer + MMX + Set + + + + + + Set packed 16-bit integers in "dst" with the supplied values in reverse order. + +dst[15:0] := e3 +dst[31:16] := e2 +dst[47:32] := e1 +dst[63:48] := e0 + +

mmintrin.h

+ + + Integer + MMX + Set + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values in reverse order. + +dst[7:0] := e7 +dst[15:8] := e6 +dst[23:16] := e5 +dst[31:24] := e4 +dst[39:32] := e3 +dst[47:40] := e2 +dst[55:48] := e1 +dst[63:56] := e0 + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst". + +dst[31:0] := a[63:32] +dst[63:32] := b[63:32] + + +

mmintrin.h

+ + + Integer + MMX + Swizzle + + + + Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst". + +dst[31:0] := a[31:0] +dst[63:32] := b[31:0] + + +

mmintrin.h

+ + + MONITOR + General Support + + + + + Arm address monitoring hardware using the address specified in "p". A store to an address within the specified address range triggers the monitoring hardware. Specify optional extensions in "extensions", and optional hints in "hints". + +

pmmintrin.h

+ + + MONITOR + General Support + + + + Hint to the processor that it can enter an implementation-dependent-optimized state while waiting for an event or store operation to the address range specified by MONITOR. + +

pmmintrin.h

+ + + MOVBE + Load + + + Load 16 bits from memory, perform a byte swap operation, and store the result in "dst". + +FOR j := 0 to 1 + i := j*8 + dst[i+7:i] := MEM[ptr+15-i:ptr+8-i] +ENDFOR + + +

immintrin.h

+ + + MOVBE + Load + + + Load 32 bits from memory, perform a byte swap operation, and store the result in "dst". + +FOR j := 0 to 3 + i := j*8 + dst[i+7:i] := MEM[ptr+31-i:ptr+24-i] +ENDFOR + + +

immintrin.h

+ + + MOVBE + Load + + + Load 64 bits from memory, perform a byte swap operation, and store the result in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := MEM[ptr+63-i:ptr+56-i] +ENDFOR + + +

immintrin.h

+ + + MOVBE + Store + + + + Perform a bit swap operation of the 16 bits in "data", and store the results to memory. + +FOR j := 0 to 1 + i := j*8 + MEM[ptr+i+7:ptr+i] := data[15-i:8-i] +ENDFOR + + +

immintrin.h

+ + + MOVBE + Store + + + + Perform a bit swap operation of the 32 bits in "data", and store the results to memory. + +addr := MEM[ptr] +FOR j := 0 to 3 + i := j*8 + MEM[ptr+i+7:ptr+i] := data[31-i:24-i] +ENDFOR + + +

immintrin.h

+ + + MOVBE + Store + + + + Perform a bit swap operation of the 64 bits in "data", and store the results to memory. + +addr := MEM[ptr] +FOR j := 0 to 7 + i := j*8 + MEM[ptr+i+7:ptr+i] := data[63-i:56-i] +ENDFOR + + +

immintrin.h

+ + + MOVDIR64B + Store + + + + Move 64-byte (512-bit) value using direct store from source memory address "src" to destination memory address "dst". + +MEM[dst+511:dst] := MEM[src+511:src] + + +

immintrin.h

+ + + MOVDIRI + Store + + + + Store 64-bit integer from "val" into memory using direct store. + +MEM[dst+63:dst] := val[63:0] + + +

immintrin.h

+ + + MOVDIRI + Store + + + + Store 32-bit integer from "val" into memory using direct store. + +MEM[dst+31:dst] := val[31:0] + + +

immintrin.h

+ + + MPX + Miscellaneous + + + + Make a pointer with the value of "srcmem" and bounds set to ["srcmem", "srcmem" + "size" - 1], and store the result in "dst". + dst := srcmem +dst.LB := srcmem.LB +dst.UB := srcmem + size - 1 + + +

immintrin.h

+ + + MPX + Miscellaneous + + + + + Narrow the bounds for pointer "q" to the intersection of the bounds of "r" and the bounds ["q", "q" + "size" - 1], and store the result in "dst". + dst := q +IF r.LB > (q + size - 1) OR r.UB < q + dst.LB := 1 + dst.UB := 0 +ELSE + dst.LB := MAX(r.LB, q) + dst.UB := MIN(r.UB, (q + size - 1)) +FI + +

immintrin.h

+ + + MPX + Miscellaneous + + + + Make a pointer with the value of "q" and bounds set to the bounds of "r" (e.g. copy the bounds of "r" to pointer "q"), and store the result in "dst". + dst := q +dst.LB := r.LB +dst.UB := r.UB + +

immintrin.h

+ + + MPX + Miscellaneous + + + Make a pointer with the value of "q" and open bounds, which allow the pointer to access the entire virtual address space, and store the result in "dst". + dst := q +dst.LB := 0 +dst.UB := 0 + +

immintrin.h

+ + + MPX + Miscellaneous + + + + Stores the bounds of "ptr_val" pointer in memory at address "ptr_addr". + MEM[ptr_addr].LB := ptr_val.LB +MEM[ptr_addr].UB := ptr_val.UB + + +

immintrin.h

+ + + MPX + Miscellaneous + + + Checks if "q" is within its lower bound, and throws a #BR if not. + IF q < q.LB + #BR +FI + + +

immintrin.h

+ + + MPX + Miscellaneous + + + Checks if "q" is within its upper bound, and throws a #BR if not. + IF q > q.UB + #BR +FI + + + +

immintrin.h

+ + + MPX + Miscellaneous + + + + Checks if ["q", "q" + "size" - 1] is within the lower and upper bounds of "q" and throws a #BR if not. + IF (q + size - 1) < q.LB OR (q + size - 1) > q.UB + #BR +FI + + + +

immintrin.h

+ + + MPX + Miscellaneous + + + Return the lower bound of "q". + dst := q.LB + +

immintrin.h

+ + + MPX + Miscellaneous + + + Return the upper bound of "q". + dst := q.UB + +

immintrin.h

+ + + Integer + Bit Manipulation + + + Set "dst" to the index of the lowest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined. + +tmp := 0 +IF a == 0 + // dst is undefined +ELSE + DO WHILE ((tmp < 32) AND a[tmp] == 0) + tmp := tmp + 1 + OD +FI +dst := tmp + + +

immintrin.h

+ + + Integer + Bit Manipulation + + + Set "dst" to the index of the highest set bit in 32-bit integer "a". If no bits are set in "a" then "dst" is undefined. + +tmp := 31 +IF a == 0 + // dst is undefined +ELSE + DO WHILE ((tmp > 0) AND a[tmp] == 0) + tmp := tmp - 1 + OD +FI +dst := tmp + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1. + +tmp := 0 +IF a == 0 + // MEM[index+31:index] is undefined + dst := 0 +ELSE + DO WHILE ((tmp < 32) AND a[tmp] == 0) + tmp := tmp + 1 + OD + MEM[index+31:index] := tmp + dst := (tmp == 31) ? 0 : 1 +FI + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1. + +tmp := 31 +IF a == 0 + // MEM[index+31:index] is undefined + dst := 0 +ELSE + DO WHILE ((tmp > 0) AND a[tmp] == 0) + tmp := tmp - 1 + OD + MEM[index+31:index] := tmp + dst := (tmp == 0) ? 0 : 1 +FI + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Set "index" to the index of the lowest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1. + +tmp := 0 +IF a == 0 + // MEM[index+31:index] is undefined + dst := 0 +ELSE + DO WHILE ((tmp < 64) AND a[tmp] == 0) + tmp := tmp + 1 + OD + MEM[index+31:index] := tmp + dst := (tmp == 63) ? 0 : 1 +FI + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Set "index" to the index of the highest set bit in 32-bit integer "mask". If no bits are set in "a", then "index" is undefined and "dst" is set to 0, otherwise "dst" is set to 1. + +tmp := 63 +IF a == 0 + // MEM[index+31:index] is undefined + dst := 0 +ELSE + DO WHILE ((tmp > 0) AND a[tmp] == 0) + tmp := tmp - 1 + OD + MEM[index+31:index] := tmp + dst := (tmp == 0) ? 0 : 1 +FI + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 32-bit integer "a". + +addr := a + ZeroExtend64(b) +dst[0] := MEM[addr] + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 32-bit integer "a", and set that bit to its complement. + +addr := a + ZeroExtend64(b) +dst[0] := MEM[addr] +MEM[addr] := ~dst[0] + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 32-bit integer "a", and set that bit to zero. + +addr := a + ZeroExtend64(b) +dst[0] := MEM[addr] +MEM[addr] := 0 + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 32-bit integer "a", and set that bit to one. + +addr := a + ZeroExtend64(b) +dst[0] := MEM[addr] +MEM[addr] := 1 + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 64-bit integer "a". + +addr := a + b +dst[0] := MEM[addr] + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 64-bit integer "a", and set that bit to its complement. + +addr := a + b +dst[0] := MEM[addr] +MEM[addr] := ~dst[0] + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 64-bit integer "a", and set that bit to zero. + +addr := a + b +dst[0] := MEM[addr] +MEM[addr] := 0 + + +

immintrin.h

+ + + Integer + Flag + Bit Manipulation + + + + Return the bit at index "b" of 64-bit integer "a", and set that bit to one. + +addr := a + b +dst[0] := MEM[addr] +MEM[addr] := 1 + + +

immintrin.h

+ + + Integer + Bit Manipulation + + + Reverse the byte order of 32-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values. + +dst[7:0] := a[31:24] +dst[15:8] := a[23:16] +dst[23:16] := a[15:8] +dst[31:24] := a[7:0] + + +

immintrin.h

+ + + Integer + Bit Manipulation + + + Reverse the byte order of 64-bit integer "a", and store the result in "dst". This intrinsic is provided for conversion between little and big endian values. + +dst[7:0] := a[63:56] +dst[15:8] := a[55:48] +dst[23:16] := a[47:40] +dst[31:24] := a[39:32] +dst[39:32] := a[31:24] +dst[47:40] := a[23:16] +dst[55:48] := a[15:8] +dst[63:56] := a[7:0] + + +

immintrin.h

+ + + Floating Point + Integer + Cast + + + Cast from type float to type unsigned __int32 without conversion. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + Cast + + + Cast from type double to type unsigned __int64 without conversion. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + Cast + + + Cast from type unsigned __int32 to type float without conversion. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Floating Point + Integer + Cast + + + Cast from type unsigned __int64 to type double without conversion. + This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned long integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst". + // size := 32 or 64 +dst := a +count := shift AND (size - 1) +DO WHILE (count > 0) + tmp[0] := dst[size - 1] + dst := (dst << 1) OR tmp[0] + count := count - 1 +OD + + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned long integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst". + // size := 32 or 64 +dst := a +count := shift AND (size - 1) +DO WHILE (count > 0) + tmp[size - 1] := dst[0] + dst := (dst >> 1) OR tmp[size - 1] + count := count - 1 +OD + + +

immintrin.h

+ + + General Support + + + Treat the processor-specific feature(s) specified in "a" as available. Multiple features may be OR'd together. See the valid feature flags below: + +_FEATURE_GENERIC_IA32 +_FEATURE_FPU +_FEATURE_CMOV +_FEATURE_MMX +_FEATURE_FXSAVE +_FEATURE_SSE +_FEATURE_SSE2 +_FEATURE_SSE3 +_FEATURE_SSSE3 +_FEATURE_SSE4_1 +_FEATURE_SSE4_2 +_FEATURE_MOVBE +_FEATURE_POPCNT +_FEATURE_PCLMULQDQ +_FEATURE_AES +_FEATURE_F16C +_FEATURE_AVX +_FEATURE_RDRND +_FEATURE_FMA +_FEATURE_BMI +_FEATURE_LZCNT +_FEATURE_HLE +_FEATURE_RTM +_FEATURE_AVX2 +_FEATURE_KNCNI +_FEATURE_AVX512F +_FEATURE_ADX +_FEATURE_RDSEED +_FEATURE_AVX512ER +_FEATURE_AVX512PF +_FEATURE_AVX512CD +_FEATURE_SHA +_FEATURE_MPX +_FEATURE_AVX512BW +_FEATURE_AVX512VL +_FEATURE_AVX512VBMI +_FEATURE_AVX512_4FMAPS +_FEATURE_AVX512_4VNNIW +_FEATURE_AVX512_VPOPCNTDQ +_FEATURE_AVX512_BITALG +_FEATURE_AVX512_VBMI2 +_FEATURE_GFNI +_FEATURE_VAES +_FEATURE_VPCLMULQDQ +_FEATURE_AVX512_VNNI +_FEATURE_CLWB +_FEATURE_RDPID +_FEATURE_IBT +_FEATURE_SHSTK +_FEATURE_SGX +_FEATURE_WBNOINVD +_FEATURE_PCONFIG +_FEATURE_AXV512_4VNNIB +_FEATURE_AXV512_4FMAPH +_FEATURE_AXV512_BITALG2 +_FEATURE_AXV512_VP2INTERSECT + +

immintrin.h

+ + + General Support + + + Dynamically query the processor to determine if the processor-specific feature(s) specified in "a" are available, and return true or false (1 or 0) if the set of features is available. Multiple features may be OR'd together. This intrinsic does not check the processor vendor. See the valid feature flags below: + +_FEATURE_GENERIC_IA32 +_FEATURE_FPU +_FEATURE_CMOV +_FEATURE_MMX +_FEATURE_FXSAVE +_FEATURE_SSE +_FEATURE_SSE2 +_FEATURE_SSE3 +_FEATURE_SSSE3 +_FEATURE_SSE4_1 +_FEATURE_SSE4_2 +_FEATURE_MOVBE +_FEATURE_POPCNT +_FEATURE_PCLMULQDQ +_FEATURE_AES +_FEATURE_F16C +_FEATURE_AVX +_FEATURE_RDRND +_FEATURE_FMA +_FEATURE_BMI +_FEATURE_LZCNT +_FEATURE_HLE +_FEATURE_RTM +_FEATURE_AVX2 +_FEATURE_KNCNI +_FEATURE_AVX512F +_FEATURE_ADX +_FEATURE_RDSEED +_FEATURE_AVX512ER +_FEATURE_AVX512PF +_FEATURE_AVX512CD +_FEATURE_SHA +_FEATURE_MPX +_FEATURE_AVX512BW +_FEATURE_AVX512VL +_FEATURE_AVX512VBMI +_FEATURE_AVX512_4FMAPS +_FEATURE_AVX512_4VNNIW +_FEATURE_AVX512_VPOPCNTDQ +_FEATURE_AVX512_BITALG +_FEATURE_AVX512_VBMI2 +_FEATURE_GFNI +_FEATURE_VAES +_FEATURE_VPCLMULQDQ +_FEATURE_AVX512_VNNI +_FEATURE_CLWB +_FEATURE_RDPID +_FEATURE_IBT +_FEATURE_SHSTK +_FEATURE_SGX +_FEATURE_WBNOINVD +_FEATURE_PCONFIG +_FEATURE_AXV512_4VNNIB +_FEATURE_AXV512_4FMAPH +_FEATURE_AXV512_BITALG2 +_FEATURE_AXV512_VP2INTERSECT + +

immintrin.h

+ + + General Support + + + Read the Performance Monitor Counter (PMC) specified by "a", and store up to 64-bits in "dst". The width of performance counters is implementation specific. + dst[63:0] := ReadPMC(a) + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned 32-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst". + +dst := a +count := shift AND 31 +DO WHILE (count > 0) + tmp[0] := dst[31] + dst := (dst << 1) OR tmp[0] + count := count - 1 +OD + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned 32-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst". + +dst := a +count := shift AND 31 +DO WHILE (count > 0) + tmp[31] := dst[0] + dst := (dst >> 1) OR tmp + count := count - 1 +OD + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned 16-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst". + +dst := a +count := shift AND 15 +DO WHILE (count > 0) + tmp[0] := dst[15] + dst := (dst << 1) OR tmp[0] + count := count - 1 +OD + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned 16-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst". + +dst := a +count := shift AND 15 +DO WHILE (count > 0) + tmp[15] := dst[0] + dst := (dst >> 1) OR tmp + count := count - 1 +OD + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned 64-bit integer "a" left by the number of bits specified in "shift", rotating the most-significant bit to the least-significant bit location, and store the unsigned result in "dst". + +dst := a +count := shift AND 63 +DO WHILE (count > 0) + tmp[0] := dst[63] + dst := (dst << 1) OR tmp[0] + count := count - 1 +OD + + +

immintrin.h

+ + + Integer + Shift + + + + Shift the bits of unsigned 64-bit integer "a" right by the number of bits specified in "shift", rotating the least-significant bit to the most-significant bit location, and store the unsigned result in "dst". + +dst := a +count := shift AND 63 +DO WHILE (count > 0) + tmp[63] := dst[0] + dst := (dst >> 1) OR tmp[63] + count := count - 1 +OD + + +

immintrin.h

+ + + Integer + Flag + Arithmetic + + + + + + Add unsigned 32-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag). + +tmp[32:0] := a[31:0] + b[31:0] + (c_in > 0 ? 1 : 0) +MEM[out+31:out] := tmp[31:0] +dst[0] := tmp[32] +dst[7:1] := 0 + + +

immintrin.h

+ + + Integer + Flag + Arithmetic + + + + + + Add unsigned 64-bit integers "a" and "b" with unsigned 8-bit carry-in "c_in" (carry flag), and store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag). + +tmp[64:0] := a[63:0] + b[63:0] + (c_in > 0 ? 1 : 0) +MEM[out+63:out] := tmp[63:0] +dst[0] := tmp[64] +dst[7:1] := 0 + + +

immintrin.h

+ + + Integer + Flag + Arithmetic + + + + + + Add unsigned 8-bit borrow "c_in" (carry flag) to unsigned 32-bit integer "b", and subtract the result from unsigned 32-bit integer "a". Store the unsigned 32-bit result in "out", and the carry-out in "dst" (carry or overflow flag). + +tmp[32:0] := a[31:0] - (b[31:0] + (c_in > 0 ? 1 : 0)) +MEM[out+31:out] := tmp[31:0] +dst[0] := tmp[32] +dst[7:1] := 0 + + +

immintrin.h

+ + + Integer + Flag + Arithmetic + + + + + + Add unsigned 8-bit borrow "c_in" (carry flag) to unsigned 64-bit integer "b", and subtract the result from unsigned 64-bit integer "a". Store the unsigned 64-bit result in "out", and the carry-out in "dst" (carry or overflow flag). + +tmp[64:0] := a[63:0] - (b[63:0] + (c_in > 0 ? 1 : 0)) +MEM[out+63:out] := tmp[63:0] +dst[0] := tmp[64] +dst[7:1] := 0 + + +

immintrin.h

+ + + Miscellaneous + + + Insert the 32-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled. + +

immintrin.h

+ + + Miscellaneous + + + Insert the 64-bit data from "a" into a Processor Trace stream via a PTW packet. The PTW packet will be inserted if tracing is currently enabled and ptwrite is currently enabled. The current IP will also be inserted via a FUP packet if FUPonPTW is enabled. + +

immintrin.h

+ + + Miscellaneous + + + + Invoke the Intel SGX enclave user (non-privilege) leaf function specified by "a", and return the error code. The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx. + +

immintrin.h

+ + + Miscellaneous + + + + Invoke the Intel SGX enclave system (privileged) leaf function specified by "a", and return the error code. The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx. + +

immintrin.h

+ + + Miscellaneous + + + + Invoke the Intel SGX enclave virtualized (VMM) leaf function specified by "a", and return the error code. The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to ebx, ecx, and edx. + +

immintrin.h

+ + + Miscellaneous + + + Write back and flush internal caches. + Initiate writing-back and flushing of external + caches. + +

immintrin.h

+ + + Floating Point + Convert + + + Convert the half-precision (16-bit) floating-point value "a" to a single-precision (32-bit) floating-point value, and store the result in "dst". + +dst[31:0] := Convert_FP16_To_FP32(a[15:0]) + +

emmintrin.h

+ + + Floating Point + Convert + + + + Convert the single-precision (32-bit) floating-point value "a" to a half-precision (16-bit) floating-point value, and store the result in "dst". + [round_note] + +dst[15:0] := Convert_FP32_To_FP16(a[31:0]) + +

emmintrin.h

+ + + Integer + PCLMULQDQ + Application-Targeted + + + + + Perform a carry-less multiplication of two 64-bit integers, selected from "a" and "b" according to "imm8", and store the results in "dst". + +IF (imm8[0] == 0) + TEMP1 := a[63:0] +ELSE + TEMP1 := a[127:64] +FI +IF (imm8[4] == 0) + TEMP2 := b[63:0] +ELSE + TEMP2 := b[127:64] +FI +FOR i := 0 to 63 + TEMP[i] := (TEMP1[0] and TEMP2[i]) + FOR j := 1 to i + TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j]) + ENDFOR + dst[i] := TEMP[i] +ENDFOR +FOR i := 64 to 127 + TEMP[i] := 0 + FOR j := (i - 63) to 63 + TEMP[i] := TEMP[i] XOR (TEMP1[j] AND TEMP2[i-j]) + ENDFOR + dst[i] := TEMP[i] +ENDFOR +dst[127] := 0 + + +

wmmintrin.h

+ + + PCONFIG + Miscellaneous + + + + Invoke the PCONFIG leaf function specified by "a". The "__data" array contains 3 32-bit elements that may act as input, output, or be unused, depending on the semantics of the specified leaf function; these correspond to rbx, rcx, and rdx. May return the value in eax, depending on the semantics of the specified leaf function. + +

immintrin.h

+ + + Integer + Flag + POPCNT + Bit Manipulation + + + Count the number of bits set to 1 in unsigned 32-bit integer "a", and return that count in "dst". + +dst := 0 +FOR i := 0 to 31 + IF a[i] + dst := dst + 1 + FI +ENDFOR + + +

nmmintrin.h

+ + + Integer + Flag + POPCNT + Bit Manipulation + + + Count the number of bits set to 1 in unsigned 64-bit integer "a", and return that count in "dst". + +dst := 0 +FOR i := 0 to 63 + IF a[i] + dst := dst + 1 + FI +ENDFOR + + +

nmmintrin.h

+ + + Integer + Flag + POPCNT + Bit Manipulation + + + Count the number of bits set to 1 in 32-bit integer "a", and return that count in "dst". + +dst := 0 +FOR i := 0 to 31 + IF a[i] + dst := dst + 1 + FI +ENDFOR + + +

immintrin.h

+ + + Integer + Flag + POPCNT + Bit Manipulation + + + Count the number of bits set to 1 in 64-bit integer "a", and return that count in "dst". + +dst := 0 +FOR i := 0 to 63 + IF a[i] + dst := dst + 1 + FI +ENDFOR + + +

immintrin.h

+ + + PREFETCHWT1 + General Support + + + + Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i". + +

xmmintrin.h

+ + + RDPID + General Support + + + Copy the IA32_TSC_AUX MSR (signature value) into "dst". + dst[31:0] := IA32_TSC_AUX[31:0] + + +

immintrin.h

+ + + Integer + Flag + RDRAND + Random + + + Read a hardware generated 16-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise. + IF HW_RND_GEN.ready == 1 + val[15:0] := HW_RND_GEN.data + dst := 1 +ELSE + val[15:0] := 0 + dst := 0 +FI + + +

immintrin.h

+ + + Integer + Flag + RDRAND + Random + + + Read a hardware generated 32-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise. + IF HW_RND_GEN.ready == 1 + val[31:0] := HW_RND_GEN.data + dst := 1 +ELSE + val[31:0] := 0 + dst := 0 +FI + + +

immintrin.h

+ + + Integer + Flag + RDRAND + Random + + + Read a hardware generated 64-bit random value and store the result in "val". Return 1 if a random value was generated, and 0 otherwise. + IF HW_RND_GEN.ready == 1 + val[63:0] := HW_RND_GEN.data + dst := 1 +ELSE + val[63:0] := 0 + dst := 0 +FI + + +

immintrin.h

+ + + Flag + RDSEED + Random + + + Read a 16-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise. + IF HW_NRND_GEN.ready == 1 + val[15:0] := HW_NRND_GEN.data + dst := 1 +ELSE + val[15:0] := 0 + dst := 0 +FI + + +

immintrin.h

+ + + Flag + RDSEED + Random + + + Read a 32-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise. + IF HW_NRND_GEN.ready == 1 + val[31:0] := HW_NRND_GEN.data + dst := 1 +ELSE + val[31:0] := 0 + dst := 0 +FI + + +

immintrin.h

+ + + Flag + RDSEED + Random + + + Read a 64-bit NIST SP800-90B and SP800-90C compliant random value and store in "val". Return 1 if a random value was generated, and 0 otherwise. + IF HW_NRND_GEN.ready == 1 + val[63:0] := HW_NRND_GEN.data + dst := 1 +ELSE + val[63:0] := 0 + dst := 0 +FI + + +

immintrin.h

+ + + RDTSCP + General Support + + + Copy the current 64-bit value of the processor's time-stamp counter into "dst", and store the IA32_TSC_AUX MSR (signature value) into memory at "mem_addr". + dst[63:0] := TimeStampCounter +MEM[mem_addr+31:mem_addr] := IA32_TSC_AUX[31:0] + + +

immintrin.h

+ + + RTM + General Support + + + Force an RTM abort. The EAX register is updated to reflect an XABORT instruction caused the abort, and the "imm8" parameter will be provided in bits [31:24] of EAX. + Following an RTM abort, the logical processor resumes execution at the fallback address computed through the outermost XBEGIN instruction. + IF RTM_ACTIVE == 0 + // nop +ELSE + // restore architectural register state + // discard memory updates performed in transaction + // update EAX with status and imm8 value + eax[31:24] := imm8[7:0] + RTM_NEST_COUNT := 0 + RTM_ACTIVE := 0 + IF _64_BIT_MODE + RIP := fallbackRIP + ELSE + EIP := fallbackEIP + FI +FI + + +

immintrin.h

+ + + RTM + General Support + + + Specify the start of an RTM code region. + If the logical processor was not already in transactional execution, then this call causes the logical processor to transition into transactional execution. + On an RTM abort, the logical processor discards all architectural register and memory updates performed during the RTM execution, restores architectural state, and starts execution beginning at the fallback address computed from the outermost XBEGIN instruction. Return status of ~0 (0xFFFF) if continuing inside transaction; all other codes are aborts. + IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT + RTM_NEST_COUNT := RTM_NEST_COUNT + 1 + IF RTM_NEST_COUNT == 1 + IF _64_BIT_MODE + fallbackRIP := RIP + ELSE IF _32_BIT_MODE + fallbackEIP := EIP + FI + + RTM_ACTIVE := 1 + // enter RTM execution, record register state, start tracking memory state + FI +ELSE + // RTM abort (see _xabort) +FI + + +

immintrin.h

+ + + RTM + General Support + + + Specify the end of an RTM code region. + If this corresponds to the outermost scope, the logical processor will attempt to commit the logical processor state atomically. + If the commit fails, the logical processor will perform an RTM abort. + IF RTM_ACTIVE == 1 + RTM_NEST_COUNT := RTM_NEST_COUNT - 1 + IF RTM_NEST_COUNT == 0 + // try to commit transaction + IF FAIL_TO_COMMIT_TRANSACTION + // RTM abort (see _xabort) + ELSE + RTM_ACTIVE := 0 + FI + FI +FI + + +

immintrin.h

+ + + RTM + General Support + + + Query the transactional execution status, return 1 if inside a transactionally executing RTM or HLE region, and return 0 otherwise. + IF (RTM_ACTIVE == 1 OR HLE_ACTIVE == 1) + dst := 1 +ELSE + dst := 0 +FI + + +

immintrin.h

+ + + SERIALIZE + General Support + + Serialize instruction execution, ensuring all modifications to flags, registers, and memory by previous instructions are completed before the next instruction is fetched. + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + Perform an intermediate calculation for the next four SHA1 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst". + +W0 := a[127:96] +W1 := a[95:64] +W2 := a[63:32] +W3 := a[31:0] +W4 := b[127:96] +W5 := b[95:64] +dst[127:96] := W2 XOR W0 +dst[95:64] := W3 XOR W1 +dst[63:32] := W4 XOR W2 +dst[31:0] := W5 XOR W3 + + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + Perform the final calculation for the next four SHA1 message values (unsigned 32-bit integers) using the intermediate result in "a" and the previous message values in "b", and store the result in "dst". + +W13 := b[95:64] +W14 := b[63:32] +W15 := b[31:0] +W16 := (a[127:96] XOR W13) <<< 1 +W17 := (a[95:64] XOR W14) <<< 1 +W18 := (a[63:32] XOR W15) <<< 1 +W19 := (a[31:0] XOR W16) <<< 1 +dst[127:96] := W16 +dst[95:64] := W17 +dst[63:32] := W18 +dst[31:0] := W19 + + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + Calculate SHA1 state variable E after four rounds of operation from the current SHA1 state variable "a", add that value to the scheduled values (unsigned 32-bit integers) in "b", and store the result in "dst". + +tmp := (a[127:96] <<< 30) +dst[127:96] := b[127:96] + tmp +dst[95:64] := b[95:64] +dst[63:32] := b[63:32] +dst[31:0] := b[31:0] + + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + + Perform four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from "a" and some pre-computed sum of the next 4 round message values (unsigned 32-bit integers), and state variable E from "b", and store the updated SHA1 state (A,B,C,D) in "dst". "func" contains the logic functions and round constants. + IF (func[1:0] == 0) + f := f0() + K := K0 +ELSE IF (func[1:0] == 1) + f := f1() + K := K1 +ELSE IF (func[1:0] == 2) + f := f2() + K := K2 +ELSE IF (func[1:0] == 3) + f := f3() + K := K3 +FI +A := a[127:96] +B := a[95:64] +C := a[63:32] +D := a[31:0] +W[0] := b[127:96] +W[1] := b[95:64] +W[2] := b[63:32] +W[3] := b[31:0] +A[1] := f(B, C, D) + (A <<< 5) + W[0] + K +B[1] := A +C[1] := B <<< 30 +D[1] := C +E[1] := D +FOR i := 1 to 3 + A[i+1] := f(B[i], C[i], D[i]) + (A[i] <<< 5) + W[i] + E[i] + K + B[i+1] := A[i] + C[i+1] := B[i] <<< 30 + D[i+1] := C[i] + E[i+1] := D[i] +ENDFOR +dst[127:96] := A[4] +dst[95:64] := B[4] +dst[63:32] := C[4] +dst[31:0] := D[4] + + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + Perform an intermediate calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst". + W4 := b[31:0] +W3 := a[127:96] +W2 := a[95:64] +W1 := a[63:32] +W0 := a[31:0] +dst[127:96] := W3 + sigma0(W4) +dst[95:64] := W2 + sigma0(W3) +dst[63:32] := W1 + sigma0(W2) +dst[31:0] := W0 + sigma0(W1) + + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + Perform the final calculation for the next four SHA256 message values (unsigned 32-bit integers) using previous message values from "a" and "b", and store the result in "dst"." + W14 := b[95:64] +W15 := b[127:96] +W16 := a[31:0] + sigma1(W14) +W17 := a[63:32] + sigma1(W15) +W18 := a[95:64] + sigma1(W16) +W19 := a[127:96] + sigma1(W17) +dst[127:96] := W19 +dst[95:64] := W18 +dst[63:32] := W17 +dst[31:0] := W16 + + +

immintrin.h

+ + + Integer + SHA + Cryptography + + + + + Perform 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H) from "a", an initial SHA256 state (A,B,E,F) from "b", and a pre-computed sum of the next 2 round message values (unsigned 32-bit integers) and the corresponding round constants from "k", and store the updated SHA256 state (A,B,E,F) in "dst". + A[0] := b[127:96] +B[0] := b[95:64] +C[0] := a[127:96] +D[0] := a[95:64] +E[0] := b[63:32] +F[0] := b[31:0] +G[0] := a[63:32] +H[0] := a[31:0] +W_K[0] := k[31:0] +W_K[1] := k[63:32] +FOR i := 0 to 1 + A[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + Maj(A[i], B[i], C[i]) + sum0(A[i]) + B[i+1] := A[i] + C[i+1] := B[i] + D[i+1] := C[i] + E[i+1] := Ch(E[i], F[i], G[i]) + sum1(E[i]) + W_K[i] + H[i] + D[i] + F[i+1] := E[i] + G[i+1] := F[i] + H[i+1] := G[i] +ENDFOR +dst[127:96] := A[2] +dst[95:64] := B[2] +dst[63:32] := E[2] +dst[31:0] := F[2] + + +

immintrin.h

+ + + SSE + Swizzle + + + + + + Macro: Transpose the 4x4 matrix formed by the 4 rows of single-precision (32-bit) floating-point elements in "row0", "row1", "row2", and "row3", and store the transposed matrix in these vectors ("row0" now contains column 0, etc.). + +__m128 tmp3, tmp2, tmp1, tmp0; +tmp0 := _mm_unpacklo_ps(row0, row1); +tmp2 := _mm_unpacklo_ps(row2, row3); +tmp1 := _mm_unpackhi_ps(row0, row1); +tmp3 := _mm_unpackhi_ps(row2, row3); +row0 := _mm_movelh_ps(tmp0, tmp2); +row1 := _mm_movehl_ps(tmp2, tmp0); +row2 := _mm_movelh_ps(tmp1, tmp3); +row3 := _mm_movehl_ps(tmp3, tmp1); + +

xmmintrin.h

+ + + SSE + General Support + + + Get the unsigned 32-bit value of the MXCSR control and status register. + dst[31:0] := MXCSR + + +

xmmintrin.h

+ + + SSE + General Support + + + Set the MXCSR control and status register with the value in unsigned 32-bit integer "a". + +MXCSR := a[31:0] + + +

xmmintrin.h

+ + + SSE + General Support + + Macro: Get the exception state bits from the MXCSR control and status register. The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT + dst[31:0] := MXCSR & _MM_EXCEPT_MASK + +

xmmintrin.h

+ + + SSE + General Support + + + Macro: Set the exception state bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception state may contain any of the following flags: _MM_EXCEPT_INVALID, _MM_EXCEPT_DIV_ZERO, _MM_EXCEPT_DENORM, _MM_EXCEPT_OVERFLOW, _MM_EXCEPT_UNDERFLOW, _MM_EXCEPT_INEXACT + MXCSR := a[31:0] AND ~_MM_EXCEPT_MASK + +

xmmintrin.h

+ + + SSE + General Support + + Macro: Get the exception mask bits from the MXCSR control and status register. The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT + dst[31:0] := MXCSR & _MM_MASK_MASK + +

xmmintrin.h

+ + + SSE + General Support + + + Macro: Set the exception mask bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The exception mask may contain any of the following flags: _MM_MASK_INVALID, _MM_MASK_DIV_ZERO, _MM_MASK_DENORM, _MM_MASK_OVERFLOW, _MM_MASK_UNDERFLOW, _MM_MASK_INEXACT + MXCSR := a[31:0] AND ~_MM_MASK_MASK + +

xmmintrin.h

+ + + SSE + General Support + + Macro: Get the rounding mode bits from the MXCSR control and status register. The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO + dst[31:0] := MXCSR & _MM_ROUND_MASK + +

xmmintrin.h

+ + + SSE + General Support + + + Macro: Set the rounding mode bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The rounding mode may contain any of the following flags: _MM_ROUND_NEAREST, _MM_ROUND_DOWN, _MM_ROUND_UP, _MM_ROUND_TOWARD_ZERO + MXCSR := a[31:0] AND ~_MM_ROUND_MASK + +

xmmintrin.h

+ + + SSE + General Support + + Macro: Get the flush zero bits from the MXCSR control and status register. The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF + dst[31:0] := MXCSR & _MM_FLUSH_MASK + +

xmmintrin.h

+ + + SSE + General Support + + + Macro: Set the flush zero bits of the MXCSR control and status register to the value in unsigned 32-bit integer "a". The flush zero may contain any of the following flags: _MM_FLUSH_ZERO_ON or _MM_FLUSH_ZERO_OFF + MXCSR := a[31:0] AND ~_MM_FLUSH_MASK + +

xmmintrin.h

+ + + SSE + General Support + + + + Fetch the line of data from memory that contains address "p" to a location in the cache heirarchy specified by the locality hint "i". + + + + +

xmmintrin.h

+ + + SSE + General Support + + + Perform a serializing operation on all store-to-memory instructions that were issued prior to this instruction. Guarantees that every store instruction that precedes, in program order, is globally visible before any store instruction which follows the fence in program order. + +

xmmintrin.h

+ + + Integer + SSE + Special Math Functions + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Special Math Functions + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Special Math Functions + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Special Math Functions + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Arithmetic + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 3 + i := j*16 + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Probability/Statistics + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Probability/Statistics + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Arithmetic + Miscellaneous + + + + Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst". + +FOR j := 0 to 7 + i := j*8 + tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i]) +ENDFOR +dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56] +dst[63:16] := 0 + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Arithmetic + Miscellaneous + + + + Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of "dst". + +FOR j := 0 to 7 + i := j*8 + tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i]) +ENDFOR +dst[15:0] := tmp[7:0] + tmp[15:8] + tmp[23:16] + tmp[31:24] + tmp[39:32] + tmp[47:40] + tmp[55:48] + tmp[63:56] +dst[63:16] := 0 + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + + Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Integer + SSE + Convert + + + + Convert the signed 32-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + + Convert the signed 64-bit integer "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + + Convert packed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[63:32] := Convert_Int32_To_FP32(b[63:32]) +dst[95:64] := a[95:64] +dst[127:96] := a[127:96] + + +

xmmintrin.h

+ + + Integer + SSE + Convert + + + + Convert packed signed 32-bit integers in "b" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", and copy the upper 2 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(b[31:0]) +dst[63:32] := Convert_Int32_To_FP32(b[63:32]) +dst[95:64] := a[95:64] +dst[127:96] := a[127:96] + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Convert packed 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + m := j*32 + dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i]) +ENDFOR + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert packed unsigned 16-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*16 + m := j*32 + dst[m+31:m] := Convert_Int16_To_FP32(a[i+15:i]) +ENDFOR + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Convert the lower packed 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*8 + m := j*32 + dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i]) +ENDFOR + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert the lower packed unsigned 8-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := j*8 + m := j*32 + dst[m+31:m] := Convert_Int8_To_FP32(a[i+7:i]) +ENDFOR + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, store the results in the lower 2 elements of "dst", then covert the packed signed 32-bit integers in "b" to single-precision (32-bit) floating-point element, and store the results in the upper 2 elements of "dst". + +dst[31:0] := Convert_Int32_To_FP32(a[31:0]) +dst[63:32] := Convert_Int32_To_FP32(a[63:32]) +dst[95:64] := Convert_Int32_To_FP32(b[31:0]) +dst[127:96] := Convert_Int32_To_FP32(b[63:32]) + +

xmmintrin.h

+ + + Integer + SSE + Store + + + + Store 64-bits of integer data from "a" into memory using a non-temporal memory hint. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

xmmintrin.h

+ + + Integer + SSE + Store + + + + + Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint. + +FOR j := 0 to 7 + i := j*8 + IF mask[i+7] + MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i] + FI +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Store + + + + + Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element). + +FOR j := 0 to 7 + i := j*8 + IF mask[i+7] + MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i] + FI +ENDFOR + + +

xmmintrin.h

+ + + Integer + SSE + Swizzle + + + + Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst". + +dst[15:0] := (a[63:0] >> (imm8[1:0] * 16))[15:0] +dst[31:16] := 0 + + +

xmmintrin.h

+ + + Integer + SSE + Swizzle + + + + + Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8". + +dst[63:0] := a[63:0] +sel := imm8[1:0]*16 +dst[sel+15:sel] := i[15:0] + + +

xmmintrin.h

+ + + Integer + SSE + Miscellaneous + + + Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[j] := a[i+7] +ENDFOR +dst[MAX:8] := 0 + + +

xmmintrin.h

+ + + Integer + SSE + Swizzle + + + + Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[15:0] := src[15:0] + 1: tmp[15:0] := src[31:16] + 2: tmp[15:0] := src[47:32] + 3: tmp[15:0] := src[63:48] + ESAC + RETURN tmp[15:0] +} +dst[15:0] := SELECT4(a[63:0], imm8[1:0]) +dst[31:16] := SELECT4(a[63:0], imm8[3:2]) +dst[47:32] := SELECT4(a[63:0], imm8[5:4]) +dst[63:48] := SELECT4(a[63:0], imm8[7:6]) + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Swizzle + + + + Shuffle 16-bit integers in "a" using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[15:0] := src[15:0] + 1: tmp[15:0] := src[31:16] + 2: tmp[15:0] := src[47:32] + 3: tmp[15:0] := src[63:48] + ESAC + RETURN tmp[15:0] +} +dst[15:0] := SELECT4(a[63:0], imm8[1:0]) +dst[31:16] := SELECT4(a[63:0], imm8[3:2]) +dst[47:32] := SELECT4(a[63:0], imm8[5:4]) +dst[63:48] := SELECT4(a[63:0], imm8[7:6]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Add the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := a[31:0] + b[31:0] +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Add packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Subtract the lower single-precision (32-bit) floating-point element in "b" from the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := a[31:0] - b[31:0] +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Subtract packed single-precision (32-bit) floating-point elements in "b" from packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Multiply the lower single-precision (32-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := a[31:0] * b[31:0] +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Multiply packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] * b[i+31:i] +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Divide the lower single-precision (32-bit) floating-point element in "a" by the lower single-precision (32-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := a[31:0] / b[31:0] +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Arithmetic + + + + Divide packed single-precision (32-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := a[i+31:i] / b[i+31:i] +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := SQRT(a[31:0]) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SQRT(a[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12. + +dst[31:0] := (1.0 / a[31:0]) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (1.0 / a[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". The maximum relative error for this approximation is less than 1.5*2^-12. + +dst[31:0] := (1.0 / SQRT(a[31:0])) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". The maximum relative error for this approximation is less than 1.5*2^-12. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (1.0 / SQRT(a[i+31:i])) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper element of "dst". + +dst[31:0] := MIN(a[31:0], b[31:0]) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper element of "dst". + +dst[31:0] := MAX(a[31:0], b[31:0]) +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Logical + + + + Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (a[i+31:i] AND b[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Logical + + + + Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ((NOT a[i+31:i]) AND b[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Logical + + + + Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] OR b[i+31:i] +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Logical + + + + Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] XOR b[i+31:i] +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := ( a[31:0] == b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := ( a[31:0] < b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] < b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := ( a[31:0] <= b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] <= b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := ( a[31:0] > b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := ( a[31:0] >= b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] >= b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := ( a[31:0] != b[31:0] ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] != b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := (!( a[31:0] < b[31:0] )) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := !( a[i+31:i] < b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := (!( a[31:0] <= b[31:0] )) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (!( a[i+31:i] <= b[i+31:i] )) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := (!( a[31:0] > b[31:0] )) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (!( a[i+31:i] > b[i+31:i] )) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := (!( a[31:0] >= b[31:0] )) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := (!( a[i+31:i] >= b[i+31:i] )) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + dst[31:0] := ( a[31:0] != NaN AND b[31:0] != NaN ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] != NaN AND b[i+31:i] != NaN ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + dst[31:0] := ( a[31:0] == NaN OR b[31:0] == NaN ) ? 0xFFFFFFFF : 0 +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Compare + + + + Compare packed single-precision (32-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] == NaN OR b[i+31:i] == NaN ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + Flag + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). + +RETURN ( a[31:0] == b[31:0] ) ? 1 : 0 + + +

xmmintrin.h

+ + + Floating Point + Flag + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). + +RETURN ( a[31:0] < b[31:0] ) ? 1 : 0 + + +

xmmintrin.h

+ + + Floating Point + Flag + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). + +RETURN ( a[31:0] <= b[31:0] ) ? 1 : 0 + + +

xmmintrin.h

+ + + Floating Point + Flag + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). + +RETURN ( a[31:0] > b[31:0] ) ? 1 : 0 + + +

xmmintrin.h

+ + + Floating Point + Flag + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). + +RETURN ( a[31:0] >= b[31:0] ) ? 1 : 0 + + +

xmmintrin.h

+ + + Floating Point + Flag + SSE + Compare + + + + Compare the lower single-precision (32-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). + +RETURN ( a[31:0] != b[31:0] ) ? 1 : 0 + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_Int32(a[31:0]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_Int32(a[31:0]) + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + +dst[63:0] := Convert_FP32_To_Int64(a[31:0]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Copy the lower single-precision (32-bit) floating-point element of "a" to "dst". + +dst[31:0] := a[31:0] + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP32_To_Int32_Truncate(a[31:0]) + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert the lower single-precision (32-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + +dst[63:0] := Convert_FP32_To_Int64_Truncate(a[31:0]) + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + SSE + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) +ENDFOR + + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 16-bit integers, and store the results in "dst". Note: this intrinsic will generate 0x7FFF, rather than 0x8000, for input values between 0x7FFF and 0x7FFFFFFF. + +FOR j := 0 to 3 + i := 16*j + k := 32*j + IF a[k+31:k] >= FP32(0x7FFF) && a[k+31:k] <= FP32(0x7FFFFFFF) + dst[i+15:i] := 0x7FFF + ELSE + dst[i+15:i] := Convert_FP32_To_Int16(a[k+31:k]) + FI +ENDFOR + +

xmmintrin.h

+ + + Floating Point + Integer + SSE + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 8-bit integers, and store the results in lower 4 elements of "dst". Note: this intrinsic will generate 0x7F, rather than 0x80, for input values between 0x7F and 0x7FFFFFFF. + +FOR j := 0 to 3 + i := 8*j + k := 32*j + IF a[k+31:k] >= FP32(0x7F) && a[k+31:k] <= FP32(0x7FFFFFFF) + dst[i+7:i] := 0x7F + ELSE + dst[i+7:i] := Convert_FP32_To_Int8(a[k+31:k]) + FI +ENDFOR + +

xmmintrin.h

+ + + Floating Point + SSE + Set + + + Copy single-precision (32-bit) floating-point element "a" to the lower element of "dst", and zero the upper 3 elements. + +dst[31:0] := a[31:0] +dst[127:32] := 0 + +

xmmintrin.h

+ + + Floating Point + SSE + Set + + + Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR + +

xmmintrin.h

+ + + Floating Point + SSE + Set + + + Broadcast single-precision (32-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR + +

xmmintrin.h

+ + + Floating Point + SSE + Set + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 +dst[95:64] := e2 +dst[127:96] := e3 + +

xmmintrin.h

+ + + Floating Point + SSE + Set + + + + + + Set packed single-precision (32-bit) floating-point elements in "dst" with the supplied values in reverse order. + +dst[31:0] := e3 +dst[63:32] := e2 +dst[95:64] := e1 +dst[127:96] := e0 + +

xmmintrin.h

+ + + Floating Point + SSE + Set + + + Return vector of type __m128 with all elements set to zero. + +dst[MAX:0] := 0 + + +

xmmintrin.h

+ + + Integer + SSE + Load + + + + Load 2 single-precision (32-bit) floating-point elements from memory into the upper 2 elements of "dst", and copy the lower 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary. + +dst[31:0] := a[31:0] +dst[63:32] := a[63:32] +dst[95:64] := MEM[mem_addr+31:mem_addr] +dst[127:96] := MEM[mem_addr+63:mem_addr+32] + + +

xmmintrin.h

+ + + Integer + SSE + Load + + + + Load 2 single-precision (32-bit) floating-point elements from memory into the lower 2 elements of "dst", and copy the upper 2 elements from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary. + +dst[31:0] := MEM[mem_addr+31:mem_addr] +dst[63:32] := MEM[mem_addr+63:mem_addr+32] +dst[95:64] := a[95:64] +dst[127:96] := a[127:96] + + +

xmmintrin.h

+ + + Floating Point + SSE + Load + + + Load a single-precision (32-bit) floating-point element from memory into the lower of "dst", and zero the upper 3 elements. "mem_addr" does not need to be aligned on any particular boundary. + +dst[31:0] := MEM[mem_addr+31:mem_addr] +dst[127:32] := 0 + + +

xmmintrin.h

+ + + Floating Point + SSE + Load + + + Load a single-precision (32-bit) floating-point element from memory into all elements of "dst". + +dst[31:0] := MEM[mem_addr+31:mem_addr] +dst[63:32] := MEM[mem_addr+31:mem_addr] +dst[95:64] := MEM[mem_addr+31:mem_addr] +dst[127:96] := MEM[mem_addr+31:mem_addr] + +

xmmintrin.h

+ + + Floating Point + SSE + Load + + + Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

xmmintrin.h

+ + + Floating Point + SSE + Load + + + Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

xmmintrin.h

+ + + Floating Point + SSE + Load + + + Load 4 single-precision (32-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[31:0] := MEM[mem_addr+127:mem_addr+96] +dst[63:32] := MEM[mem_addr+95:mem_addr+64] +dst[95:64] := MEM[mem_addr+63:mem_addr+32] +dst[127:96] := MEM[mem_addr+31:mem_addr] + +

xmmintrin.h

+ + + Floating Point + SSE + Store + + + + Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

xmmintrin.h

+ + + Integer + SSE + Store + + + + Store the upper 2 single-precision (32-bit) floating-point elements from "a" into memory. + +MEM[mem_addr+31:mem_addr] := a[95:64] +MEM[mem_addr+63:mem_addr+32] := a[127:96] + + +

xmmintrin.h

+ + + Integer + SSE + Store + + + + Store the lower 2 single-precision (32-bit) floating-point elements from "a" into memory. + +MEM[mem_addr+31:mem_addr] := a[31:0] +MEM[mem_addr+63:mem_addr+32] := a[63:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Store + + + + Store the lower single-precision (32-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+31:mem_addr] := a[31:0] + + +

xmmintrin.h

+ + + Floating Point + SSE + Store + + + + Store the lower single-precision (32-bit) floating-point element from "a" into 4 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+31:mem_addr] := a[31:0] +MEM[mem_addr+63:mem_addr+32] := a[31:0] +MEM[mem_addr+95:mem_addr+64] := a[31:0] +MEM[mem_addr+127:mem_addr+96] := a[31:0] + +

xmmintrin.h

+ + + Floating Point + SSE + Store + + + + Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

xmmintrin.h

+ + + Floating Point + SSE + Store + + + + Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

xmmintrin.h

+ + + Floating Point + SSE + Store + + + + Store 4 single-precision (32-bit) floating-point elements from "a" into memory in reverse order. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+31:mem_addr] := a[127:96] +MEM[mem_addr+63:mem_addr+32] := a[95:64] +MEM[mem_addr+95:mem_addr+64] := a[63:32] +MEM[mem_addr+127:mem_addr+96] := a[31:0] + + +

xmmintrin.h

+ + + Floating Point + SSE + Move + + + + Move the lower single-precision (32-bit) floating-point element from "b" to the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := b[31:0] +dst[127:32] := a[127:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Swizzle + + + + + Shuffle single-precision (32-bit) floating-point elements in "a" using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(b[127:0], imm8[5:4]) +dst[127:96] := SELECT4(b[127:0], imm8[7:6]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Swizzle + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the high half "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Swizzle + + + + Unpack and interleave single-precision (32-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) + + +

xmmintrin.h

+ + + Floating Point + SSE + Move + + + + Move the upper 2 single-precision (32-bit) floating-point elements from "b" to the lower 2 elements of "dst", and copy the upper 2 elements from "a" to the upper 2 elements of "dst". + +dst[31:0] := b[95:64] +dst[63:32] := b[127:96] +dst[95:64] := a[95:64] +dst[127:96] := a[127:96] + + +

xmmintrin.h

+ + + Floating Point + SSE + Move + + + + Move the lower 2 single-precision (32-bit) floating-point elements from "b" to the upper 2 elements of "dst", and copy the lower 2 elements from "a" to the lower 2 elements of "dst". + +dst[31:0] := a[31:0] +dst[63:32] := a[63:32] +dst[95:64] := b[31:0] +dst[127:96] := b[63:32] + + +

xmmintrin.h

+ + + Floating Point + SSE + Miscellaneous + + + Set each bit of mask "dst" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in "a". + +FOR j := 0 to 3 + i := j*32 + IF a[i+31] + dst[j] := 1 + ELSE + dst[j] := 0 + FI +ENDFOR +dst[MAX:4] := 0 + + +

xmmintrin.h

+ + + SSE + General Support + + + + Allocate "size" bytes of memory, aligned to the alignment specified in "align", and return a pointer to the allocated memory. "_mm_free" should be used to free memory that is allocated with "_mm_malloc". +

xmmintrin.h

+ + + SSE + General Support + + + Free aligned memory that was allocated with "_mm_malloc". +

xmmintrin.h

+ + + Floating Point + SSE + General Support + + + Return vector of type __m128 with undefined elements. +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ACOS(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ACOS(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ACOSH(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ACOSH(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ASIN(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ASIN(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ASINH(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ASINH(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ATAN(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ATAN(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + + Compute the inverse tangent of packed double-precision (64-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians. + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ATAN2(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + + Compute the inverse tangent of packed single-precision (32-bit) floating-point elements in "a" divided by packed elements in "b", and store the results in "dst" expressed in radians. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ATAN2(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ATANH(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the inverse hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ATANH(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CubeRoot(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := CubeRoot(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CDFNormal(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := CDFNormal(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the inverse cumulative distribution function of packed double-precision (64-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := InverseCDFNormal(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the inverse cumulative distribution function of packed single-precision (32-bit) floating-point elements in "a" using the normal distribution, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := InverseCDFNormal(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]". + +DEFINE CEXP(a[31:0], b[31:0]) { + result[31:0] := POW(FP32(e), a[31:0]) * COS(b[31:0]) + result[63:32] := POW(FP32(e), a[31:0]) * SIN(b[31:0]) + RETURN result +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CEXP(a[i+31:i], a[i+63:i+32]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the natural logarithm of packed complex numbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]". + +DEFINE CLOG(a[31:0], b[31:0]) { + result[31:0] := LOG(SQRT(POW(a, 2.0) + POW(b, 2.0))) + result[63:32] := ATAN2(b, a) + RETURN result +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CLOG(a[i+31:i], a[i+63:i+32]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := COS(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := COS(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := COSD(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := COSD(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the hyperbolic cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := COSH(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the hyperbolic cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := COSH(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the square root of packed complex snumbers in "a", and store the complex results in "dst". Each complex number is composed of two adjacent single-precision (32-bit) floating-point elements, which defines the complex number "complex = vec.fp32[0] + i * vec.fp32[1]". + +DEFINE CSQRT(a[31:0], b[31:0]) { + sign[31:0] := (b < 0.0) ? -FP32(1.0) : FP32(1.0) + result[31:0] := SQRT((a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0) + result[63:32] := sign * SQRT((-a + SQRT(POW(a, 2.0) + POW(b, 2.0))) / 2.0) + RETURN result +} +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CSQRT(a[i+31:i], a[i+63:i+32]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed signed 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 15 + i := 8*j + IF b[i+7:i] == 0 + #DE + FI + dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed signed 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 7 + i := 16*j + IF b[i+15:i] == 0 + #DE + FI + dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 3 + i := 32*j + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed signed 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 1 + i := 64*j + IF b[i+63:i] == 0 + #DE + FI + dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 15 + i := 8*j + IF b[i+7:i] == 0 + #DE + FI + dst[i+7:i] := Truncate8(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 7 + i := 16*j + IF b[i+15:i] == 0 + #DE + FI + dst[i+15:i] := Truncate16(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 3 + i := 32*j + IF b[i+31:i] == 0 + #DE + FI + dst[i+31:i] := Truncate32(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + +FOR j := 0 to 1 + i := 64*j + IF b[i+63:i] == 0 + #DE + FI + dst[i+63:i] := Truncate64(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Arithmetic + + + Compute the error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ERF(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ERF(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := 1.0 - ERF(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+63:i] := 1.0 - ERF(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the inverse complementary error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+63:i])) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the inverse complementary error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+63:i] := 1.0 / (1.0 - ERF(a[i+31:i])) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the inverse error function of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := 1.0 / ERF(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Probability/Statistics + + + Compute the inverse error function of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+63:i] := 1.0 / ERF(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := POW(e, a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := POW(FP32(e), a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of 10 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := POW(10.0, a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of 10 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := POW(FP32(10.0), a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of 2 raised to the power of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := POW(2.0, a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of 2 raised to the power of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := POW(FP32(2.0), a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed double-precision (64-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := POW(e, a[i+63:i]) - 1.0 +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the exponential value of "e" raised to the power of packed single-precision (32-bit) floating-point elements in "a", subtract one from each element, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := POW(FP32(e), a[i+31:i]) - 1.0 +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SQRT(POW(a[i+63:i], 2.0) + POW(b[i+63:i], 2.0)) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + + Compute the length of the hypotenous of a right triangle, with the lengths of the other two sides of the triangle stored as packed single-precision (32-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SQRT(POW(a[i+31:i], 2.0) + POW(b[i+31:i], 2.0)) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + + Divide packed 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed 32-bit integers into memory at "mem_addr". + FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the inverse cube root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := InvCubeRoot(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the inverse cube root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := InvCubeRoot(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the inverse square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := InvSQRT(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the inverse square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := InvSQRT(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed 32-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the natural logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the natural logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the base-10 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) / LOG(10.0) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the base-10 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(10.0) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the natural logarithm of one plus packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := LOG(1.0 + a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the natural logarithm of one plus packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := LOG(1.0 + a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the base-2 logarithm of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := LOG(a[i+63:i]) / LOG(2.0) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the base-2 logarithm of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := LOG(a[i+31:i]) / LOG(2.0) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Convert the exponent of each packed double-precision (64-bit) floating-point element in "a" to a double-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ConvertExpFP64(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Convert the exponent of each packed single-precision (32-bit) floating-point element in "a" to a single-precision floating-point number representing the integer exponent, and store the results in "dst". This intrinsic essentially calculates "floor(log2(x))" for each element. + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ConvertExpFP32(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + + Compute the exponential value of packed double-precision (64-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := POW(a[i+63:i], b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + + Compute the exponential value of packed single-precision (32-bit) floating-point elements in "a" raised by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := POW(a[i+31:i], b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed 8-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 15 + i := 8*j + dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed 16-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 7 + i := 16*j + dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed 64-bit integers in "a" by packed elements in "b", and store the remainders as packed 32-bit integers in "dst". + FOR j := 0 to 1 + i := 64*j + dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 8-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 15 + i := 8*j + dst[i+7:i] := REMAINDER(a[i+7:i] / b[i+7:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 16-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 7 + i := 16*j + dst[i+15:i] := REMAINDER(a[i+15:i] / b[i+15:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 64-bit integers in "a" by packed elements in "b", and store the remainders as packed unsigned 32-bit integers in "dst". + FOR j := 0 to 1 + i := 64*j + dst[i+63:i] := REMAINDER(a[i+63:i] / b[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SIN(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SIN(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + + Compute the sine and cosine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SIN(a[i+63:i]) + MEM[mem_addr+i+63:mem_addr+i] := COS(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + + Compute the sine and cosine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, store the sine in "dst", and store the cosine into memory at "mem_addr". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SIN(a[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := COS(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the sine of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SIND(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the sine of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SIND(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the hyperbolic sine of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SINH(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the hyperbolic sine of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SINH(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CEIL(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := CEIL(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := FLOOR(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := FLOOR(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ROUND(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" to the nearest integer value, and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ROUND(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_pd". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SQRT(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Elementary Math Functions + + + Compute the square root of packed single-precision (32-bit) floating-point elements in "a", and store the results in "dst". Note that this intrinsic is less efficient than "_mm_sqrt_ps". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SQRT(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := TAN(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := TAN(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := TAND(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in degrees, and store the results in "dst". + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := TAND(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the hyperbolic tangent of packed double-precision (64-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := TANH(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Trigonometry + + + Compute the hyperbolic tangent of packed single-precision (32-bit) floating-point elements in "a" expressed in radians, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := TANH(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Miscellaneous + + + Truncate the packed double-precision (64-bit) floating-point elements in "a", and store the results as packed double-precision floating-point elements in "dst". This intrinsic may generate the "roundpd"/"vroundpd" instruction. + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := TRUNCATE(a[i+63:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Floating Point + SSE + Miscellaneous + + + Truncate the packed single-precision (32-bit) floating-point elements in "a", and store the results as packed single-precision floating-point elements in "dst". This intrinsic may generate the "roundps"/"vroundps" instruction. + FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := TRUNCATE(a[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", and store the truncated results in "dst". + FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Arithmetic + + + + + Divide packed unsigned 32-bit integers in "a" by packed elements in "b", store the truncated results in "dst", and store the remainders as packed unsigned 32-bit integers into memory at "mem_addr". + FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := TRUNCATE(a[i+31:i] / b[i+31:i]) + MEM[mem_addr+i+31:mem_addr+i] := REMAINDER(a[i+31:i] / b[i+31:i]) +ENDFOR +dst[MAX:128] := 0 + +

immintrin.h

+ + + Integer + SSE + Store + + + + Store 16-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+15:mem_addr] := a[15:0] + +

immintrin.h

+ + + Integer + SSE + Load + + + Load unaligned 64-bit integer from memory into the first element of "dst". + +dst[63:0] := MEM[mem_addr+63:mem_addr] +dst[MAX:64] := 0 + + +

immintrin.h

+ + + Integer + SSE + Store + + + + Store 64-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

immintrin.h

+ + + Integer + SSE + Load + + + Load unaligned 16-bit integer from memory into the first element of "dst". + +dst[15:0] := MEM[mem_addr+15:mem_addr] +dst[MAX:16] := 0 + +

immintrin.h

+ + + Floating Point + SSE2 + General Support + + + Return vector of type __m128d with undefined elements. +

immintrin.h

+ + + Integer + SSE2 + General Support + + + Return vector of type __m128i with undefined elements. +

immintrin.h

+ + + Integer + SSE2 + Load + + + Load unaligned 32-bit integer from memory into the first element of "dst". + +dst[31:0] := MEM[mem_addr+31:mem_addr] +dst[MAX:32] := 0 + + +

immintrin.h

+ + + Integer + SSE2 + Store + + + + Store 32-bit integer from the first element of "a" into memory. "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+31:mem_addr] := a[31:0] + + +

immintrin.h

+ + + SSE2 + General Support + + + Provide a hint to the processor that the code sequence is a spin-wait loop. This can help improve the performance and power consumption of spin-wait loops. + +

emmintrin.h

+ + + SSE2 + General Support + + + Invalidate and flush the cache line that contains "p" from all levels of the cache hierarchy. + +

emmintrin.h

+ + + SSE2 + General Support + + + Perform a serializing operation on all load-from-memory instructions that were issued prior to this instruction. Guarantees that every load instruction that precedes, in program order, is globally visible before any load instruction which follows the fence in program order. + +

emmintrin.h

+ + + SSE2 + General Support + + + Perform a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior to this instruction. Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction which follows the fence in program order. + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := a[i+7:i] + b[i+7:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := a[i+15:i] + b[i+15:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed 32-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] + b[i+31:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add 64-bit integers "a" and "b", and store the result in "dst". + +dst[63:0] := a[63:0] + b[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed 64-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed signed 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := Saturate8( a[i+7:i] + b[i+7:i] ) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed signed 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i] + b[i+15:i] ) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed unsigned 8-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := SaturateU8( a[i+7:i] + b[i+7:i] ) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Add packed unsigned 16-bit integers in "a" and "b" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := SaturateU16( a[i+15:i] + b[i+15:i] ) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Probability/Statistics + + + + Average packed unsigned 8-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := (a[i+7:i] + b[i+7:i] + 1) >> 1 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Probability/Statistics + + + + Average packed unsigned 16-bit integers in "a" and "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := (a[i+15:i] + b[i+15:i] + 1) >> 1 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := SignExtend32(a[i+31:i+16]*b[i+31:i+16]) + SignExtend32(a[i+15:i]*b[i+15:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Special Math Functions + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Special Math Functions + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Special Math Functions + + + + Compare packed signed 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Special Math Functions + + + + Compare packed unsigned 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Multiply the packed signed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 7 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[31:16] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Multiply the packed unsigned 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 7 + i := j*16 + tmp[31:0] := a[i+15:i] * b[i+15:i] + dst[i+15:i] := tmp[31:16] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Multiply the packed 16-bit integers in "a" and "b", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in "dst". + +FOR j := 0 to 7 + i := j*16 + tmp[31:0] := SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i]) + dst[i+15:i] := tmp[15:0] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Multiply the low unsigned 32-bit integers from "a" and "b", and store the unsigned 64-bit result in "dst". + +dst[63:0] := a[31:0] * b[31:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Multiply the low unsigned 32-bit integers from each packed 64-bit element in "a" and "b", and store the unsigned 64-bit results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+31:i] * b[i+31:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + Miscellaneous + + + + Compute the absolute differences of packed unsigned 8-bit integers in "a" and "b", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in "dst". + +FOR j := 0 to 15 + i := j*8 + tmp[i+7:i] := ABS(a[i+7:i] - b[i+7:i]) +ENDFOR +FOR j := 0 to 1 + i := j*64 + dst[i+15:i] := tmp[i+7:i] + tmp[i+15:i+8] + tmp[i+23:i+16] + tmp[i+31:i+24] + \ + tmp[i+39:i+32] + tmp[i+47:i+40] + tmp[i+55:i+48] + tmp[i+63:i+56] + dst[i+63:i+16] := 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed 8-bit integers in "b" from packed 8-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := a[i+7:i] - b[i+7:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed 16-bit integers in "b" from packed 16-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := a[i+15:i] - b[i+15:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed 32-bit integers in "b" from packed 32-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[i+31:i] - b[i+31:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract 64-bit integer "b" from 64-bit integer "a", and store the result in "dst". + +dst[63:0] := a[63:0] - b[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed 64-bit integers in "b" from packed 64-bit integers in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed signed 8-bit integers in "b" from packed 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := Saturate8(a[i+7:i] - b[i+7:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed signed 16-bit integers in "b" from packed 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := Saturate16(a[i+15:i] - b[i+15:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed unsigned 8-bit integers in "b" from packed unsigned 8-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := SaturateU8(a[i+7:i] - b[i+7:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Arithmetic + + + + Subtract packed unsigned 16-bit integers in "b" from packed unsigned 16-bit integers in "a" using saturation, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := SaturateU16(a[i+15:i] - b[i+15:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift "a" left by "imm8" bytes while shifting in zeros, and store the results in "dst". + +tmp := imm8[7:0] +IF tmp > 15 + tmp := 16 +FI +dst[127:0] := a[127:0] << (tmp*8) + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift "a" right by "imm8" bytes while shifting in zeros, and store the results in "dst". + +tmp := imm8[7:0] +IF tmp > 15 + tmp := 16 +FI +dst[127:0] := a[127:0] >> (tmp*8) + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 16-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 16-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] << count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 32-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 32-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] << count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 64-bit integers in "a" left by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 64-bit integers in "a" left by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] << count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := (a[i+15] ? 0xFFFF : 0x0) + ELSE + dst[i+15:i] := SignExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in sign bits, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := (a[i+31] ? 0xFFFFFFFF : 0x0) + ELSE + dst[i+31:i] := SignExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 16-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF imm8[7:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 16-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF count[63:0] > 15 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := ZeroExtend16(a[i+15:i] >> count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 32-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF imm8[7:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 32-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF count[63:0] > 31 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := ZeroExtend32(a[i+31:i] >> count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 64-bit integers in "a" right by "imm8" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF imm8[7:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> imm8[7:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Shift + + + + Shift packed 64-bit integers in "a" right by "count" while shifting in zeros, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF count[63:0] > 63 + dst[i+63:i] := 0 + ELSE + dst[i+63:i] := ZeroExtend64(a[i+63:i] >> count[63:0]) + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Logical + + + + Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[127:0] := (a[127:0] AND b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Logical + + + + Compute the bitwise NOT of 128 bits (representing integer data) in "a" and then AND with "b", and store the result in "dst". + +dst[127:0] := ((NOT a[127:0]) AND b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Logical + + + + Compute the bitwise OR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[127:0] := (a[127:0] OR b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Logical + + + + Compute the bitwise XOR of 128 bits (representing integer data) in "a" and "b", and store the result in "dst". + +dst[127:0] := (a[127:0] XOR b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed 8-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := ( a[i+7:i] == b[i+7:i] ) ? 0xFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed 16-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := ( a[i+15:i] == b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed 32-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] == b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := ( a[i+7:i] > b[i+7:i] ) ? 0xFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := ( a[i+15:i] > b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] > b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed signed 8-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtb instruction with the order of the operands switched. + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := ( a[i+7:i] < b[i+7:i] ) ? 0xFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed signed 16-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtw instruction with the order of the operands switched. + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := ( a[i+15:i] < b[i+15:i] ) ? 0xFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Compare + + + + Compare packed signed 32-bit integers in "a" and "b" for less-than, and store the results in "dst". Note: This intrinsic emits the pcmpgtd instruction with the order of the operands switched. + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ( a[i+31:i] < b[i+31:i] ) ? 0xFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + m := j*64 + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + + Convert the signed 32-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_Int32_To_FP64(b[31:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + + Convert the signed 64-bit integer "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_Int64_To_FP64(b[63:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert packed signed 32-bit integers in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := Convert_Int32_To_FP32(a[i+31:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + Convert packed signed 32-bit integers in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := j*32 + m := j*64 + dst[m+63:m] := Convert_Int32_To_FP64(a[i+31:i]) +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Convert + + + Copy 32-bit integer "a" to the lower elements of "dst", and zero the upper elements of "dst". + +dst[31:0] := a[31:0] +dst[127:32] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Convert + + + Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element. + +dst[63:0] := a[63:0] +dst[127:64] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Convert + + + Copy 64-bit integer "a" to the lower element of "dst", and zero the upper element. + +dst[63:0] := a[63:0] +dst[127:64] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Convert + + + Copy the lower 32-bit integer in "a" to "dst". + +dst[31:0] := a[31:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Convert + + + Copy the lower 64-bit integer in "a" to "dst". + +dst[63:0] := a[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Convert + + + Copy the lower 64-bit integer in "a" to "dst". + +dst[63:0] := a[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + Set packed 64-bit integers in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + Set packed 64-bit integers in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + + + Set packed 32-bit integers in "dst" with the supplied values. + +dst[31:0] := e0 +dst[63:32] := e1 +dst[95:64] := e2 +dst[127:96] := e3 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + + + + + + + Set packed 16-bit integers in "dst" with the supplied values. + +dst[15:0] := e0 +dst[31:16] := e1 +dst[47:32] := e2 +dst[63:48] := e3 +dst[79:64] := e4 +dst[95:80] := e5 +dst[111:96] := e6 +dst[127:112] := e7 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + + + + + + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values. + +dst[7:0] := e0 +dst[15:8] := e1 +dst[23:16] := e2 +dst[31:24] := e3 +dst[39:32] := e4 +dst[47:40] := e5 +dst[55:48] := e6 +dst[63:56] := e7 +dst[71:64] := e8 +dst[79:72] := e9 +dst[87:80] := e10 +dst[95:88] := e11 +dst[103:96] := e12 +dst[111:104] := e13 +dst[119:112] := e14 +dst[127:120] := e15 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + Broadcast 64-bit integer "a" to all elements of "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + Broadcast 64-bit integer "a" to all elements of "dst". This intrinsic may generate the "vpbroadcastq". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + Broadcast 32-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastd". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := a[31:0] +ENDFOR + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + Broadcast 16-bit integer "a" to all all elements of "dst". This intrinsic may generate "vpbroadcastw". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := a[15:0] +ENDFOR + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + Broadcast 8-bit integer "a" to all elements of "dst". This intrinsic may generate "vpbroadcastb". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := a[7:0] +ENDFOR + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + Set packed 64-bit integers in "dst" with the supplied values in reverse order. + +dst[63:0] := e1 +dst[127:64] := e0 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + + + Set packed 32-bit integers in "dst" with the supplied values in reverse order. + +dst[31:0] := e3 +dst[63:32] := e2 +dst[95:64] := e1 +dst[127:96] := e0 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + + + + + + + Set packed 16-bit integers in "dst" with the supplied values in reverse order. + +dst[15:0] := e7 +dst[31:16] := e6 +dst[47:32] := e5 +dst[63:48] := e4 +dst[79:64] := e3 +dst[95:80] := e2 +dst[111:96] := e1 +dst[127:112] := e0 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + + + + + + + + + + + + + + + + + Set packed 8-bit integers in "dst" with the supplied values in reverse order. + +dst[7:0] := e15 +dst[15:8] := e14 +dst[23:16] := e13 +dst[31:24] := e12 +dst[39:32] := e11 +dst[47:40] := e10 +dst[55:48] := e9 +dst[63:56] := e8 +dst[71:64] := e7 +dst[79:72] := e6 +dst[87:80] := e5 +dst[95:88] := e4 +dst[103:96] := e3 +dst[111:104] := e2 +dst[119:112] := e1 +dst[127:120] := e0 + +

emmintrin.h

+ + + Integer + SSE2 + Set + + Return vector of type __m128i with all elements set to zero. + +dst[MAX:0] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Load + + + Load 64-bit integer from memory into the first element of "dst". + +dst[63:0] := MEM[mem_addr+63:mem_addr] +dst[MAX:64] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Load + + + Load 128-bits of integer data from memory into "dst". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

emmintrin.h

+ + + Integer + SSE2 + Load + + + Load 128-bits of integer data from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + + Conditionally store 8-bit integer elements from "a" into memory using "mask" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint. "mem_addr" does not need to be aligned on any particular boundary. + +FOR j := 0 to 15 + i := j*8 + IF mask[i+7] + MEM[mem_addr+i+7:mem_addr+i] := a[i+7:i] + FI +ENDFOR + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + Store 128-bits of integer data from "a" into memory. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + Store 128-bits of integer data from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + Store 64-bit integer from the first element of "a" into memory. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + Store 128-bits of integer data from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + Store 32-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated. + +MEM[mem_addr+31:mem_addr] := a[31:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Store + + + + Store 64-bit integer "a" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address "mem_addr" is already in the cache, the cache will be updated. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Miscellaneous + + + Copy the lower 64-bit integer in "a" to "dst". + +dst[63:0] := a[63:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Move + + + Copy the 64-bit integer "a" to the lower element of "dst", and zero the upper element. + +dst[63:0] := a[63:0] +dst[127:64] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Move + + + Copy the lower 64-bit integer in "a" to the lower element of "dst", and zero the upper element. + +dst[63:0] := a[63:0] +dst[127:64] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using signed saturation, and store the results in "dst". + +dst[7:0] := Saturate8(a[15:0]) +dst[15:8] := Saturate8(a[31:16]) +dst[23:16] := Saturate8(a[47:32]) +dst[31:24] := Saturate8(a[63:48]) +dst[39:32] := Saturate8(a[79:64]) +dst[47:40] := Saturate8(a[95:80]) +dst[55:48] := Saturate8(a[111:96]) +dst[63:56] := Saturate8(a[127:112]) +dst[71:64] := Saturate8(b[15:0]) +dst[79:72] := Saturate8(b[31:16]) +dst[87:80] := Saturate8(b[47:32]) +dst[95:88] := Saturate8(b[63:48]) +dst[103:96] := Saturate8(b[79:64]) +dst[111:104] := Saturate8(b[95:80]) +dst[119:112] := Saturate8(b[111:96]) +dst[127:120] := Saturate8(b[127:112]) + + +

emmintrin.h

+ + + Integer + SSE2 + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using signed saturation, and store the results in "dst". + +dst[15:0] := Saturate16(a[31:0]) +dst[31:16] := Saturate16(a[63:32]) +dst[47:32] := Saturate16(a[95:64]) +dst[63:48] := Saturate16(a[127:96]) +dst[79:64] := Saturate16(b[31:0]) +dst[95:80] := Saturate16(b[63:32]) +dst[111:96] := Saturate16(b[95:64]) +dst[127:112] := Saturate16(b[127:96]) + + +

emmintrin.h

+ + + Integer + SSE2 + Miscellaneous + + + + Convert packed signed 16-bit integers from "a" and "b" to packed 8-bit integers using unsigned saturation, and store the results in "dst". + +dst[7:0] := SaturateU8(a[15:0]) +dst[15:8] := SaturateU8(a[31:16]) +dst[23:16] := SaturateU8(a[47:32]) +dst[31:24] := SaturateU8(a[63:48]) +dst[39:32] := SaturateU8(a[79:64]) +dst[47:40] := SaturateU8(a[95:80]) +dst[55:48] := SaturateU8(a[111:96]) +dst[63:56] := SaturateU8(a[127:112]) +dst[71:64] := SaturateU8(b[15:0]) +dst[79:72] := SaturateU8(b[31:16]) +dst[87:80] := SaturateU8(b[47:32]) +dst[95:88] := SaturateU8(b[63:48]) +dst[103:96] := SaturateU8(b[79:64]) +dst[111:104] := SaturateU8(b[95:80]) +dst[119:112] := SaturateU8(b[111:96]) +dst[127:120] := SaturateU8(b[127:112]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Extract a 16-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst". + +dst[15:0] := (a[127:0] >> (imm8[2:0] * 16))[15:0] +dst[31:16] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + + Copy "a" to "dst", and insert the 16-bit integer "i" into "dst" at the location specified by "imm8". + +dst[127:0] := a[127:0] +sel := imm8[2:0]*16 +dst[sel+15:sel] := i[15:0] + + +

emmintrin.h

+ + + Integer + SSE2 + Miscellaneous + + + Create mask from the most significant bit of each 8-bit element in "a", and store the result in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[j] := a[i+7] +ENDFOR +dst[MAX:16] := 0 + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Shuffle 32-bit integers in "a" using the control in "imm8", and store the results in "dst". + +DEFINE SELECT4(src, control) { + CASE(control[1:0]) OF + 0: tmp[31:0] := src[31:0] + 1: tmp[31:0] := src[63:32] + 2: tmp[31:0] := src[95:64] + 3: tmp[31:0] := src[127:96] + ESAC + RETURN tmp[31:0] +} +dst[31:0] := SELECT4(a[127:0], imm8[1:0]) +dst[63:32] := SELECT4(a[127:0], imm8[3:2]) +dst[95:64] := SELECT4(a[127:0], imm8[5:4]) +dst[127:96] := SELECT4(a[127:0], imm8[7:6]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Shuffle 16-bit integers in the high 64 bits of "a" using the control in "imm8". Store the results in the high 64 bits of "dst", with the low 64 bits being copied from from "a" to "dst". + +dst[63:0] := a[63:0] +dst[79:64] := (a >> (imm8[1:0] * 16))[79:64] +dst[95:80] := (a >> (imm8[3:2] * 16))[79:64] +dst[111:96] := (a >> (imm8[5:4] * 16))[79:64] +dst[127:112] := (a >> (imm8[7:6] * 16))[79:64] + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Shuffle 16-bit integers in the low 64 bits of "a" using the control in "imm8". Store the results in the low 64 bits of "dst", with the high 64 bits being copied from from "a" to "dst". + +dst[15:0] := (a >> (imm8[1:0] * 16))[15:0] +dst[31:16] := (a >> (imm8[3:2] * 16))[15:0] +dst[47:32] := (a >> (imm8[5:4] * 16))[15:0] +dst[63:48] := (a >> (imm8[7:6] * 16))[15:0] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 8-bit integers from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[71:64] + dst[15:8] := src2[71:64] + dst[23:16] := src1[79:72] + dst[31:24] := src2[79:72] + dst[39:32] := src1[87:80] + dst[47:40] := src2[87:80] + dst[55:48] := src1[95:88] + dst[63:56] := src2[95:88] + dst[71:64] := src1[103:96] + dst[79:72] := src2[103:96] + dst[87:80] := src1[111:104] + dst[95:88] := src2[111:104] + dst[103:96] := src1[119:112] + dst[111:104] := src2[119:112] + dst[119:112] := src1[127:120] + dst[127:120] := src2[127:120] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_BYTES(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 16-bit integers from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[79:64] + dst[31:16] := src2[79:64] + dst[47:32] := src1[95:80] + dst[63:48] := src2[95:80] + dst[79:64] := src1[111:96] + dst[95:80] := src2[111:96] + dst[111:96] := src1[127:112] + dst[127:112] := src2[127:112] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_WORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 32-bit integers from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[95:64] + dst[63:32] := src2[95:64] + dst[95:64] := src1[127:96] + dst[127:96] := src2[127:96] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_DWORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 64-bit integers from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 8-bit integers from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_BYTES(src1[127:0], src2[127:0]) { + dst[7:0] := src1[7:0] + dst[15:8] := src2[7:0] + dst[23:16] := src1[15:8] + dst[31:24] := src2[15:8] + dst[39:32] := src1[23:16] + dst[47:40] := src2[23:16] + dst[55:48] := src1[31:24] + dst[63:56] := src2[31:24] + dst[71:64] := src1[39:32] + dst[79:72] := src2[39:32] + dst[87:80] := src1[47:40] + dst[95:88] := src2[47:40] + dst[103:96] := src1[55:48] + dst[111:104] := src2[55:48] + dst[119:112] := src1[63:56] + dst[127:120] := src2[63:56] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_BYTES(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 16-bit integers from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_WORDS(src1[127:0], src2[127:0]) { + dst[15:0] := src1[15:0] + dst[31:16] := src2[15:0] + dst[47:32] := src1[31:16] + dst[63:48] := src2[31:16] + dst[79:64] := src1[47:32] + dst[95:80] := src2[47:32] + dst[111:96] := src1[63:48] + dst[127:112] := src2[63:48] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_WORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 32-bit integers from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_DWORDS(src1[127:0], src2[127:0]) { + dst[31:0] := src1[31:0] + dst[63:32] := src2[31:0] + dst[95:64] := src1[63:32] + dst[127:96] := src2[63:32] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_DWORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Integer + SSE2 + Swizzle + + + + Unpack and interleave 64-bit integers from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Add the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := a[63:0] + b[63:0] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Add packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] + b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Divide the lower double-precision (64-bit) floating-point element in "a" by the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := a[63:0] / b[63:0] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Divide packed double-precision (64-bit) floating-point elements in "a" by packed elements in "b", and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + dst[i+63:i] := a[i+63:i] / b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Special Math Functions + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the maximum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := MAX(a[63:0], b[63:0]) +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Special Math Functions + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := MAX(a[i+63:i], b[i+63:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Special Math Functions + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b", store the minimum value in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := MIN(a[63:0], b[63:0]) +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Special Math Functions + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := MIN(a[i+63:i], b[i+63:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Multiply the lower double-precision (64-bit) floating-point element in "a" and "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := a[63:0] * b[63:0] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Multiply packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] * b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Elementary Math Functions + + + + Compute the square root of the lower double-precision (64-bit) floating-point element in "b", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := SQRT(b[63:0]) +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Elementary Math Functions + + + Compute the square root of packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SQRT(a[i+63:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Subtract the lower double-precision (64-bit) floating-point element in "b" from the lower double-precision (64-bit) floating-point element in "a", store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := a[63:0] - b[63:0] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Arithmetic + + + + Subtract packed double-precision (64-bit) floating-point elements in "b" from packed double-precision (64-bit) floating-point elements in "a", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] - b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Logical + + + + Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] AND b[i+63:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Logical + + + + Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in "a" and then AND with "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ((NOT a[i+63:i]) AND b[i+63:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Logical + + + + Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] OR b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Logical + + + + Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in "a" and "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[i+63:i] XOR b[i+63:i] +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for equality, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] == b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] < b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] <= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] > b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] >= b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + dst[63:0] := (a[63:0] != NaN AND b[63:0] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + dst[63:0] := (a[63:0] == NaN OR b[63:0] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (a[63:0] != b[63:0]) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (!(a[63:0] < b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (!(a[63:0] <= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (!(a[63:0] > b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := (!(a[63:0] >= b[63:0])) ? 0xFFFFFFFFFFFFFFFF : 0 +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] == b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] < b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for less-than-or-equal, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] <= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] > b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for greater-than-or-equal, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] >= b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if neither is NaN, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] != NaN AND b[i+63:i] != NaN) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" to see if either is NaN, and store the results in "dst". + FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] == NaN OR b[i+63:i] == NaN) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-equal, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (a[i+63:i] != b[i+63:i]) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (!(a[i+63:i] < b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-less-than-or-equal, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (!(a[i+63:i] <= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (!(a[i+63:i] > b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Compare + + + + Compare packed double-precision (64-bit) floating-point elements in "a" and "b" for not-greater-than-or-equal, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := (!(a[i+63:i] >= b[i+63:i])) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

emmintrin.h

+ + + Floating Point + Flag + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for equality, and return the boolean result (0 or 1). + +RETURN ( a[63:0] == b[63:0] ) ? 1 : 0 + + +

emmintrin.h

+ + + Floating Point + Flag + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than, and return the boolean result (0 or 1). + +RETURN ( a[63:0] < b[63:0] ) ? 1 : 0 + + +

emmintrin.h

+ + + Floating Point + Flag + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for less-than-or-equal, and return the boolean result (0 or 1). + +RETURN ( a[63:0] <= b[63:0] ) ? 1 : 0 + + +

emmintrin.h

+ + + Floating Point + Flag + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than, and return the boolean result (0 or 1). + +RETURN ( a[63:0] > b[63:0] ) ? 1 : 0 + + +

emmintrin.h

+ + + Floating Point + Flag + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for greater-than-or-equal, and return the boolean result (0 or 1). + +RETURN ( a[63:0] >= b[63:0] ) ? 1 : 0 + + +

emmintrin.h

+ + + Floating Point + Flag + SSE2 + Compare + + + + Compare the lower double-precision (64-bit) floating-point element in "a" and "b" for not-equal, and return the boolean result (0 or 1). + +RETURN ( a[63:0] != b[63:0] ) ? 1 : 0 + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed single-precision (32-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_FP32(a[k+63:k]) +ENDFOR +dst[127:64] := 0 + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed double-precision (64-bit) floating-point elements, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 32*j + dst[i+63:i] := Convert_FP32_To_FP64(a[k+31:k]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32(a[k+63:k]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer, and store the result in "dst". + +dst[31:0] := Convert_FP64_To_Int32(a[63:0]) + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer, and store the result in "dst". + +dst[63:0] := Convert_FP64_To_Int64(a[63:0]) + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + + Convert the lower double-precision (64-bit) floating-point element in "b" to a single-precision (32-bit) floating-point element, store the result in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := Convert_FP64_To_FP32(b[63:0]) +dst[127:32] := a[127:32] +dst[MAX:128] := 0 + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + Copy the lower double-precision (64-bit) floating-point element of "a" to "dst". + +dst[63:0] := a[63:0] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Convert + + + + Convert the lower single-precision (32-bit) floating-point element in "b" to a double-precision (64-bit) floating-point element, store the result in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := Convert_FP32_To_FP64(b[31:0]) +dst[127:64] := a[127:64] +dst[MAX:128] := 0 + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert packed double-precision (64-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 1 + i := 32*j + k := 64*j + dst[i+31:i] := Convert_FP64_To_Int32_Truncate(a[k+63:k]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 32-bit integer with truncation, and store the result in "dst". + +dst[31:0] := Convert_FP64_To_Int32_Truncate(a[63:0]) + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert the lower double-precision (64-bit) floating-point element in "a" to a 64-bit integer with truncation, and store the result in "dst". + +dst[63:0] := Convert_FP64_To_Int64_Truncate(a[63:0]) + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32(a[i+31:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Convert + + + Convert packed single-precision (32-bit) floating-point elements in "a" to packed 32-bit integers with truncation, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + dst[i+31:i] := Convert_FP32_To_Int32_Truncate(a[i+31:i]) +ENDFOR + + +

emmintrin.h

+ + + Floating Point + SSE2 + Set + + + Copy double-precision (64-bit) floating-point element "a" to the lower element of "dst", and zero the upper element. + +dst[63:0] := a[63:0] +dst[127:64] := 0 + +

emmintrin.h

+ + + Floating Point + SSE2 + Set + + + Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR + +

emmintrin.h

+ + + Floating Point + SSE2 + Set + + + Broadcast double-precision (64-bit) floating-point value "a" to all elements of "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := a[63:0] +ENDFOR + +

emmintrin.h

+ + + Floating Point + SSE2 + Set + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values. + +dst[63:0] := e0 +dst[127:64] := e1 + +

emmintrin.h

+ + + Floating Point + SSE2 + Set + + + + Set packed double-precision (64-bit) floating-point elements in "dst" with the supplied values in reverse order. + +dst[63:0] := e1 +dst[127:64] := e0 + +

emmintrin.h

+ + + Floating Point + SSE2 + Set + + + Return vector of type __m128d with all elements set to zero. + +dst[MAX:0] := 0 + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst". + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + Load a double-precision (64-bit) floating-point element from memory into both elements of "dst". + +dst[63:0] := MEM[mem_addr+63:mem_addr] +dst[127:64] := MEM[mem_addr+63:mem_addr] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + Load 2 double-precision (64-bit) floating-point elements from memory into "dst" in reverse order. mem_addr must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[63:0] := MEM[mem_addr+127:mem_addr+64] +dst[127:64] := MEM[mem_addr+63:mem_addr] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into "dst". + "mem_addr" does not need to be aligned on any particular boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + Load a double-precision (64-bit) floating-point element from memory into the lower of "dst", and zero the upper element. "mem_addr" does not need to be aligned on any particular boundary. + +dst[63:0] := MEM[mem_addr+63:mem_addr] +dst[127:64] := 0 + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + + Load a double-precision (64-bit) floating-point element from memory into the upper element of "dst", and copy the lower element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary. + +dst[63:0] := a[63:0] +dst[127:64] := MEM[mem_addr+63:mem_addr] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Load + + + + Load a double-precision (64-bit) floating-point element from memory into the lower element of "dst", and copy the upper element from "a" to "dst". "mem_addr" does not need to be aligned on any particular boundary. + +dst[63:0] := MEM[mem_addr+63:mem_addr] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory using a non-temporal memory hint. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store the lower double-precision (64-bit) floating-point element from "a" into memory. "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store the lower double-precision (64-bit) floating-point element from "a" into 2 contiguous elements in memory. "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+63:mem_addr] := a[63:0] +MEM[mem_addr+127:mem_addr+64] := a[63:0] + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from "a" into memory. + "mem_addr" does not need to be aligned on any particular boundary. + +MEM[mem_addr+127:mem_addr] := a[127:0] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store 2 double-precision (64-bit) floating-point elements from "a" into memory in reverse order. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +MEM[mem_addr+63:mem_addr] := a[127:64] +MEM[mem_addr+127:mem_addr+64] := a[63:0] + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store the upper double-precision (64-bit) floating-point element from "a" into memory. + +MEM[mem_addr+63:mem_addr] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Store + + + + Store the lower double-precision (64-bit) floating-point element from "a" into memory. + +MEM[mem_addr+63:mem_addr] := a[63:0] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Swizzle + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the high half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_HIGH_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[127:64] + dst[127:64] := src2[127:64] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_HIGH_QWORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Floating Point + SSE2 + Swizzle + + + + Unpack and interleave double-precision (64-bit) floating-point elements from the low half of "a" and "b", and store the results in "dst". + +DEFINE INTERLEAVE_QWORDS(src1[127:0], src2[127:0]) { + dst[63:0] := src1[63:0] + dst[127:64] := src2[63:0] + RETURN dst[127:0] +} +dst[127:0] := INTERLEAVE_QWORDS(a[127:0], b[127:0]) + + +

emmintrin.h

+ + + Floating Point + SSE2 + Miscellaneous + + + Set each bit of mask "dst" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in "a". + +FOR j := 0 to 1 + i := j*64 + IF a[i+63] + dst[j] := 1 + ELSE + dst[j] := 0 + FI +ENDFOR +dst[MAX:2] := 0 + + +

emmintrin.h

+ + + Floating Point + SSE2 + Swizzle + + + + + Shuffle double-precision (64-bit) floating-point elements using the control in "imm8", and store the results in "dst". + +dst[63:0] := (imm8[0] == 0) ? a[63:0] : a[127:64] +dst[127:64] := (imm8[1] == 0) ? b[63:0] : b[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Move + + + + Move the lower double-precision (64-bit) floating-point element from "b" to the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := b[63:0] +dst[127:64] := a[127:64] + + +

emmintrin.h

+ + + Floating Point + SSE2 + Cast + + + Cast vector of type __m128d to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Cast + + + Cast vector of type __m128d to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

emmintrin.h

+ + + Floating Point + SSE2 + Cast + + + Cast vector of type __m128 to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

emmintrin.h

+ + + Floating Point + Integer + SSE2 + Cast + + + Cast vector of type __m128 to type __m128i. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

emmintrin.h

+ + + Floating Point + SSE2 + Cast + + + Cast vector of type __m128i to type __m128d. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

emmintrin.h

+ + + Floating Point + SSE2 + Cast + + + Cast vector of type __m128i to type __m128. This intrinsic is only used for compilation and does not generate any instructions, thus it has zero latency. +

emmintrin.h

+ + + Floating Point + SSE3 + Arithmetic + + + + Alternatively add and subtract packed single-precision (32-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF ((j & 1) == 0) + dst[i+31:i] := a[i+31:i] - b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + b[i+31:i] + FI +ENDFOR + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Arithmetic + + + + Alternatively add and subtract packed double-precision (64-bit) floating-point elements in "a" to/from packed elements in "b", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF ((j & 1) == 0) + dst[i+63:i] := a[i+63:i] - b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + b[i+63:i] + FI +ENDFOR + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Arithmetic + + + + Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[63:0] := a[127:64] + a[63:0] +dst[127:64] := b[127:64] + b[63:0] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Arithmetic + + + + Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[31:0] := a[63:32] + a[31:0] +dst[63:32] := a[127:96] + a[95:64] +dst[95:64] := b[63:32] + b[31:0] +dst[127:96] := b[127:96] + b[95:64] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Arithmetic + + + + Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[63:0] := a[63:0] - a[127:64] +dst[127:64] := b[63:0] - b[127:64] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Arithmetic + + + + Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in "a" and "b", and pack the results in "dst". + +dst[31:0] := a[31:0] - a[63:32] +dst[63:32] := a[95:64] - a[127:96] +dst[95:64] := b[31:0] - b[63:32] +dst[127:96] := b[95:64] - b[127:96] + + +

pmmintrin.h

+ + + Integer + SSE3 + Load + + + Load 128-bits of integer data from unaligned memory into "dst". This intrinsic may perform better than "_mm_loadu_si128" when the data crosses a cache line boundary. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Move + + + Duplicate the low double-precision (64-bit) floating-point element from "a", and store the results in "dst". + +dst[63:0] := a[63:0] +dst[127:64] := a[63:0] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Load + + + Load a double-precision (64-bit) floating-point element from memory into both elements of "dst". + +dst[63:0] := MEM[mem_addr+63:mem_addr] +dst[127:64] := MEM[mem_addr+63:mem_addr] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Move + + + Duplicate odd-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst". + +dst[31:0] := a[63:32] +dst[63:32] := a[63:32] +dst[95:64] := a[127:96] +dst[127:96] := a[127:96] + + +

pmmintrin.h

+ + + Floating Point + SSE3 + Move + + + Duplicate even-indexed single-precision (32-bit) floating-point elements from "a", and store the results in "dst". + +dst[31:0] := a[31:0] +dst[63:32] := a[31:0] +dst[95:64] := a[95:64] +dst[127:96] := a[95:64] + + +

pmmintrin.h

+ + + Floating Point + SSE4.1 + Swizzle + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF imm8[j] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Swizzle + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF imm8[j] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Swizzle + + + + + Blend packed double-precision (64-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + IF mask[i+63] + dst[i+63:i] := b[i+63:i] + ELSE + dst[i+63:i] := a[i+63:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Swizzle + + + + + Blend packed single-precision (32-bit) floating-point elements from "a" and "b" using "mask", and store the results in "dst". + +FOR j := 0 to 3 + i := j*32 + IF mask[i+31] + dst[i+31:i] := b[i+31:i] + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + + Blend packed 8-bit integers from "a" and "b" using "mask", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + IF mask[i+7] + dst[i+7:i] := b[i+7:i] + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + + Blend packed 16-bit integers from "a" and "b" using control mask "imm8", and store the results in "dst". + +FOR j := 0 to 7 + i := j*16 + IF imm8[j] + dst[i+15:i] := b[i+15:i] + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Arithmetic + + + + + Conditionally multiply the packed double-precision (64-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8". + +DEFINE DP(a[127:0], b[127:0], imm8[7:0]) { + FOR j := 0 to 1 + i := j*64 + IF imm8[(4+j)%8] + temp[i+63:i] := a[i+63:i] * b[i+63:i] + ELSE + temp[i+63:i] := 0.0 + FI + ENDFOR + + sum[63:0] := temp[127:64] + temp[63:0] + + FOR j := 0 to 1 + i := j*64 + IF imm8[j%8] + tmpdst[i+63:i] := sum[63:0] + ELSE + tmpdst[i+63:i] := 0.0 + FI + ENDFOR + RETURN tmpdst[127:0] +} +dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0]) + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Arithmetic + + + + + Conditionally multiply the packed single-precision (32-bit) floating-point elements in "a" and "b" using the high 4 bits in "imm8", sum the four products, and conditionally store the sum in "dst" using the low 4 bits of "imm8". + +DEFINE DP(a[127:0], b[127:0], imm8[7:0]) { + FOR j := 0 to 3 + i := j*32 + IF imm8[(4+j)%8] + temp[i+31:i] := a[i+31:i] * b[i+31:i] + ELSE + temp[i+31:i] := 0 + FI + ENDFOR + + sum[31:0] := (temp[127:96] + temp[95:64]) + (temp[63:32] + temp[31:0]) + + FOR j := 0 to 3 + i := j*32 + IF imm8[j%8] + tmpdst[i+31:i] := sum[31:0] + ELSE + tmpdst[i+31:i] := 0 + FI + ENDFOR + RETURN tmpdst[127:0] +} +dst[127:0] := DP(a[127:0], b[127:0], imm8[7:0]) + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Swizzle + + + + Extract a single-precision (32-bit) floating-point element from "a", selected with "imm8", and store the result in "dst". + +dst[31:0] := (a[127:0] >> (imm8[1:0] * 32))[31:0] + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + Extract an 8-bit integer from "a", selected with "imm8", and store the result in the lower element of "dst". + +dst[7:0] := (a[127:0] >> (imm8[3:0] * 8))[7:0] +dst[31:8] := 0 + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + Extract a 32-bit integer from "a", selected with "imm8", and store the result in "dst". + +dst[31:0] := (a[127:0] >> (imm8[1:0] * 32))[31:0] + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + Extract a 64-bit integer from "a", selected with "imm8", and store the result in "dst". + +dst[63:0] := (a[127:0] >> (imm8[0] * 64))[63:0] + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Swizzle + + + + + Copy "a" to "tmp", then insert a single-precision (32-bit) floating-point element from "b" into "tmp" using the control in "imm8". Store "tmp" to "dst" using the mask in "imm8" (elements are zeroed out when the corresponding bit is set). + +tmp2[127:0] := a[127:0] +CASE (imm8[7:6]) OF +0: tmp1[31:0] := b[31:0] +1: tmp1[31:0] := b[63:32] +2: tmp1[31:0] := b[95:64] +3: tmp1[31:0] := b[127:96] +ESAC +CASE (imm8[5:4]) OF +0: tmp2[31:0] := tmp1[31:0] +1: tmp2[63:32] := tmp1[31:0] +2: tmp2[95:64] := tmp1[31:0] +3: tmp2[127:96] := tmp1[31:0] +ESAC +FOR j := 0 to 3 + i := j*32 + IF imm8[j%8] + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := tmp2[i+31:i] + FI +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + + Copy "a" to "dst", and insert the lower 8-bit integer from "i" into "dst" at the location specified by "imm8". + +dst[127:0] := a[127:0] +sel := imm8[3:0]*8 +dst[sel+7:sel] := i[7:0] + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + + Copy "a" to "dst", and insert the 32-bit integer "i" into "dst" at the location specified by "imm8". + +dst[127:0] := a[127:0] +sel := imm8[1:0]*32 +dst[sel+31:sel] := i[31:0] + + +

smmintrin.h

+ + + Integer + SSE4.1 + Swizzle + + + + + Copy "a" to "dst", and insert the 64-bit integer "i" into "dst" at the location specified by "imm8". + +dst[127:0] := a[127:0] +sel := imm8[0]*64 +dst[sel+63:sel] := i[63:0] + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := MAX(a[i+7:i], b[i+7:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := MAX(a[i+31:i], b[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed maximum values in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := MAX(a[i+15:i], b[i+15:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed signed 8-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := MIN(a[i+7:i], b[i+7:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed signed 32-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed unsigned 32-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := MIN(a[i+31:i], b[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Special Math Functions + + + + Compare packed unsigned 16-bit integers in "a" and "b", and store packed minimum values in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := MIN(a[i+15:i], b[i+15:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + Miscellaneous + + + + Convert packed signed 32-bit integers from "a" and "b" to packed 16-bit integers using unsigned saturation, and store the results in "dst". + +dst[15:0] := SaturateU16(a[31:0]) +dst[31:16] := SaturateU16(a[63:32]) +dst[47:32] := SaturateU16(a[95:64]) +dst[63:48] := SaturateU16(a[127:96]) +dst[79:64] := SaturateU16(b[31:0]) +dst[95:80] := SaturateU16(b[63:32]) +dst[111:96] := SaturateU16(b[95:64]) +dst[127:112] := SaturateU16(b[127:96]) + + +

smmintrin.h

+ + + Integer + SSE4.1 + Compare + + + + Compare packed 64-bit integers in "a" and "b" for equality, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ( a[i+63:i] == b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Sign extend packed 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + l := j*16 + dst[l+15:l] := SignExtend16(a[i+7:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Sign extend packed 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 8*j + dst[i+31:i] := SignExtend32(a[k+7:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Sign extend packed 8-bit integers in the low 8 bytes of "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 8*j + dst[i+63:i] := SignExtend64(a[k+7:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Sign extend packed 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 16*j + dst[i+31:i] := SignExtend32(a[k+15:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Sign extend packed 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 16*j + dst[i+63:i] := SignExtend64(a[k+15:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Sign extend packed 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 32*j + dst[i+63:i] := SignExtend64(a[k+31:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Zero extend packed unsigned 8-bit integers in "a" to packed 16-bit integers, and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + l := j*16 + dst[l+15:l] := ZeroExtend16(a[i+7:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Zero extend packed unsigned 8-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 8*j + dst[i+31:i] := ZeroExtend32(a[k+7:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Zero extend packed unsigned 8-bit integers in the low 8 byte sof "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 8*j + dst[i+63:i] := ZeroExtend64(a[k+7:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Zero extend packed unsigned 16-bit integers in "a" to packed 32-bit integers, and store the results in "dst". + +FOR j := 0 to 3 + i := 32*j + k := 16*j + dst[i+31:i] := ZeroExtend32(a[k+15:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Zero extend packed unsigned 16-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 16*j + dst[i+63:i] := ZeroExtend64(a[k+15:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Convert + + + Zero extend packed unsigned 32-bit integers in "a" to packed 64-bit integers, and store the results in "dst". + +FOR j := 0 to 1 + i := 64*j + k := 32*j + dst[i+63:i] := ZeroExtend64(a[k+31:k]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Arithmetic + + + + Multiply the low signed 32-bit integers from each packed 64-bit element in "a" and "b", and store the signed 64-bit results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := SignExtend64(a[i+31:i]) * SignExtend64(b[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Integer + SSE4.1 + Arithmetic + + + + Multiply the packed 32-bit integers in "a" and "b", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in "dst". + +FOR j := 0 to 3 + i := j*32 + tmp[63:0] := a[i+31:i] * b[i+31:i] + dst[i+31:i] := tmp[31:0] +ENDFOR + + +

smmintrin.h

+ + + Integer + Flag + SSE4.1 + Logical + + + + Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "ZF" value. + +IF ((a[127:0] AND b[127:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[127:0]) AND b[127:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +RETURN ZF + + +

smmintrin.h

+ + + Integer + Flag + SSE4.1 + Logical + + + + Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return the "CF" value. + +IF ((a[127:0] AND b[127:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[127:0]) AND b[127:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +RETURN CF + + +

smmintrin.h

+ + + Integer + Flag + SSE4.1 + Logical + + + + Compute the bitwise AND of 128 bits (representing integer data) in "a" and "b", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "b", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +IF ((a[127:0] AND b[127:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[127:0]) AND b[127:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

smmintrin.h

+ + + Integer + Flag + SSE4.1 + Logical + + + + Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and return 1 if the result is zero, otherwise return 0. + +IF ((a[127:0] AND mask[127:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +dst := ZF + + +

smmintrin.h

+ + + Integer + Flag + SSE4.1 + Logical + + + + Compute the bitwise AND of 128 bits (representing integer data) in "a" and "mask", and set "ZF" to 1 if the result is zero, otherwise set "ZF" to 0. Compute the bitwise NOT of "a" and then AND with "mask", and set "CF" to 1 if the result is zero, otherwise set "CF" to 0. Return 1 if both the "ZF" and "CF" values are zero, otherwise return 0. + +IF ((a[127:0] AND mask[127:0]) == 0) + ZF := 1 +ELSE + ZF := 0 +FI +IF (((NOT a[127:0]) AND mask[127:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +IF (ZF == 0 && CF == 0) + dst := 1 +ELSE + dst := 0 +FI + + +

smmintrin.h

+ + + Integer + Flag + SSE4.1 + Logical + + + Compute the bitwise NOT of "a" and then AND with a 128-bit vector containing all 1's, and return 1 if the result is zero, otherwise return 0. + +FOR j := 0 to 127 + tmp[j] := 1 +ENDFOR +IF (((NOT a[127:0]) AND tmp[127:0]) == 0) + CF := 1 +ELSE + CF := 0 +FI +dst := CF + + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + Round the packed double-precision (64-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed double-precision floating-point elements in "dst". + [round_note] + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ROUND(a[i+63:i], rounding) +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" down to an integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := FLOOR(a[i+63:i]) +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + Round the packed double-precision (64-bit) floating-point elements in "a" up to an integer value, and store the results as packed double-precision floating-point elements in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := CEIL(a[i+63:i]) +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + Round the packed single-precision (32-bit) floating-point elements in "a" using the "rounding" parameter, and store the results as packed single-precision floating-point elements in "dst". + [round_note] + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ROUND(a[i+31:i], rounding) +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" down to an integer value, and store the results as packed single-precision floating-point elements in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := FLOOR(a[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + Round the packed single-precision (32-bit) floating-point elements in "a" up to an integer value, and store the results as packed single-precision floating-point elements in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := CEIL(a[i+31:i]) +ENDFOR + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + + Round the lower double-precision (64-bit) floating-point element in "b" using the "rounding" parameter, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + [round_note] + +dst[63:0] := ROUND(b[63:0], rounding) +dst[127:64] := a[127:64] + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + Round the lower double-precision (64-bit) floating-point element in "b" down to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := FLOOR(b[63:0]) +dst[127:64] := a[127:64] + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + Round the lower double-precision (64-bit) floating-point element in "b" up to an integer value, store the result as a double-precision floating-point element in the lower element of "dst", and copy the upper element from "a" to the upper element of "dst". + +dst[63:0] := CEIL(b[63:0]) +dst[127:64] := a[127:64] + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + + Round the lower single-precision (32-bit) floating-point element in "b" using the "rounding" parameter, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + [round_note] + +dst[31:0] := ROUND(b[31:0], rounding) +dst[127:32] := a[127:32] + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + Round the lower single-precision (32-bit) floating-point element in "b" down to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := FLOOR(b[31:0]) +dst[127:32] := a[127:32] + + +

smmintrin.h

+ + + Floating Point + SSE4.1 + Special Math Functions + + + + Round the lower single-precision (32-bit) floating-point element in "b" up to an integer value, store the result as a single-precision floating-point element in the lower element of "dst", and copy the upper 3 packed elements from "a" to the upper elements of "dst". + +dst[31:0] := CEIL(b[31:0]) +dst[127:32] := a[127:32] + + +

smmintrin.h

+ + + Integer + SSE4.1 + Miscellaneous + + + Horizontally compute the minimum amongst the packed unsigned 16-bit integers in "a", store the minimum and index in "dst", and zero the remaining bits in "dst". + +index[2:0] := 0 +min[15:0] := a[15:0] +FOR j := 0 to 7 + i := j*16 + IF a[i+15:i] < min[15:0] + index[2:0] := j + min[15:0] := a[i+15:i] + FI +ENDFOR +dst[15:0] := min[15:0] +dst[18:16] := index[2:0] +dst[127:19] := 0 + + +

smmintrin.h

+ + + Integer + SSE4.1 + Arithmetic + Miscellaneous + + + + + Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in "a" compared to those in "b", and store the 16-bit results in "dst". + Eight SADs are performed using one quadruplet from "b" and eight quadruplets from "a". One quadruplet is selected from "b" starting at on the offset specified in "imm8". Eight quadruplets are formed from sequential 8-bit integers selected from "a" starting at the offset specified in "imm8". + +DEFINE MPSADBW(a[127:0], b[127:0], imm8[2:0]) { + a_offset := imm8[2]*32 + b_offset := imm8[1:0]*32 + FOR j := 0 to 7 + i := j*8 + k := a_offset+i + l := b_offset + tmp[i*2+15:i*2] := ABS(Signed(a[k+7:k] - b[l+7:l])) + ABS(Signed(a[k+15:k+8] - b[l+15:l+8])) + \ + ABS(Signed(a[k+23:k+16] - b[l+23:l+16])) + ABS(Signed(a[k+31:k+24] - b[l+31:l+24])) + ENDFOR + RETURN tmp[127:0] +} +dst[127:0] := MPSADBW(a[127:0], b[127:0], imm8[2:0]) + + +

smmintrin.h

+ + + Integer + SSE4.1 + Load + + + Load 128-bits of integer data from memory into "dst" using a non-temporal memory hint. + "mem_addr" must be aligned on a 16-byte boundary or a general-protection exception may be generated. + +dst[127:0] := MEM[mem_addr+127:mem_addr] + + +

smmintrin.h

+ + + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated mask in "dst". + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF a[m+size-1:m] == 0 + aInvalid := 1 + FI + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +bInvalid := 0 +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + IF bInvalid // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +IF imm8[6] // byte / word mask + FOR i := 0 to UpperBound + j := i*size + IF IntRes2[i] + dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF) + ELSE + dst[j+size-1:j] := 0 + FI + ENDFOR +ELSE // bit mask + dst[UpperBound:0] := IntRes2[UpperBound:0] + dst[127:UpperBound+1] := 0 +FI + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and store the generated index in "dst". + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF a[m+size-1:m] == 0 + aInvalid := 1 + FI + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +bInvalid := 0 +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + IF bInvalid // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +IF imm8[6] // most significant bit + tmp := UpperBound + dst := tmp + DO WHILE ((tmp >= 0) AND a[tmp] == 0) + tmp := tmp - 1 + dst := tmp + OD +ELSE // least significant bit + tmp := 0 + dst := tmp + DO WHILE ((tmp <= UpperBound) AND a[tmp] == 0) + tmp := tmp + 1 + dst := tmp + OD +FI + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +bInvalid := 0 +FOR j := 0 to UpperBound + n := j*size + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI +ENDFOR +dst := bInvalid + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF a[m+size-1:m] == 0 + aInvalid := 1 + FI + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +bInvalid := 0 +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + IF bInvalid // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +dst := (IntRes2 != 0) + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +aInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + IF a[m+size-1:m] == 0 + aInvalid := 1 + FI +ENDFOR +dst := aInvalid + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns bit 0 of the resulting bit mask. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF a[m+size-1:m] == 0 + aInvalid := 1 + FI + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +bInvalid := 0 +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + IF bInvalid // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +dst := IntRes2[0] + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + Compare packed strings with implicit lengths in "a" and "b" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF a[m+size-1:m] == 0 + aInvalid := 1 + FI + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +bInvalid := 0 +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF b[n+size-1:n] == 0 + bInvalid := 1 + FI + IF bInvalid // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +dst := (IntRes2 == 0) AND bInvalid + + +

nmmintrin.h

+ + + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated mask in "dst". + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF i == la + aInvalid := 1 + FI + IF j == lb + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF i >= lb // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +IF imm8[6] // byte / word mask + FOR i := 0 to UpperBound + j := i*size + IF IntRes2[i] + dst[j+size-1:j] := (imm8[0] ? 0xFF : 0xFFFF) + ELSE + dst[j+size-1:j] := 0 + FI + ENDFOR +ELSE // bit mask + dst[UpperBound:0] := IntRes2[UpperBound:0] + dst[127:UpperBound+1] := 0 +FI + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and store the generated index in "dst". + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF i == la + aInvalid := 1 + FI + IF j == lb + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF i >= lb // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +IF imm8[6] // most significant bit + tmp := UpperBound + dst := tmp + DO WHILE ((tmp >= 0) AND a[tmp] == 0) + tmp := tmp - 1 + dst := tmp + OD +ELSE // least significant bit + tmp := 0 + dst := tmp + DO WHILE ((tmp <= UpperBound) AND a[tmp] == 0) + tmp := tmp + 1 + dst := tmp + OD +FI + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "b" was null, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +dst := (lb <= UpperBound) + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if the resulting mask was non-zero, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF i == la + aInvalid := 1 + FI + IF j == lb + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF i >= lb // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +dst := (IntRes2 != 0) + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if any character in "a" was null, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +dst := (la <= UpperBound) + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns bit 0 of the resulting bit mask. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF i == la + aInvalid := 1 + FI + IF j == lb + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF i >= lb // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +dst := IntRes2[0] + + +

nmmintrin.h

+ + + Flag + SSE4.2 + String Compare + + + + + + + Compare packed strings in "a" and "b" with lengths "la" and "lb" using the control in "imm8", and returns 1 if "b" did not contain a null character and the resulting mask was zero, and 0 otherwise. + [strcmp_note] + +size := (imm8[0] ? 16 : 8) // 8 or 16-bit characters +UpperBound := (128 / size) - 1 +BoolRes := 0 +// compare all characters +aInvalid := 0 +bInvalid := 0 +FOR i := 0 to UpperBound + m := i*size + FOR j := 0 to UpperBound + n := j*size + BoolRes.word[i].bit[j] := (a[m+size-1:m] == b[n+size-1:n]) ? 1 : 0 + + // invalidate characters after EOS + IF i == la + aInvalid := 1 + FI + IF j == lb + bInvalid := 1 + FI + + // override comparisons for invalid characters + CASE (imm8[3:2]) OF + 0: // equal any + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 1: // ranges + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + FI + 2: // equal each + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + 3: // equal ordered + IF (!aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 0 + ELSE IF (aInvalid && !bInvalid) + BoolRes.word[i].bit[j] := 1 + ELSE IF (aInvalid && bInvalid) + BoolRes.word[i].bit[j] := 1 + FI + ESAC + ENDFOR +ENDFOR +// aggregate results +CASE (imm8[3:2]) OF +0: // equal any + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR BoolRes.word[i].bit[j] + ENDFOR + ENDFOR +1: // ranges + IntRes1 := 0 + FOR i := 0 to UpperBound + FOR j := 0 to UpperBound + IntRes1[i] := IntRes1[i] OR (BoolRes.word[i].bit[j] AND BoolRes.word[i].bit[j+1]) + j += 2 + ENDFOR + ENDFOR +2: // equal each + IntRes1 := 0 + FOR i := 0 to UpperBound + IntRes1[i] := BoolRes.word[i].bit[i] + ENDFOR +3: // equal ordered + IntRes1 := (imm8[0] ? 0xFF : 0xFFFF) + FOR i := 0 to UpperBound + k := i + FOR j := 0 to UpperBound-i + IntRes1[i] := IntRes1[i] AND BoolRes.word[k].bit[j] + k := k+1 + ENDFOR + ENDFOR +ESAC +// optionally negate results +FOR i := 0 to UpperBound + IF imm8[4] + IF imm8[5] // only negate valid + IF i >= lb // invalid, don't negate + IntRes2[i] := IntRes1[i] + ELSE // valid, negate + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // negate all + IntRes2[i] := -1 XOR IntRes1[i] + FI + ELSE // don't negate + IntRes2[i] := IntRes1[i] + FI +ENDFOR +// output +dst := (IntRes2 == 0) AND (lb > UpperBound) + + +

nmmintrin.h

+ + + Integer + SSE4.2 + Compare + + + + Compare packed signed 64-bit integers in "a" and "b" for greater-than, and store the results in "dst". + +FOR j := 0 to 1 + i := j*64 + dst[i+63:i] := ( a[i+63:i] > b[i+63:i] ) ? 0xFFFFFFFFFFFFFFFF : 0 +ENDFOR + + +

nmmintrin.h

+ + + Integer + SSE4.2 + Cryptography + + + + Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 8-bit integer "v", and stores the result in "dst". + tmp1[7:0] := v[0:7] // bit reflection +tmp2[31:0] := crc[0:31] // bit reflection +tmp3[39:0] := tmp1[7:0] << 32 +tmp4[39:0] := tmp2[31:0] << 8 +tmp5[39:0] := tmp3[39:0] XOR tmp4[39:0] +tmp6[31:0] := MOD2(tmp5[39:0], 0x11EDC6F41) // remainder from polynomial division modulus 2 +dst[31:0] := tmp6[0:31] // bit reflection + + +

nmmintrin.h

+ + + Integer + SSE4.2 + Cryptography + + + + Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 16-bit integer "v", and stores the result in "dst". + tmp1[15:0] := v[0:15] // bit reflection +tmp2[31:0] := crc[0:31] // bit reflection +tmp3[47:0] := tmp1[15:0] << 32 +tmp4[47:0] := tmp2[31:0] << 16 +tmp5[47:0] := tmp3[47:0] XOR tmp4[47:0] +tmp6[31:0] := MOD2(tmp5[47:0], 0x11EDC6F41) // remainder from polynomial division modulus 2 +dst[31:0] := tmp6[0:31] // bit reflection + + +

nmmintrin.h

+ + + Integer + SSE4.2 + Cryptography + + + + Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 32-bit integer "v", and stores the result in "dst". + tmp1[31:0] := v[0:31] // bit reflection +tmp2[31:0] := crc[0:31] // bit reflection +tmp3[63:0] := tmp1[31:0] << 32 +tmp4[63:0] := tmp2[31:0] << 32 +tmp5[63:0] := tmp3[63:0] XOR tmp4[63:0] +tmp6[31:0] := MOD2(tmp5[63:0], 0x11EDC6F41) // remainder from polynomial division modulus 2 +dst[31:0] := tmp6[0:31] // bit reflection + + +

nmmintrin.h

+ + + Integer + SSE4.2 + Cryptography + + + + Starting with the initial value in "crc", accumulates a CRC32 value for unsigned 64-bit integer "v", and stores the result in "dst". + tmp1[63:0] := v[0:63] // bit reflection +tmp2[31:0] := crc[0:31] // bit reflection +tmp3[95:0] := tmp1[31:0] << 32 +tmp4[95:0] := tmp2[63:0] << 64 +tmp5[95:0] := tmp3[95:0] XOR tmp4[95:0] +tmp6[31:0] := MOD2(tmp5[95:0], 0x11EDC6F41) // remainder from polynomial division modulus 2 +dst[31:0] := tmp6[0:31] // bit reflection + + +

nmmintrin.h

+ + + Integer + SSSE3 + Special Math Functions + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 7 + i := j*8 + dst[i+7:i] := ABS(Int(a[i+7:i])) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Special Math Functions + + + Compute the absolute value of packed signed 8-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 15 + i := j*8 + dst[i+7:i] := ABS(a[i+7:i]) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Special Math Functions + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := ABS(Int(a[i+15:i])) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Special Math Functions + + + Compute the absolute value of packed signed 16-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := ABS(a[i+15:i]) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Special Math Functions + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 1 + i := j*32 + dst[i+31:i] := ABS(a[i+31:i]) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Special Math Functions + + + Compute the absolute value of packed signed 32-bit integers in "a", and store the unsigned results in "dst". + +FOR j := 0 to 3 + i := j*32 + dst[i+31:i] := ABS(a[i+31:i]) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Swizzle + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst". + +FOR j := 0 to 15 + i := j*8 + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[3:0] := b[i+3:i] + dst[i+7:i] := a[index*8+7:index*8] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Swizzle + + + + Shuffle packed 8-bit integers in "a" according to shuffle control mask in the corresponding 8-bit element of "b", and store the results in "dst". + +FOR j := 0 to 7 + i := j*8 + IF b[i+7] == 1 + dst[i+7:i] := 0 + ELSE + index[2:0] := b[i+2:i] + dst[i+7:i] := a[index*8+7:index*8] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Miscellaneous + + + + + Concatenate 16-byte blocks in "a" and "b" into a 32-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst". + +tmp[255:0] := ((a[127:0] << 128)[255:0] OR b[127:0]) >> (imm8*8) +dst[127:0] := tmp[127:0] + + +

tmmintrin.h

+ + + Integer + SSSE3 + Miscellaneous + + + + + Concatenate 8-byte blocks in "a" and "b" into a 16-byte temporary result, shift the result right by "imm8" bytes, and store the low 16 bytes in "dst". + +tmp[127:0] := ((a[63:0] << 64)[127:0] OR b[63:0]) >> (imm8*8) +dst[63:0] := tmp[63:0] + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Horizontally add adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst". + +dst[15:0] := a[31:16] + a[15:0] +dst[31:16] := a[63:48] + a[47:32] +dst[47:32] := a[95:80] + a[79:64] +dst[63:48] := a[127:112] + a[111:96] +dst[79:64] := b[31:16] + b[15:0] +dst[95:80] := b[63:48] + b[47:32] +dst[111:96] := b[95:80] + b[79:64] +dst[127:112] := b[127:112] + b[111:96] + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Horizontally add adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst". + +dst[15:0] := Saturate16(a[31:16] + a[15:0]) +dst[31:16] := Saturate16(a[63:48] + a[47:32]) +dst[47:32] := Saturate16(a[95:80] + a[79:64]) +dst[63:48] := Saturate16(a[127:112] + a[111:96]) +dst[79:64] := Saturate16(b[31:16] + b[15:0]) +dst[95:80] := Saturate16(b[63:48] + b[47:32]) +dst[111:96] := Saturate16(b[95:80] + b[79:64]) +dst[127:112] := Saturate16(b[127:112] + b[111:96]) + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Horizontally add adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst". + +dst[31:0] := a[63:32] + a[31:0] +dst[63:32] := a[127:96] + a[95:64] +dst[95:64] := b[63:32] + b[31:0] +dst[127:96] := b[127:96] + b[95:64] + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Horizontally subtract adjacent pairs of 16-bit integers in "a" and "b", and pack the signed 16-bit results in "dst". + +dst[15:0] := a[15:0] - a[31:16] +dst[31:16] := a[47:32] - a[63:48] +dst[47:32] := a[79:64] - a[95:80] +dst[63:48] := a[111:96] - a[127:112] +dst[79:64] := b[15:0] - b[31:16] +dst[95:80] := b[47:32] - b[63:48] +dst[111:96] := b[79:64] - b[95:80] +dst[127:112] := b[111:96] - b[127:112] + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Horizontally subtract adjacent pairs of signed 16-bit integers in "a" and "b" using saturation, and pack the signed 16-bit results in "dst". + +dst[15:0] := Saturate16(a[15:0] - a[31:16]) +dst[31:16] := Saturate16(a[47:32] - a[63:48]) +dst[47:32] := Saturate16(a[79:64] - a[95:80]) +dst[63:48] := Saturate16(a[111:96] - a[127:112]) +dst[79:64] := Saturate16(b[15:0] - b[31:16]) +dst[95:80] := Saturate16(b[47:32] - b[63:48]) +dst[111:96] := Saturate16(b[79:64] - b[95:80]) +dst[127:112] := Saturate16(b[111:96] - b[127:112]) + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Horizontally subtract adjacent pairs of 32-bit integers in "a" and "b", and pack the signed 32-bit results in "dst". + +dst[31:0] := a[31:0] - a[63:32] +dst[63:32] := a[95:64] - a[127:96] +dst[95:64] := b[31:0] - b[63:32] +dst[127:96] := b[95:64] - b[127:96] + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst". + +FOR j := 0 to 7 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Vertically multiply each unsigned 8-bit integer from "a" with the corresponding signed 8-bit integer from "b", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in "dst". + +FOR j := 0 to 3 + i := j*16 + dst[i+15:i] := Saturate16( a[i+15:i+8]*b[i+15:i+8] + a[i+7:i]*b[i+7:i] ) +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst". + +FOR j := 0 to 7 + i := j*16 + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Multiply packed signed 16-bit integers in "a" and "b", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to "dst". + +FOR j := 0 to 3 + i := j*16 + tmp[31:0] := ((SignExtend32(a[i+15:i]) * SignExtend32(b[i+15:i])) >> 14) + 1 + dst[i+15:i] := tmp[16:1] +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 15 + i := j*8 + IF b[i+7:i] < 0 + dst[i+7:i] := -(a[i+7:i]) + ELSE IF b[i+7:i] == 0 + dst[i+7:i] := 0 + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 7 + i := j*16 + IF b[i+15:i] < 0 + dst[i+15:i] := -(a[i+15:i]) + ELSE IF b[i+15:i] == 0 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 3 + i := j*32 + IF b[i+31:i] < 0 + dst[i+31:i] := -(a[i+31:i]) + ELSE IF b[i+31:i] == 0 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Negate packed 8-bit integers in "a" when the corresponding signed 8-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 7 + i := j*8 + IF b[i+7:i] < 0 + dst[i+7:i] := -(a[i+7:i]) + ELSE IF b[i+7:i] == 0 + dst[i+7:i] := 0 + ELSE + dst[i+7:i] := a[i+7:i] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Negate packed 16-bit integers in "a" when the corresponding signed 16-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 3 + i := j*16 + IF b[i+15:i] < 0 + dst[i+15:i] := -(a[i+15:i]) + ELSE IF b[i+15:i] == 0 + dst[i+15:i] := 0 + ELSE + dst[i+15:i] := a[i+15:i] + FI +ENDFOR + + +

tmmintrin.h

+ + + Integer + SSSE3 + Arithmetic + + + + Negate packed 32-bit integers in "a" when the corresponding signed 32-bit integer in "b" is negative, and store the results in "dst". Element in "dst" are zeroed out when the corresponding element in "b" is zero. + +FOR j := 0 to 1 + i := j*32 + IF b[i+31:i] < 0 + dst[i+31:i] := -(a[i+31:i]) + ELSE IF b[i+31:i] == 0 + dst[i+31:i] := 0 + ELSE + dst[i+31:i] := a[i+31:i] + FI +ENDFOR + + +

tmmintrin.h

+ + + TSC + General Support + + + Copy the current 64-bit value of the processor's time-stamp counter into "dst". + dst[63:0] := TimeStampCounter + + +

immintrin.h

+ + + TSXLDTRK + Miscellaneous + + Mark the start of a TSX (HLE/RTM) suspend load address tracking region. If this is used inside a transactional region, subsequent loads are not added to the read set of the transaction. If this is used inside a suspend load address tracking region it will cause transaction abort. If this is used outside of a transactional region it behaves like a NOP. + +

immintrin.h

+ + + TSXLDTRK + Miscellaneous + + Mark the end of a TSX (HLE/RTM) suspend load address tracking region. If this is used inside a suspend load address tracking region it will end the suspend region and all following load addresses will be added to the transaction read set. If this is used inside an active transaction but not in a suspend region it will cause transaction abort. If this is used outside of a transactional region it behaves like a NOP. + +

immintrin.h

+ + + Integer + AVX512VL + VAES + Cryptography + + + + Perform the last round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"." + FOR j := 0 to 1 + i := j*128 + a[i+127:i] := ShiftRows(a[i+127:i]) + a[i+127:i] := SubBytes(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + VAES + Cryptography + + + + Perform one round of an AES encryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst"." + FOR j := 0 to 1 + i := j*128 + a[i+127:i] := ShiftRows(a[i+127:i]) + a[i+127:i] := SubBytes(a[i+127:i]) + a[i+127:i] := MixColumns(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + VAES + Cryptography + + + + Perform the last round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst". + FOR j := 0 to 1 + i := j*128 + a[i+127:i] := InvShiftRows(a[i+127:i]) + a[i+127:i] := InvSubBytes(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + VAES + Cryptography + + + + Perform one round of an AES decryption flow on data (state) in "a" using the round key in "RoundKey", and store the results in "dst". + FOR j := 0 to 1 + i := j*128 + a[i+127:i] := InvShiftRows(a[i+127:i]) + a[i+127:i] := InvSubBytes(a[i+127:i]) + a[i+127:i] := InvMixColumns(a[i+127:i]) + dst[i+127:i] := a[i+127:i] XOR RoundKey[i+127:i] +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Integer + VPCLMULQDQ + Application-Targeted + + + + + Carry-less multiplication of one quadword of + 'b' by one quadword of 'c', stores + the 128-bit result in 'dst'. The immediate 'Imm8' is + used to determine which quadwords of 'b' + and 'c' should be used. + +DEFINE PCLMUL128(X,Y) { + FOR i := 0 to 63 + TMP[i] := X[ 0 ] and Y[ i ] + FOR j := 1 to i + TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ]) + ENDFOR + DEST[ i ] := TMP[ i ] + ENDFOR + FOR i := 64 to 126 + TMP[i] := 0 + FOR j := i - 63 to 63 + TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ]) + ENDFOR + DEST[ i ] := TMP[ i ] + ENDFOR + DEST[127] := 0 + RETURN DEST // 128b vector +} +FOR i := 0 to 3 + IF Imm8[0] == 0 + TEMP1 := b.m128[i].qword[0] + ELSE + TEMP1 := b.m128[i].qword[1] + FI + IF Imm8[4] == 0 + TEMP2 := c.m128[i].qword[0] + ELSE + TEMP2 := c.m128[i].qword[1] + FI + dst.m128[i] := PCLMUL128(TEMP1, TEMP2) +ENDFOR +dst[MAX:512] := 0 + + +

immintrin.h

+ + + Integer + AVX512VL + VPCLMULQDQ + Application-Targeted + + + + + Carry-less multiplication of one quadword of + 'b' by one quadword of 'c', stores + the 128-bit result in 'dst'. The immediate 'Imm8' is + used to determine which quadwords of 'b' + and 'c' should be used. + +DEFINE PCLMUL128(X,Y) { + FOR i := 0 to 63 + TMP[i] := X[ 0 ] and Y[ i ] + FOR j := 1 to i + TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ]) + ENDFOR + DEST[ i ] := TMP[ i ] + ENDFOR + FOR i := 64 to 126 + TMP[i] := 0 + FOR j := i - 63 to 63 + TMP[i] := TMP[i] xor (X[ j ] and Y[ i - j ]) + ENDFOR + DEST[ i ] := TMP[ i ] + ENDFOR + DEST[127] := 0 + RETURN DEST // 128b vector +} +FOR i := 0 to 1 + IF Imm8[0] == 0 + TEMP1 := b.m128[i].qword[0] + ELSE + TEMP1 := b.m128[i].qword[1] + FI + IF Imm8[4] == 0 + TEMP2 := c.m128[i].qword[0] + ELSE + TEMP2 := c.m128[i].qword[1] + FI + dst.m128[i] := PCLMUL128(TEMP1, TEMP2) +ENDFOR +dst[MAX:256] := 0 + + +

immintrin.h

+ + + Flag + WAITPKG + Miscellaneous + + + + Directs the processor to enter an implementation-dependent optimized state until the TSC reaches or exceeds the value specified in "counter". Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF). + +

immintrin.h

+ + + Flag + WAITPKG + Miscellaneous + + + + Directs the processor to enter an implementation-dependent optimized state while monitoring a range of addresses. The instruction wakes up when the TSC reaches or exceeds the value specified in "counter" (if the monitoring hardware did not trigger beforehand). Bit 0 of "ctrl" selects between a lower power (cleared) or faster wakeup (set) optimized state. Returns the carry flag (CF). + +

immintrin.h

+ + + WAITPKG + Miscellaneous + + + Sets up a linear address range to be + monitored by hardware and activates the + monitor. The address range should be a writeback + memory caching type. The address is + contained in "a". + +

immintrin.h

+ + + WBNOINVD + Miscellaneous + + + Write back and do not flush internal caches. + Initiate writing-back without flushing of external + caches. + +

immintrin.h

+ + + XSAVE + OS-Targeted + + + Copy up to 64-bits from the value of the extended control register (XCR) specified by "a" into "dst". Currently only XFEATURE_ENABLED_MASK XCR is supported. + dst[63:0] := XCR[a] + + +

immintrin.h

+ + + XSAVE + OS-Targeted + + + + Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary. + st_mask := mem_addr.HEADER.XSTATE_BV[62:0] +FOR i := 0 to 62 + IF (rs_mask[i] AND XCR0[i]) + IF st_mask[i] + CASE (i) OF + 0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU] + 1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE] + DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i] + ESAC + ELSE + // ProcessorExtendedState := Processor Supplied Values + CASE (i) OF + 1: MXCSR := mem_addr.FPUSSESave_Area[SSE] + ESAC + FI + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + + XSAVE + OS-Targeted + + + + Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. + mask[62:0] := save_mask[62:0] AND XCR0[62:0] +FOR i := 0 to 62 + IF mask[i] + CASE (i) OF + 0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU] + 1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE] + DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i] + ESAC + mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i] + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + + XSAVE + XSAVEOPT + OS-Targeted + + + + Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE instruction. + mask[62:0] := save_mask[62:0] AND XCR0[62:0] +FOR i := 0 to 62 + IF mask[i] + CASE (i) OF + 0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU] + 1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE] + 2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM] + DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i] + ESAC + mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i] + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + + XSAVE + XSAVEOPT + OS-Targeted + + + + Perform a full or partial save of the enabled processor states to memory at "mem_addr". State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. The hardware may optimize the manner in which data is saved. The performance of this instruction will be equal to or better than using the XSAVE64 instruction. + mask[62:0] := save_mask[62:0] AND XCR0[62:0] +FOR i := 0 to 62 + IF mask[i] + CASE (i) OF + 0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU] + 1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE] + 2: mem_addr.EXT_SAVE_Area2[YMM] := ProcessorState[YMM] + DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i] + ESAC + mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i] + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + + XSAVE + OS-Targeted + + + + Copy 64-bits from "val" to the extended control register (XCR) specified by "a". Currently only XFEATURE_ENABLED_MASK XCR is supported. + +XCR[a] := val[63:0] + + +

immintrin.h

+ + + XSAVE + XSAVEC + OS-Targeted + + + + Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsavec differs from xsave in that it uses compaction and that it may use init optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. + mask[62:0] := save_mask[62:0] AND XCR0[62:0] +FOR i := 0 to 62 + IF mask[i] + CASE (i) OF + 0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU] + 1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE] + DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i] + ESAC + mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i] + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + + XSAVE + XSS + OS-Targeted + + + + Perform a full or partial save of the enabled processor states to memory at "mem_addr"; xsaves differs from xsave in that it can save state components corresponding to bits set in IA32_XSS MSR and that it may use the modified optimization. State is saved based on bits [62:0] in "save_mask" and "XCR0". "mem_addr" must be aligned on a 64-byte boundary. + mask[62:0] := save_mask[62:0] AND XCR0[62:0] +FOR i := 0 to 62 + IF mask[i] + CASE (i) OF + 0: mem_addr.FPUSSESave_Area[FPU] := ProcessorState[x87_FPU] + 1: mem_addr.FPUSSESaveArea[SSE] := ProcessorState[SSE] + DEFAULT: mem_addr.Ext_Save_Area[i] := ProcessorState[i] + ESAC + mem_addr.HEADER.XSTATE_BV[i] := INIT_FUNCTION[i] + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + + XSAVE + XSS + OS-Targeted + + + + Perform a full or partial restore of the enabled processor states using the state information stored in memory at "mem_addr". xrstors differs from xrstor in that it can restore state components corresponding to bits set in the IA32_XSS MSR; xrstors cannot restore from an xsave area in which the extended region is in the standard form. State is restored based on bits [62:0] in "rs_mask", "XCR0", and "mem_addr.HEADER.XSTATE_BV". "mem_addr" must be aligned on a 64-byte boundary. + st_mask := mem_addr.HEADER.XSTATE_BV[62:0] +FOR i := 0 to 62 + IF (rs_mask[i] AND XCR0[i]) + IF st_mask[i] + CASE (i) OF + 0: ProcessorState[x87_FPU] := mem_addr.FPUSSESave_Area[FPU] + 1: ProcessorState[SSE] := mem_addr.FPUSSESaveArea[SSE] + DEFAULT: ProcessorState[i] := mem_addr.Ext_Save_Area[i] + ESAC + ELSE + // ProcessorExtendedState := Processor Supplied Values + CASE (i) OF + 1: MXCSR := mem_addr.FPUSSESave_Area[SSE] + ESAC + FI + FI + i := i + 1 +ENDFOR + + +

immintrin.h

+ + \ No newline at end of file -- cgit v1.2.3